From nobody Fri Apr 10 12:52:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B612C4332F for ; Mon, 3 Oct 2022 07:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229872AbiJCHOV (ORCPT ); Mon, 3 Oct 2022 03:14:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbiJCHNR (ORCPT ); Mon, 3 Oct 2022 03:13:17 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E6034333B; Mon, 3 Oct 2022 00:12:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1AC81B80E65; Mon, 3 Oct 2022 07:12:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47954C433D6; Mon, 3 Oct 2022 07:12:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1664781161; bh=EMX1hIXsoJuNfe/hfMW8cmBmiDYk7jG0rtirzCg1I54=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=z0y9Ne3bg5xcW2Z1uukKGj/uEq4HDNQfUj/8OwyL8iPvcuA/t1APIZ71yBewE6vul 3mYRE8zQNlths1mJbRq8lUb/d+6LgCJlo6GxHlYHRSvI5ePsKOyj6lai6YG5OhiV8E v5CMw1LjpwbxUQKidgIkGJkUvI6QeHDn7l6OfkBc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Syed Nayyar Waris , David Laight , Linus Walleij , William Breathitt Gray , Sasha Levin Subject: [PATCH 5.19 004/101] counter: 104-quad-8: Utilize iomap interface Date: Mon, 3 Oct 2022 09:10:00 +0200 Message-Id: <20221003070724.611391952@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221003070724.490989164@linuxfoundation.org> References: <20221003070724.490989164@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: William Breathitt Gray [ Upstream commit b6e9cded90d46b1066a1ca260d8b5ecf67787aba ] This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Link: https://lore.kernel.org/r/861c003318dce3d2bef4061711643bb04f5ec14f.16= 52201921.git.william.gray@linaro.org Cc: Syed Nayyar Waris Suggested-by: David Laight Reviewed-by: Linus Walleij Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/e971b897cacfac4cb2eca478f5533d2875f5cadd.16= 57813472.git.william.gray@linaro.org Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2bc54aaa65d2 ("counter: 104-quad-8: Fix skipped IRQ lines du= ring events configuration") Signed-off-by: Sasha Levin --- drivers/counter/104-quad-8.c | 169 ++++++++++++++++++----------------- 1 file changed, 89 insertions(+), 80 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index a17e51d65aca..43dde9abfdcf 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -63,7 +63,7 @@ struct quad8 { unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; - unsigned int base; + void __iomem *base; }; =20 #define QUAD8_REG_INTERRUPT_STATUS 0x10 @@ -118,8 +118,8 @@ static int quad8_signal_read(struct counter_device *cou= nter, if (signal->id < 16) return -EINVAL; =20 - state =3D inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) - & BIT(signal->id - 16); + state =3D ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) & + BIT(signal->id - 16); =20 *level =3D (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; =20 @@ -130,14 +130,14 @@ static int quad8_count_read(struct counter_device *co= unter, struct counter_count *count, u64 *val) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned int flags; unsigned int borrow; unsigned int carry; unsigned long irqflags; int i; =20 - flags =3D inb(base_offset + 1); + flags =3D ioread8(base_offset + 1); borrow =3D flags & QUAD8_FLAG_BT; carry =3D !!(flags & QUAD8_FLAG_CT); =20 @@ -147,11 +147,11 @@ static int quad8_count_read(struct counter_device *co= unter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer; transfer Counter to Output Latch */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, - base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, + base_offset + 1); =20 for (i =3D 0; i < 3; i++) - *val |=3D (unsigned long)inb(base_offset) << (8 * i); + *val |=3D (unsigned long)ioread8(base_offset) << (8 * i); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -162,7 +162,7 @@ static int quad8_count_write(struct counter_device *cou= nter, struct counter_count *count, u64 val) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned long irqflags; int i; =20 @@ -173,27 +173,27 @@ static int quad8_count_write(struct counter_device *c= ounter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Counter can only be set via Preset Register */ for (i =3D 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); =20 /* Transfer Preset Register to Counter */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set Preset Register back to original value */ val =3D priv->preset[count->id]; for (i =3D 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); =20 /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -246,7 +246,7 @@ static int quad8_function_write(struct counter_device *= counter, unsigned int *const quadrature_mode =3D priv->quadrature_mode + id; unsigned int *const scale =3D priv->quadrature_scale + id; unsigned int *const synchronous_mode =3D priv->synchronous_mode + id; - const int base_offset =3D priv->base + 2 * id + 1; + void __iomem *const base_offset =3D priv->base + 2 * id + 1; unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; @@ -266,7 +266,7 @@ static int quad8_function_write(struct counter_device *= counter, if (*synchronous_mode) { *synchronous_mode =3D 0; /* Disable synchronous function mode */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); } } else { *quadrature_mode =3D 1; @@ -292,7 +292,7 @@ static int quad8_function_write(struct counter_device *= counter, } =20 /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -305,10 +305,10 @@ static int quad8_direction_read(struct counter_device= *counter, { const struct quad8 *const priv =3D counter_priv(counter); unsigned int ud_flag; - const unsigned int flag_addr =3D priv->base + 2 * count->id + 1; + void __iomem *const flag_addr =3D priv->base + 2 * count->id + 1; =20 /* U/D flag: nonzero =3D up, zero =3D down */ - ud_flag =3D inb(flag_addr) & QUAD8_FLAG_UD; + ud_flag =3D ioread8(flag_addr) & QUAD8_FLAG_UD; =20 *direction =3D (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; @@ -402,7 +402,7 @@ static int quad8_events_configure(struct counter_device= *counter) struct counter_event_node *event_node; unsigned int next_irq_trigger; unsigned long ior_cfg; - unsigned long base_offset; + void __iomem *base_offset; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 @@ -438,13 +438,13 @@ static int quad8_events_configure(struct counter_devi= ce *counter) priv->preset_enable[event_node->channel] << 1 | priv->irq_trigger[event_node->channel] << 3; base_offset =3D priv->base + 2 * event_node->channel + 1; - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); =20 /* Enable IRQ line */ irq_enabled |=3D BIT(event_node->channel); } =20 - outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -508,7 +508,7 @@ static int quad8_index_polarity_set(struct counter_devi= ce *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; - const int base_offset =3D priv->base + 2 * channel_id + 1; + void __iomem *const base_offset =3D priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg =3D index_polarity << 1; =20 @@ -519,7 +519,7 @@ static int quad8_index_polarity_set(struct counter_devi= ce *counter, priv->index_polarity[channel_id] =3D index_polarity; =20 /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -549,7 +549,7 @@ static int quad8_synchronous_mode_set(struct counter_de= vice *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; - const int base_offset =3D priv->base + 2 * channel_id + 1; + void __iomem *const base_offset =3D priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg =3D synchronous_mode; =20 @@ -566,7 +566,7 @@ static int quad8_synchronous_mode_set(struct counter_de= vice *counter, priv->synchronous_mode[channel_id] =3D synchronous_mode; =20 /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -614,7 +614,7 @@ static int quad8_count_mode_write(struct counter_device= *counter, struct quad8 *const priv =3D counter_priv(counter); unsigned int count_mode; unsigned int mode_cfg; - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; unsigned long irqflags; =20 /* Map Generic Counter count mode to 104-QUAD-8 count mode */ @@ -648,7 +648,7 @@ static int quad8_count_mode_write(struct counter_device= *counter, mode_cfg |=3D (priv->quadrature_scale[count->id] + 1) << 3; =20 /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -669,7 +669,7 @@ static int quad8_count_enable_write(struct counter_devi= ce *counter, struct counter_count *count, u8 enable) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned long irqflags; unsigned int ior_cfg; =20 @@ -681,7 +681,7 @@ static int quad8_count_enable_write(struct counter_devi= ce *counter, priv->irq_trigger[count->id] << 3; =20 /* Load I/O control configuration */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -697,9 +697,9 @@ static int quad8_error_noise_get(struct counter_device = *counter, struct counter_count *count, u32 *noise_error) { const struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; =20 - *noise_error =3D !!(inb(base_offset) & QUAD8_FLAG_E); + *noise_error =3D !!(ioread8(base_offset) & QUAD8_FLAG_E); =20 return 0; } @@ -717,17 +717,17 @@ static int quad8_count_preset_read(struct counter_dev= ice *counter, static void quad8_preset_register_set(struct quad8 *const priv, const int = id, const unsigned int preset) { - const unsigned int base_offset =3D priv->base + 2 * id; + void __iomem *const base_offset =3D priv->base + 2 * id; int i; =20 priv->preset[id] =3D preset; =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set Preset Register */ for (i =3D 0; i < 3; i++) - outb(preset >> (8 * i), base_offset); + iowrite8(preset >> (8 * i), base_offset); } =20 static int quad8_count_preset_write(struct counter_device *counter, @@ -816,7 +816,7 @@ static int quad8_count_preset_enable_write(struct count= er_device *counter, u8 preset_enable) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; unsigned long irqflags; unsigned int ior_cfg; =20 @@ -831,7 +831,7 @@ static int quad8_count_preset_enable_write(struct count= er_device *counter, priv->irq_trigger[count->id] << 3; =20 /* Load I/O control configuration to Input / Output Control Register */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -858,7 +858,7 @@ static int quad8_signal_cable_fault_read(struct counter= _device *counter, } =20 /* Logic 0 =3D cable fault */ - status =3D inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + status =3D ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -899,7 +899,8 @@ static int quad8_signal_cable_fault_enable_write(struct= counter_device *counter, /* Enable is active low in Differential Encoder Cable Status register */ cable_fault_enable =3D ~priv->cable_fault_enable; =20 - outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(cable_fault_enable, + priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -923,7 +924,7 @@ static int quad8_signal_fck_prescaler_write(struct coun= ter_device *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id / 2; - const int base_offset =3D priv->base + 2 * channel_id; + void __iomem *const base_offset =3D priv->base + 2 * channel_id; unsigned long irqflags; =20 spin_lock_irqsave(&priv->lock, irqflags); @@ -931,12 +932,12 @@ static int quad8_signal_fck_prescaler_write(struct co= unter_device *counter, priv->fck_prescaler[channel_id] =3D prescaler; =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set filter clock factor */ - outb(prescaler, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); + iowrite8(prescaler, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -1084,12 +1085,12 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) { struct counter_device *counter =3D private; struct quad8 *const priv =3D counter_priv(counter); - const unsigned long base =3D priv->base; + void __iomem *const base =3D priv->base; unsigned long irq_status; unsigned long channel; u8 event; =20 - irq_status =3D inb(base + QUAD8_REG_INTERRUPT_STATUS); + irq_status =3D ioread8(base + QUAD8_REG_INTERRUPT_STATUS); if (!irq_status) return IRQ_NONE; =20 @@ -1118,17 +1119,43 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) } =20 /* Clear pending interrupts on device */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); =20 return IRQ_HANDLED; } =20 +static void quad8_init_counter(void __iomem *const base_offset) +{ + unsigned long i; + + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset filter clock factor */ + iowrite8(0, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset Preset Register */ + for (i =3D 0; i < 3; i++) + iowrite8(0x00, base_offset); + /* Reset Borrow, Carry, Compare, and Sign flags */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + /* Reset Error flag */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + /* Binary encoding; Normal count; non-quadrature mode */ + iowrite8(QUAD8_CTR_CMR, base_offset + 1); + /* Disable A and B inputs; preset on index; FLG1 as Carry */ + iowrite8(QUAD8_CTR_IOR, base_offset + 1); + /* Disable index function; negative index polarity */ + iowrite8(QUAD8_CTR_IDR, base_offset + 1); +} + static int quad8_probe(struct device *dev, unsigned int id) { struct counter_device *counter; struct quad8 *priv; - int i, j; - unsigned int base_offset; + unsigned long i; int err; =20 if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { @@ -1142,6 +1169,10 @@ static int quad8_probe(struct device *dev, unsigned = int id) return -ENOMEM; priv =3D counter_priv(counter); =20 + priv->base =3D devm_ioport_map(dev, base[id], QUAD8_EXTENT); + if (!priv->base) + return -ENOMEM; + /* Initialize Counter device and driver data */ counter->name =3D dev_name(dev); counter->parent =3D dev; @@ -1150,43 +1181,21 @@ static int quad8_probe(struct device *dev, unsigned= int id) counter->num_counts =3D ARRAY_SIZE(quad8_counts); counter->signals =3D quad8_signals; counter->num_signals =3D ARRAY_SIZE(quad8_signals); - priv->base =3D base[id]; =20 spin_lock_init(&priv->lock); =20 /* Reset Index/Interrupt Register */ - outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT); /* Reset all counters and disable interrupt function */ - outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP); /* Set initial configuration for all counters */ - for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) { - base_offset =3D base[id] + 2 * i; - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset filter clock factor */ - outb(0, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset Preset Register */ - for (j =3D 0; j < 3; j++) - outb(0x00, base_offset); - /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); - /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - /* Binary encoding; Normal count; non-quadrature mode */ - outb(QUAD8_CTR_CMR, base_offset + 1); - /* Disable A and B inputs; preset on index; FLG1 as Carry */ - outb(QUAD8_CTR_IOR, base_offset + 1); - /* Disable index function; negative index polarity */ - outb(QUAD8_CTR_IDR, base_offset + 1); - } + for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) + quad8_init_counter(priv->base + 2 * i); /* Disable Differential Encoder Cable Status for all channels */ - outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); /* Enable all counters and enable interrupt function */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, + priv->base + QUAD8_REG_CHAN_OP); =20 err =3D devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, IRQF_SHARED, counter->name, counter); --=20 2.35.1