From nobody Sun Dec 14 06:19:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 485EDC4332F for ; Mon, 3 Oct 2022 07:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbiJCH3T (ORCPT ); Mon, 3 Oct 2022 03:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230515AbiJCH2D (ORCPT ); Mon, 3 Oct 2022 03:28:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D036AEE39; Mon, 3 Oct 2022 00:19:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 90FBA60FA6; Mon, 3 Oct 2022 07:19:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5D1DC433D6; Mon, 3 Oct 2022 07:19:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1664781570; bh=88y6V89ZhIC2mAYvMvB8/89AVze1JwN4vvrzk+RVBGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L7B3yMshQ3UDwSmjtGghGQkLC+szmeaWdE8x4pi2cyhyBipCz967QRsqPThQ7wjeF YvPVUiYZCSGqN606xg49kgg1nkUBdqFXp85+U3m/NRJVJRRB8DaNyWoVYsRjQl95ms jdtMEN8vintE5A3PRW3Ov5uGuq7OQr/d6jP6M+38= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Han Xu , Fabio Estevam , Abel Vesa , Stephen Boyd , Sasha Levin Subject: [PATCH 5.15 68/83] clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks Date: Mon, 3 Oct 2022 09:11:33 +0200 Message-Id: <20221003070723.699047440@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221003070721.971297651@linuxfoundation.org> References: <20221003070721.971297651@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Han Xu [ Upstream commit b1ff1bfe81e763420afd5f3f25f0b3cbfd97055c ] There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag should not be used. For instance, the default parent clock for QSPI is pll2_bus, which is also the parent clock for quite a few modules, such as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system hang due to pll2_bus rate changed. Fixes: f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API") Signed-off-by: Han Xu Link: https://lore.kernel.org/r/20220915150959.3646702-1-han.xu@nxp.com Tested-by: Fabio Estevam Reviewed-by: Abel Vesa Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/imx/clk-imx6sx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index fc1bd23d4583..598f3cf4eba4 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -280,13 +280,13 @@ static void __init imx6sx_clocks_init(struct device_n= ode *ccm_node) hws[IMX6SX_CLK_SSI3_SEL] =3D imx_clk_hw_mux("ssi3_sel", = base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); hws[IMX6SX_CLK_SSI2_SEL] =3D imx_clk_hw_mux("ssi2_sel", = base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); hws[IMX6SX_CLK_SSI1_SEL] =3D imx_clk_hw_mux("ssi1_sel", = base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - hws[IMX6SX_CLK_QSPI1_SEL] =3D imx_clk_hw_mux_flags("qspi1_sel", = base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT= ); + hws[IMX6SX_CLK_QSPI1_SEL] =3D imx_clk_hw_mux("qspi1_sel", = base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); hws[IMX6SX_CLK_PERCLK_SEL] =3D imx_clk_hw_mux("perclk_sel", = base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); hws[IMX6SX_CLK_VID_SEL] =3D imx_clk_hw_mux("vid_sel", = base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels)); hws[IMX6SX_CLK_ESAI_SEL] =3D imx_clk_hw_mux("esai_sel", = base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6SX_CLK_CAN_SEL] =3D imx_clk_hw_mux("can_sel", = base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); hws[IMX6SX_CLK_UART_SEL] =3D imx_clk_hw_mux("uart_sel", = base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); - hws[IMX6SX_CLK_QSPI2_SEL] =3D imx_clk_hw_mux_flags("qspi2_sel", = base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT= ); + hws[IMX6SX_CLK_QSPI2_SEL] =3D imx_clk_hw_mux("qspi2_sel", = base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels)); hws[IMX6SX_CLK_SPDIF_SEL] =3D imx_clk_hw_mux("spdif_sel", = base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6SX_CLK_AUDIO_SEL] =3D imx_clk_hw_mux("audio_sel", = base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6SX_CLK_ENET_PRE_SEL] =3D imx_clk_hw_mux("enet_pre_sel", = base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels)= ); --=20 2.35.1