From nobody Mon Apr 6 14:57:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55918C433F5 for ; Sun, 2 Oct 2022 06:45:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbiJBGpz (ORCPT ); Sun, 2 Oct 2022 02:45:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229461AbiJBGpt (ORCPT ); Sun, 2 Oct 2022 02:45:49 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 859782CDE4 for ; Sat, 1 Oct 2022 23:45:46 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id rk17so16551386ejb.1 for ; Sat, 01 Oct 2022 23:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+EFb6uk4cTnqBeI+5KKFVfi8qmpv//hil6I+XjIEg10=; b=Z6eZABtXZW25w/5ZyMrjoGibSALBRFTBPOZ3m9ciR8K5cg5YYtOx+uYUCdFWVGG7vC Fj8IrV/vXJ8t6J+fMB+I2+mkQIsc0hz6XEZxe/ffAXYEafz21v/MVLnMLO77sabS2aSm ma9lsFZUE903KWzEhReXmALwvDgy4P3ehuLBw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+EFb6uk4cTnqBeI+5KKFVfi8qmpv//hil6I+XjIEg10=; b=rmoVKZW0Pl1vRIR/Em5b+IG64VZdAm4o4RONk95SyB/+F4omtguemUIeHsG8iDe8qI Nh3OHWwFKZmGDsJsCAyApP1xrQRxdbRl+AtxLsviScBeM7EMAi8EQW8F18ye72e+KUBC YUJt8E7Te2Cho4vIOtyB7ytjmhfrhz/8wpu2u7eiAIeWC+te0fImKB5BNWxcB/tIYZ5R NVV7fXPhs9CX1UNFHCWhVGi4R1r7fOKtuQIk0eNuIlMIU2wSLUt0KIGvfD4LZ+g7M9Gr 7u9dJM36PXqnllYqlAS1wy0uE/pd7xRgM97f8AZN3Btb87qISQa3cqnxq46SaC2lGg2Y KYyQ== X-Gm-Message-State: ACrzQf1+6o8PtnyAFfhOiOQnjgKFpNqtDMqz+/I9jefTtu3SabAHKtg6 8KVeI9Ucfy6KvdQv3lRliownWw== X-Google-Smtp-Source: AMsMyM4B5NnmV+Vv6ol70KZMuL8JEVXI/URE4cg0VGwaJQnYUbGUUGOKtgaodi64X9B7RZP0ZmTX1Q== X-Received: by 2002:a17:907:160d:b0:782:bc5d:162e with SMTP id hb13-20020a170907160d00b00782bc5d162emr11502660ejc.291.1664693145088; Sat, 01 Oct 2022 23:45:45 -0700 (PDT) Received: from panicking.. ([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:44 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie , Daniel Vetter Cc: Kishon Vijay Abraham I , Vinod Koul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com Subject: [RFC PATCH 1/4] phy: add PHY_MODE_TTL Date: Sun, 2 Oct 2022 08:45:37 +0200 Message-Id: <20221002064540.2500257-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are combo phys out there that can be switched between doing dsi, lvds, and ttl. So add a mode definition for it. Signed-off-by: Michael Trimarchi --- include/linux/phy/phy.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b1413757fcc3..87ae8c27ec57 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -42,7 +42,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_TTL }; =20 enum phy_media { --=20 2.34.1 From nobody Mon Apr 6 14:57:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCEB5C433F5 for ; Sun, 2 Oct 2022 06:46:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229617AbiJBGp7 (ORCPT ); Sun, 2 Oct 2022 02:45:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbiJBGpu (ORCPT ); Sun, 2 Oct 2022 02:45:50 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FACC2E6B2 for ; Sat, 1 Oct 2022 23:45:48 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id 13so16564507ejn.3 for ; Sat, 01 Oct 2022 23:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=I6XMIDzmAb5OEYRQrNrBJ64J1RkMPb1xdg1o6LLrqS4=; b=kdPlUwALYdNbkW9cx2XLVNwgOxrzhu3xLLiNM5FmcdjmtgSxDjZiXivE9cURSlKI9G THB25Gxkx5t8suAAn8LL2pI7YADY+GVOgVmXbiI2zDF9bH2yHej+i0+hvqZxj0Akp/p5 uh/tBzNaQX2p0eFbQeZw5FnMylVKKnY0W1Xc4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=I6XMIDzmAb5OEYRQrNrBJ64J1RkMPb1xdg1o6LLrqS4=; b=uVEbYBiw3cdRQMJvQNdFCPb1BNFRP+2e6kux27f5WvR0IWHF2fnWD+tswOrqNTq5Ec tJTFG1ByZKZQ+0fvy96auDAoS2c5gy2bT4LEQZhZ50Qy8Vdp9VN9/4OMdaTRN6xSlvdv iKDZWUgD2bdeZaYP2mzB0kUOUaMplwjGYdweR2PaW7QHddnpbLXPmJPOaUPBNRrNq0Ud A1T835/AQcY56RHWXyNfaXsWjcH8JTFKJr0TCQj3TrkffDq3SwOD1TSgX0PO5F7NvGAt 6QNCf+GaOWobjeW4CjBLnNS98U4oMrGKQX8+M3sDmzcWtnlG+jJsoLGaLUj3yWVoF5PP ky8Q== X-Gm-Message-State: ACrzQf1/svjZ1glrHWL5Je+JoPxJExkrt/1FLonravtyv1i2nXyq2GMy iNtSfl2NuLC/XA1FApiYNmAg+w== X-Google-Smtp-Source: AMsMyM42Y13+9SuPHtB+8bbihrWVsma1thKzuBn20iHav0eL1jLmBw0Y9w2/3o+fg6AJtnqVC042IA== X-Received: by 2002:a17:907:2c67:b0:77d:740a:e9b1 with SMTP id ib7-20020a1709072c6700b0077d740ae9b1mr11198850ejc.614.1664693146999; Sat, 01 Oct 2022 23:45:46 -0700 (PDT) Received: from panicking.. ([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:46 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie , Daniel Vetter Cc: Kishon Vijay Abraham I , Vinod Koul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com Subject: [RFC PATCH 2/4] phy: rockchip: Add inno_is_valid_phy_mode Date: Sun, 2 Oct 2022 08:45:38 +0200 Message-Id: <20221002064540.2500257-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The function is used to avoid to enable clock on the hardware if the mode requested is invalid Signed-off-by: Michael Trimarchi --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-dsidphy.c index 630e01b5c19b..644cf73cfd53 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -217,6 +217,20 @@ static void phy_update_bits(struct inno_dsidphy *inno, writel(tmp, inno->phy_base + reg); } =20 +static int inno_is_valid_phy_mode(struct inno_dsidphy *inno) +{ + switch (inno->mode) { + case PHY_MODE_MIPI_DPHY: + break; + case PHY_MODE_LVDS: + break; + default: + return -EINVAL; + } + + return 0; +}; + static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, unsigned long rate) { @@ -495,6 +509,11 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_= dsidphy *inno) static int inno_dsidphy_power_on(struct phy *phy) { struct inno_dsidphy *inno =3D phy_get_drvdata(phy); + int ret =3D 0; + + ret =3D inno_is_valid_phy_mode(inno); + if (ret) + return ret; =20 clk_prepare_enable(inno->pclk_phy); clk_prepare_enable(inno->ref_clk); --=20 2.34.1 From nobody Mon Apr 6 14:57:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3739C43217 for ; Sun, 2 Oct 2022 06:46:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229636AbiJBGqC (ORCPT ); Sun, 2 Oct 2022 02:46:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229441AbiJBGpv (ORCPT ); Sun, 2 Oct 2022 02:45:51 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F1642ED4C for ; Sat, 1 Oct 2022 23:45:50 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id y100so10274720ede.6 for ; Sat, 01 Oct 2022 23:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=riE4lHaMXHSULeXJrv4hqGT03pNNa5PlNR8v7ryuD60=; b=rsLBLijZiEznSvV9r7o+s1+gbRqyxGcXwwvhnVSRKOyAThP1CQ4D8FRgo4h14v4OuB N4/KPuwLrtJJi5use8++OnPnxML8KbamdgvX+5FsTzDlbW51iEHl5Y3aAYzPpvNV595b ClEQiXJ0dzWPUKO1e6FchUS4Cn6jE7iHF9xGA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=riE4lHaMXHSULeXJrv4hqGT03pNNa5PlNR8v7ryuD60=; b=pDMMj9Crva44PI2jq2XfZkvjP08J0KzT/QR8WKO42cS6ayq2vLZk0UiFAEQInIv5UW 8nWZenjxhnvDDC2QVYrD/2i7eSurTQhitHU5hPhTYJTi9YFV/CC1JwFzEdA47lOPJIqB YG0jG60Z9HRRfhUgAxGpBGhM9KmjnF83nDcv0Lk2/ai0lgNBvPSxIHMREMye4uwBgBwJ oQU2OtGexPPUgnF3C8nXVpTjKAFDfCjO3dVipKFveGp5BLMyomo5HA3UwEdni9MzcZmT P+YeiiRYD8DZDOFJs20FF4E2B6JKjIu46qDaGfqh8gTMVUEeyVFSeUHbN4WQ9/UjMGPV bvUA== X-Gm-Message-State: ACrzQf245gpy0ErhqWWWANjk/ukgVTwbOBSGb7PqJ8uQvHq1AVHy8qOO KANHNvBxkKAnw869Q3sOBjkaUg== X-Google-Smtp-Source: AMsMyM5CVyyAdanMhvOm71Pk3KKLbggnhE3t2Sd+hxkylpEi/NEYUXHm12kfOKY78cBjLZ9qp3zzKg== X-Received: by 2002:a05:6402:448c:b0:457:52eb:b57e with SMTP id er12-20020a056402448c00b0045752ebb57emr14243393edb.178.1664693148777; Sat, 01 Oct 2022 23:45:48 -0700 (PDT) Received: from panicking.. ([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:48 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie , Daniel Vetter Cc: Kishon Vijay Abraham I , Vinod Koul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com Subject: [RFC PATCH 3/4] phy: rockchip: Implement TTY phy mode Date: Sun, 2 Oct 2022 08:45:39 +0200 Message-Id: <20221002064540.2500257-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The rockchip phy can be programmed in 3 modes: - dsi - lvds - ttl For instance in px30 there are two sets of rgb interface pins m0 and m1. The logic can go outside from the VOP using m0 set or go outside using the m1 set and the ttl logic enable. There are combination where a set of pin can be taken from m1 and m0 where all the two path are enabled. dsi and ttl enable share one register in their register area. Simple implementation is overlap the area where we want access the register Signed-off-by: Michael Trimarchi --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-dsidphy.c index 644cf73cfd53..0af50d2e0402 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -217,6 +217,17 @@ static void phy_update_bits(struct inno_dsidphy *inno, writel(tmp, inno->phy_base + reg); } =20 +static void host_update_bits(struct inno_dsidphy *inno, + u32 reg, u32 mask, u32 val) +{ + unsigned int tmp, orig; + + orig =3D readl(inno->host_base + reg); + tmp =3D orig & ~mask; + tmp |=3D val & mask; + writel(tmp, inno->host_base + reg); +} + static int inno_is_valid_phy_mode(struct inno_dsidphy *inno) { switch (inno->mode) { @@ -224,6 +235,10 @@ static int inno_is_valid_phy_mode(struct inno_dsidphy = *inno) break; case PHY_MODE_LVDS: break; + case PHY_MODE_TTL: + if (IS_ERR(inno->host_base)) + return -EINVAL; + break; default: return -EINVAL; } @@ -506,6 +521,32 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_= dsidphy *inno) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); } =20 +static void inno_dsidphy_ttl_mode_enable(struct inno_dsidphy *inno) +{ + /* Select TTL mode */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, + MODE_ENABLE_MASK, TTL_MODE_ENABLE); + /* Reset digital logic */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_ENABLE); + udelay(1); + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_DISABLE); + /* Enable digital logic */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, + LVDS_DIGITAL_INTERNAL_ENABLE_MASK, + LVDS_DIGITAL_INTERNAL_ENABLE); + /* Enable analog driver */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, + LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | + LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | + LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); + /* Enable for clk lane in TTL mode */ + host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); +} + static int inno_dsidphy_power_on(struct phy *phy) { struct inno_dsidphy *inno =3D phy_get_drvdata(phy); @@ -533,6 +574,9 @@ static int inno_dsidphy_power_on(struct phy *phy) case PHY_MODE_LVDS: inno_dsidphy_lvds_mode_enable(inno); break; + case PHY_MODE_TTL: + inno_dsidphy_ttl_mode_enable(inno); + break; default: return -EINVAL; } @@ -561,6 +605,10 @@ static int inno_dsidphy_power_off(struct phy *phy) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); =20 + /* Disable for clk lane in TTL mode */ + if (!IS_ERR(inno->host_base)) + host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); + pm_runtime_put(inno->dev); clk_disable_unprepare(inno->ref_clk); clk_disable_unprepare(inno->pclk_phy); @@ -576,6 +624,7 @@ static int inno_dsidphy_set_mode(struct phy *phy, enum = phy_mode mode, switch (mode) { case PHY_MODE_MIPI_DPHY: case PHY_MODE_LVDS: + case PHY_MODE_TTL: inno->mode =3D mode; break; default: @@ -630,6 +679,10 @@ static int inno_dsidphy_probe(struct platform_device *= pdev) if (IS_ERR(inno->phy_base)) return PTR_ERR(inno->phy_base); =20 + inno->host_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(inno->host_base)) + dev_warn(dev, "TTL mode is not supported\n"); + inno->ref_clk =3D devm_clk_get(dev, "ref"); if (IS_ERR(inno->ref_clk)) { ret =3D PTR_ERR(inno->ref_clk); --=20 2.34.1 From nobody Mon Apr 6 14:57:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AEC2C43217 for ; Sun, 2 Oct 2022 06:46:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229644AbiJBGqH (ORCPT ); Sun, 2 Oct 2022 02:46:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229549AbiJBGpx (ORCPT ); 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([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:50 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie , Daniel Vetter Cc: Kishon Vijay Abraham I , Vinod Koul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com Subject: [RFC PATCH 4/4] drm/rockchip: rgb: Add dphy connection to rgb output Date: Sun, 2 Oct 2022 08:45:40 +0200 Message-Id: <20221002064540.2500257-5-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dispite the commit 1f0f015151727, the rgb output has an option to allow to sent the output pin using the dsi/lvds/ttl logic. The only way to do and stay on the same design is let the rockchip_rgb block to grab the handle if it is present and enable it. The present of this handle depends on dts configuration I have a full working example with an hardware with mixed lines on direct logic and using the phy, with the follow dts example: panel: panel { compatible =3D "panel-dpi"; ... panel-timing { clock-frequency =3D <30000000>; ... }; port { panel_rgb_in: endpoint { remote-endpoint =3D <&vopb_out_rgb>; }; }; }; &vopb_out { vopb_out_rgb: endpoint@2 { reg =3D <2>; remote-endpoint =3D <&panel_rgb_in>; }; }; &vopb { status =3D "okay"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&lcdc_rgb_pins>; pinctrl-1 =3D <&lcdc_sleep_pins>; phys =3D <&dsi_dphy>; phy-names =3D "dphy"; }; Signed-off-by: Michael Trimarchi --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rock= chip/rockchip_rgb.c index 75eb7cca3d82..c725774a0f40 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include #include @@ -30,6 +31,7 @@ struct rockchip_rgb { struct drm_bridge *bridge; struct drm_encoder encoder; struct drm_connector connector; + struct phy *dphy; int output_mode; }; =20 @@ -168,6 +170,22 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *= dev, goto err_free_connector; } =20 + /* PHY */ + rgb->dphy =3D devm_phy_get(dev, "dphy"); + if (!IS_ERR(rgb->dphy)) { + ret =3D phy_init(rgb->dphy); + if (ret) + return ERR_PTR(ret); + + ret =3D phy_set_mode(rgb->dphy, PHY_MODE_TTL); + if (ret) + return ERR_PTR(ret); + + ret =3D phy_power_on(rgb->dphy); + if (ret) + return ERR_PTR(ret); + } + return rgb; =20 err_free_connector: --=20 2.34.1