From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C766AC433FE for ; Sat, 1 Oct 2022 03:26:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233310AbiJAD0j (ORCPT ); Fri, 30 Sep 2022 23:26:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233013AbiJADZj (ORCPT ); Fri, 30 Sep 2022 23:25:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78F71F80A2; Fri, 30 Sep 2022 20:17:49 -0700 (PDT) X-UUID: 80f56eadce3b4ba19370e56a9f848434-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3NxniVY0kLSVgBJbuv5v98YNltI4Zo9r6UkH/bKrbJk=; b=GNKaPHiyMhX8bDN448Fmgmyq4ThTh3EDCcUTif4GK35mQ2P/B2Q3jKq0TNvfcWn/7RfeLY37STgtpKg82Tu/Vqg1fNzrj6Hu/zTAyFSj9f81MvsAlNG8eqKTLr/eFItFjtr1chQ5gRL9Um/okDpaVrnm2pfQPgpTa1LgbQx35wg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:27de0494-0bf4-4456-983a-defcf79a9769,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:27de0494-0bf4-4456-983a-defcf79a9769,IP:0,URL :25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:3eaba107-1cee-4c38-b21b-a45f9682fdc0,B ulkID:2210011117469BOHLU59,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: 80f56eadce3b4ba19370e56a9f848434-20221001 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1050102750; Sat, 01 Oct 2022 11:17:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:42 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:41 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Tzung-Bi Shih , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , Subject: [PATCH v6, 1/8] dt-bindings: media: mediatek: vcodec: Adds encoder cores dt-bindings for mt8195 Date: Sat, 1 Oct 2022 11:17:30 +0800 Message-ID: <20221001031737.18266-2-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mt8195 has two H264 encoder hardware, which are named core0 and core1. The two encoder cores are independent, we can just enable one core to do encoding or enable both of them to achieve higher performance. We pick core0 as main device and core1 as its subdevice, it just a way to to manage the two encoder hardware, because they are two equal encoder hardware with the same function. Signed-off-by: Irui Wang --- .../media/mediatek,vcodec-encoder-core.yaml | 217 ++++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 1 - 2 files changed, 217 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec= -encoder-core.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r-core.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encod= er-core.yaml new file mode 100644 index 000000000000..1dda7d7908da --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.= yaml @@ -0,0 +1,217 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yam= l#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Video Encoder Accelerator With Multi Core + +maintainers: + - Irui Wang + +description: | + MediaTek Video Encoder is the video encoder hardware present in MediaTek + SoCs which supports high resolution encoding functionalities. To meet hi= gher + encoder performance, there will be one or more encoder hardware inside S= oC, + which named core0, core1, etc.. For example, mt8195 has two encoder hard= ware, + the two encoder cores block diagram, can check below. + -------------------------------------------------------------- + Input frame 0 1 2 3 4 5 6 + | | | | | | | + v | v | v | v + +-------+ | +-------+ | +-------+ | +-------+ + | core0 | | | core0 | | | core0 | | | core0 | + +-------+ | +-------+ | +-------+ | +-------+ + | | | | | | | + | v | v | v | + | +-------+ | +-------+ | +-------+ | + | | core1 | | | core1 | | | core1 | | + | +-------+ | +-------+ | +-------+ | + | | | | | | | + v v v v v v v + -------------------------------------------------------------- + core || index + \/ + +--------------------------------------------------+ + | core0/core1 | + | enable/disable power/clk/irq | + +--------------------------------------------------+ + -------------------------------------------------------------- + As above, there are two cores child devices, they are two encoder hardwa= re + which can encode input frames in order. When start encoding, input frame= 0 + will be encoded by core0, and input frame 1 can be encoded by core1 even= if + frame 0 has not been encoded done yet, after frame 0 encoded done, frame= 2 + will be encoded by core0, even input frames are encoded by core0 and odd + input frames are encoded by core1, these two encoder cores encode ench i= nput + frames in this overlapping manner. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-vcodec-enc + + reg: + maxItems: 1 + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + The node of system control processor (SCP), using + the remoteproc & rpmsg framework. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^venc-core@[0-9a-f]+$": + type: object + description: | + The video encoder core device node which should be added as subnodes= to + the main venc node, it represents a encoder hardware. + + properties: + compatible: + const: mediatek,mtk-venc-hw + + reg: + maxItems: 1 + + mediatek,hw-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current encoder core id. We use it to pick which one encoder core + will be used to encoding current input frame. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current = Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - mediatek,hw-id + - iommus + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - power-domains + + additionalProperties: false + +required: + - compatible + - reg + - mediatek,scp + - iommus + - interrupts + - clocks + - clock-names + - dma-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + venc: venc@1a020000 { + compatible =3D "mediatek,mt8195-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts =3D ; + clocks =3D <&vencsys CLK_VENC_VENC>; + clock-names =3D "clk_venc"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + venc-core@1b020000 { + compatible =3D "mediatek,mtk-venc-hw"; + reg =3D <0 0x1b020000 0 0x10000>; + mediatek,hw-id =3D <1>; + iommus =3D <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, + <&iommu_vpp M4U_PORT_L20_VENC_REC>, + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; + interrupts =3D ; + clocks =3D <&vencsys_core1 CLK_VENC_CORE1_VENC>; + clock-names =3D "clk_venc_core1"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index 32aee09aea33..f5f79efe3ba3 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -22,7 +22,6 @@ properties: - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc =20 reg: maxItems: 1 --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EC1DC433FE for ; Sat, 1 Oct 2022 03:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232287AbiJAD0z (ORCPT ); Fri, 30 Sep 2022 23:26:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232005AbiJADZl (ORCPT ); Fri, 30 Sep 2022 23:25:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54EA5F80A4; Fri, 30 Sep 2022 20:17:50 -0700 (PDT) X-UUID: e97db3c1121c430aab2360299c843be4-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nD2qa9frkMSGj6PytXf0V1URBD+ujDxdpHZfDVsjUxQ=; b=BSRsvhL94fovYxf+4eHQMy/Q4pJVHDUeRE//sfQAo0DZhwu4Yt7KWd7n2fG6y9F6LvcJBrwDFWpMd4WpGfbjTDFm/UX0zpPAH6htj2j+6KBOdRxRhNWyQje7pFb4F9TwFpoUjgfZ2w8ejgXs9GvUsqkG8MxskgfOreRkX3HXl3w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:d51d1420-53bc-484c-bb64-25d358a0c0da,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:8067afa3-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e97db3c1121c430aab2360299c843be4-20221001 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1596094693; Sat, 01 Oct 2022 11:17:44 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:43 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:42 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , "Tzung-Bi Shih" , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , "Irui Wang" , , , , , , Subject: [PATCH v6, 2/8] media: mediatek: vcodec: Enable venc dual core usage Date: Sat, 1 Oct 2022 11:17:31 +0800 Message-ID: <20221001031737.18266-3-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds new property to indicate whether the encoder has multiple cores. Use of_platform_populate to probe each venc cores, the core device can use the init_clk/request_irq helper to initialize their own power/clk/irq. Signed-off-by: Irui Wang --- .../media/platform/mediatek/vcodec/Makefile | 4 +- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 12 ++ .../mediatek/vcodec/mtk_vcodec_enc_drv.c | 6 + .../mediatek/vcodec/mtk_vcodec_enc_hw.c | 136 ++++++++++++++++++ .../mediatek/vcodec/mtk_vcodec_enc_hw.h | 36 +++++ 5 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_h= w.c create mode 100644 drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_h= w.h diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/medi= a/platform/mediatek/vcodec/Makefile index 93e7a343b5b0..e150b3dbd15c 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -3,7 +3,8 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) +=3D mtk-vcodec-dec.o \ mtk-vcodec-enc.o \ mtk-vcodec-common.o \ - mtk-vcodec-dec-hw.o + mtk-vcodec-dec-hw.o \ + mtk-vcodec-enc-hw.o =20 mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp8_if.o \ @@ -32,6 +33,7 @@ mtk-vcodec-enc-y :=3D venc/venc_vp8_if.o \ venc_drv_if.o \ venc_vpu_if.o \ =20 +mtk-vcodec-enc-hw-y :=3D mtk_vcodec_enc_hw.o =20 mtk-vcodec-common-y :=3D mtk_vcodec_intr.o \ mtk_vcodec_util.o \ diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 9acab54fd650..6faf9ccc940f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -95,6 +95,15 @@ enum mtk_fmt_type { MTK_FMT_FRAME =3D 2, }; =20 +/* + * enum mtk_venc_hw_id -- encoder hardware id + */ +enum mtk_venc_hw_id { + MTK_VENC_CORE_0 =3D 0, + MTK_VENC_CORE_1, + MTK_VENC_HW_MAX, +}; + /* * enum mtk_vdec_hw_id - Hardware index used to separate * different hardware @@ -470,6 +479,7 @@ struct mtk_vcodec_enc_pdata { * @dec_active_cnt: used to mark whether need to record register value * @vdec_racing_info: record register value * @dec_racing_info_mutex: mutex lock used for inner racing mode + * @enc_hw_dev: used to store venc core device */ struct mtk_vcodec_dev { struct v4l2_device v4l2_dev; @@ -520,6 +530,8 @@ struct mtk_vcodec_dev { u32 vdec_racing_info[132]; /* Protects access to vdec_racing_info data */ struct mutex dec_racing_info_mutex; + + void *enc_hw_dev[MTK_VENC_HW_MAX]; }; =20 static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index 9095186d5495..48f9f59516bd 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -263,6 +263,12 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) goto err_enc_pm; } =20 + ret =3D of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret) { + mtk_v4l2_err("Failed to populate children devices"); + goto err_enc_pm; + } + pm_runtime_enable(&pdev->dev); =20 dev->reg_base[dev->venc_pdata->core_id] =3D diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c new file mode 100644 index 000000000000..cc4938f027e0 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "mtk_vcodec_drv.h" +#include "mtk_vcodec_enc.h" +#include "mtk_vcodec_enc_hw.h" +#include "mtk_vcodec_intr.h" + +static const struct of_device_id mtk_venc_hw_ids[] =3D { + {.compatible =3D "mediatek,mtk-venc-hw",}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_venc_hw_ids); + +static void clean_hw_irq_status(unsigned int irq_status, void __iomem *add= r) +{ + if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE) + writel(MTK_VENC_IRQ_STATUS_PAUSE, addr); + + if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH) + writel(MTK_VENC_IRQ_STATUS_SWITCH, addr); + + if (irq_status & MTK_VENC_IRQ_STATUS_DRAM) + writel(MTK_VENC_IRQ_STATUS_DRAM, addr); + + if (irq_status & MTK_VENC_IRQ_STATUS_SPS) + writel(MTK_VENC_IRQ_STATUS_SPS, addr); + + if (irq_status & MTK_VENC_IRQ_STATUS_PPS) + writel(MTK_VENC_IRQ_STATUS_PPS, addr); + + if (irq_status & MTK_VENC_IRQ_STATUS_FRM) + writel(MTK_VENC_IRQ_STATUS_FRM, addr); +} + +static irqreturn_t mtk_enc_hw_irq_handler(int irq, void *priv) +{ + struct mtk_venc_hw_dev *dev =3D priv; + struct mtk_vcodec_ctx *ctx; + unsigned long flags; + void __iomem *addr; + + spin_lock_irqsave(&dev->main_dev->irqlock, flags); + ctx =3D dev->curr_ctx; + spin_unlock_irqrestore(&dev->main_dev->irqlock, flags); + if (!ctx) + return IRQ_HANDLED; + + mtk_v4l2_debug(1, "id=3D%d core :%d", ctx->id, dev->hw_id); + + addr =3D dev->reg_base + MTK_VENC_IRQ_ACK_OFFSET; + ctx->irq_status =3D readl(dev->reg_base + MTK_VENC_IRQ_STATUS_OFFSET); + clean_hw_irq_status(ctx->irq_status, addr); + + wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0); + return IRQ_HANDLED; +} + +static int mtk_venc_hw_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_venc_hw_dev *sub_core; + struct mtk_vcodec_dev *main_dev; + int ret; + + if (!dev->parent) + return dev_err_probe(dev, -ENODEV, + "No parent for venc core device\n"); + + main_dev =3D dev_get_drvdata(dev->parent); + if (!main_dev) + return dev_err_probe(dev, -EINVAL, + "Failed to get parent driver data\n"); + + sub_core =3D devm_kzalloc(&pdev->dev, sizeof(*sub_core), GFP_KERNEL); + if (!sub_core) + return dev_err_probe(dev, -ENOMEM, + "Failed to get alloc core data\n"); + + sub_core->plat_dev =3D pdev; + + platform_set_drvdata(pdev, sub_core); + + sub_core->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sub_core->reg_base)) + return dev_err_probe(dev, PTR_ERR(sub_core->reg_base), + "Failed to get reg base\n"); + + sub_core->enc_irq =3D platform_get_irq(pdev, 0); + if (sub_core->enc_irq < 0) + return dev_err_probe(dev, -EINVAL, + "Failed to get irq resource\n"); + + ret =3D devm_request_irq(dev, sub_core->enc_irq, + mtk_enc_hw_irq_handler, 0, + pdev->name, sub_core); + if (ret) + return dev_err_probe(dev, -EINVAL, + "Failed to install sub_core->enc_irq %d\n", + sub_core->enc_irq); + + ret =3D of_property_read_u32(dev->of_node, "mediatek,hw-id", + &sub_core->hw_id); + + if (ret || sub_core->hw_id >=3D MTK_VENC_HW_MAX) + return dev_err_probe(dev, (ret ? ret : -EINVAL), + "Cannot parse hardware id"); + + main_dev->enc_hw_dev[sub_core->hw_id] =3D sub_core; + sub_core->main_dev =3D main_dev; + + dev_dbg(dev, "Venc core :%d probe done\n", sub_core->hw_id); + + return 0; +} + +static struct platform_driver mtk_venc_core_driver =3D { + .probe =3D mtk_venc_hw_probe, + .driver =3D { + .name =3D "mtk-venc-core", + .of_match_table =3D mtk_venc_hw_ids, + }, +}; +module_platform_driver(mtk_venc_core_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek video encoder core driver"); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h new file mode 100644 index 000000000000..9daea9665659 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef _MTK_VCODEC_ENC_HW_H_ +#define _MTK_VCODEC_ENC_HW_H_ + +#include +#include "mtk_vcodec_drv.h" + +/** + * struct mtk_venc_hw_dev - driver data + * @plat_dev: platform_device + * @main_dev: main device + * @pm: power management data + * @curr_ctx: the context that is waiting for venc hardware + * @reg_base: mapped address of venc registers + * @irq_status: venc hardware irq status + * @enc_irq: venc device irq + * @hw_id: for venc hardware id: core#0, core#1... + */ +struct mtk_venc_hw_dev { + struct platform_device *plat_dev; + struct mtk_vcodec_dev *main_dev; + + struct mtk_vcodec_pm pm; + struct mtk_vcodec_ctx *curr_ctx; + + void __iomem *reg_base; + unsigned int irq_status; + int enc_irq; + enum mtk_venc_hw_id hw_id; +}; + +#endif /* _MTK_VCODEC_ENC_HW_H_ */ --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73F43C433F5 for ; Sat, 1 Oct 2022 03:27:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233189AbiJAD1B (ORCPT ); Fri, 30 Sep 2022 23:27:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233175AbiJADZn (ORCPT ); Fri, 30 Sep 2022 23:25:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E40BF80A6; Fri, 30 Sep 2022 20:17:52 -0700 (PDT) X-UUID: 1a4316dc2c9b471d863f015873e272fd-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tVU561ie3mo1qOpQcZtWrSSXP0unSyosTSaMx2bhXHE=; b=Ux0MD2HjZgSl9ueJfSI5B1EMqMBM+xM9uMVXCG+Sr/Emp0nA6xGPhsAWx5V/mhj6k7PNbeF1KbbcfCuc9lH98zgdWwIqCy3VohS0pmvHs8qILseJl+vd7N+l0OU1wip3JvVqw6Xwk3a+rp0FKkkzasEJbcioVnOSle/JshDdYwI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:44f34caa-23b5-4d8e-8173-c48fd1448a0a,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:44f34caa-23b5-4d8e-8173-c48fd1448a0a,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:963ed6e4-87f9-4bb0-97b6-34957dc0fbbe,B ulkID:221001111749B6OCBMAP,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: 1a4316dc2c9b471d863f015873e272fd-20221001 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 761456109; Sat, 01 Oct 2022 11:17:46 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:44 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:43 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Tzung-Bi Shih , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , Subject: [PATCH v6, 3/8] media: mediatek: vcodec: Refactor venc power manage function Date: Sat, 1 Oct 2022 11:17:32 +0800 Message-ID: <20221001031737.18266-4-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The args "struct mtk_vcodec_dev *" doesn't appropriate for init_clk functions because of sub-devices, sub-devices will init their own "pm/clk" instead, so refactor the pm function with args "platform_device *" and "mtk_vcodec_pm*". Signed-off-by: Irui Wang --- .../media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c | 2 +- .../media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c | 8 ++++++++ .../media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c | 9 +++------ .../media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h | 3 ++- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index 48f9f59516bd..5bfbf4eead13 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -257,7 +257,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) return PTR_ERR(dev->fw_handler); =20 dev->venc_pdata =3D of_device_get_match_data(&pdev->dev); - ret =3D mtk_vcodec_init_enc_clk(dev); + ret =3D mtk_vcodec_init_enc_clk(dev->plat_dev, &dev->pm); if (ret < 0) { dev_err(&pdev->dev, "Failed to get mtk vcodec clock source!"); goto err_enc_pm; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c index cc4938f027e0..1ed4279925b7 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c @@ -13,6 +13,7 @@ #include "mtk_vcodec_drv.h" #include "mtk_vcodec_enc.h" #include "mtk_vcodec_enc_hw.h" +#include "mtk_vcodec_enc_pm.h" #include "mtk_vcodec_intr.h" =20 static const struct of_device_id mtk_venc_hw_ids[] =3D { @@ -115,6 +116,13 @@ static int mtk_venc_hw_probe(struct platform_device *p= dev) return dev_err_probe(dev, (ret ? ret : -EINVAL), "Cannot parse hardware id"); =20 + ret =3D mtk_vcodec_init_enc_clk(sub_core->plat_dev, &sub_core->pm); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get venc core clock source!"); + + pm_runtime_enable(&pdev->dev); + main_dev->enc_hw_dev[sub_core->hw_id] =3D sub_core; sub_core->main_dev =3D main_dev; =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c index 7055954eb2af..75de5031d292 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c @@ -12,17 +12,13 @@ #include "mtk_vcodec_enc_pm.h" #include "mtk_vcodec_util.h" =20 -int mtk_vcodec_init_enc_clk(struct mtk_vcodec_dev *mtkdev) +int mtk_vcodec_init_enc_clk(struct platform_device *pdev, + struct mtk_vcodec_pm *pm) { - struct platform_device *pdev; - struct mtk_vcodec_pm *pm; struct mtk_vcodec_clk *enc_clk; struct mtk_vcodec_clk_info *clk_info; int ret, i; =20 - pdev =3D mtkdev->plat_dev; - pm =3D &mtkdev->pm; - memset(pm, 0, sizeof(struct mtk_vcodec_pm)); pm->dev =3D &pdev->dev; enc_clk =3D &pm->venc_clk; =20 @@ -58,6 +54,7 @@ int mtk_vcodec_init_enc_clk(struct mtk_vcodec_dev *mtkdev) =20 return 0; } +EXPORT_SYMBOL_GPL(mtk_vcodec_init_enc_clk); =20 void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h index bc455cefc0cd..361dec5be47f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h @@ -9,7 +9,8 @@ =20 #include "mtk_vcodec_drv.h" =20 -int mtk_vcodec_init_enc_clk(struct mtk_vcodec_dev *dev); +int mtk_vcodec_init_enc_clk(struct platform_device *pdev, + struct mtk_vcodec_pm *pm); =20 void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm); void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm); --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6E8BC433F5 for ; Sat, 1 Oct 2022 03:26:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233324AbiJAD0q (ORCPT ); Fri, 30 Sep 2022 23:26:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233109AbiJADZk (ORCPT ); Fri, 30 Sep 2022 23:25:40 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2108BF80A3; Fri, 30 Sep 2022 20:17:49 -0700 (PDT) X-UUID: 189f2903897642d585ab51ff4907afab-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gQH1JyEktFOJV39yJWLnXwk1nF1Uwl2E7ka1LkvPm10=; b=Hd6W2J7GXQ7ILuBmxb3sXsi2uqGHFai6LIfz3zMgzE8uzQD5jTB020hA0aHjg0q5lizMZPNmWhlIME1sOQgc28WbikWm2uPAlMMQfjAyCllWssOWEDzk5wRnmYmEvzhXWMzKrEMY8I3DKm9VvnZr9Vbb/dyUfPBhDGfAWxjmTT0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:56c23a73-1160-4a54-82e2-1d75663274e5,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:56c23a73-1160-4a54-82e2-1d75663274e5,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:9e67afa3-dc04-435c-b19b-71e131a5fc35,B ulkID:221001111747BN0SKB6G,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: 189f2903897642d585ab51ff4907afab-20221001 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 278911089; Sat, 01 Oct 2022 11:17:47 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:45 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:44 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Tzung-Bi Shih , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , Subject: [PATCH v6, 4/8] media: mediatek: vcodec: Add more extra processing for multi-core encoding Date: Sat, 1 Oct 2022 11:17:33 +0800 Message-ID: <20221001031737.18266-5-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a bit for indicating support multi-core encoding, because multi-core encoding need more working buffers for encoder hardware. The working buffers are allocated from kernel side then pass to scp firmware side through shared memory, the struct definition must be kept align between kernel and scp firmware side. New another shared memory struct for multi-core encoding. Signed-off-by: Irui Wang --- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 2 + .../mediatek/vcodec/mtk_vcodec_util.c | 19 +++ .../mediatek/vcodec/mtk_vcodec_util.h | 2 + .../mediatek/vcodec/venc/venc_h264_if.c | 108 +++++++++++++++--- 4 files changed, 116 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 6faf9ccc940f..e074198a12ad 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -27,6 +27,8 @@ #define WAIT_INTR_TIMEOUT_MS 1000 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >=3D MTK_VDEC_LAT_SINGLE_CORE) #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) +#define MTK_VENC_MULTICORE_ENABLE BIT(1) +#define IS_VENC_MULTICORE(capability) ((capability) & MTK_VENC_MULTICORE_E= NABLE) =20 /* * enum mtk_hw_reg_idx - MTK hw register base index diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c b/dri= vers/media/platform/mediatek/vcodec/mtk_vcodec_util.c index ace78c4b5b9e..a4c2cbf4040e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c @@ -11,6 +11,7 @@ =20 #include "mtk_vcodec_dec_hw.h" #include "mtk_vcodec_drv.h" +#include "mtk_vcodec_enc_hw.h" #include "mtk_vcodec_util.h" =20 void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, @@ -26,6 +27,24 @@ void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_= ctx *data, } EXPORT_SYMBOL(mtk_vcodec_get_reg_addr); =20 +void __iomem *mtk_venc_get_core_reg_addr(struct mtk_vcodec_ctx *ctx, + int hw_id) +{ + struct mtk_venc_hw_dev *sub_core; + + if (hw_id >=3D MTK_VENC_HW_MAX) { + mtk_v4l2_err("Invalid hw_id =3D %d", hw_id); + return NULL; + } + + sub_core =3D (struct mtk_venc_hw_dev *)ctx->dev->enc_hw_dev[hw_id]; + if (!sub_core) + return NULL; + + return sub_core->reg_base; +} +EXPORT_SYMBOL(mtk_venc_get_core_reg_addr); + int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h b/dri= vers/media/platform/mediatek/vcodec/mtk_vcodec_util.h index 71956627a0e2..0033c53d5589 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h @@ -50,6 +50,8 @@ struct mtk_vcodec_dev; =20 void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, unsigned int reg_idx); +void __iomem *mtk_venc_get_core_reg_addr(struct mtk_vcodec_ctx *data, + int hw_id); int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem); void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data, diff --git a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c b/d= rivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c index 13c4f860fa69..d7ed5c753a0e 100644 --- a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c @@ -50,6 +50,24 @@ enum venc_h264_vpu_work_buf { VENC_H264_VPU_WORK_BUF_MAX, }; =20 +/* + * enum venc_multi_core_work_buf - h264 multi core encoder buffer index + */ +enum venc_multi_core_work_buf { + VENC_MULTI_CORE_WORK_BUF_RC_INFO_CORE0, + VENC_MULTI_CORE_WORK_BUF_RC_CODE, + VENC_MULTI_CORE_WORK_BUF_REC_LUMA, + VENC_MULTI_CORE_WORK_BUF_REC_CHROMA, + VENC_MULTI_CORE_WORK_BUF_REF_LUMA, + VENC_MULTI_CORE_WORK_BUF_REF_CHROMA, + VENC_MULTI_CORE_WORK_BUF_MV_INFO_1, + VENC_MULTI_CORE_WORK_BUF_MV_INFO_2, + VENC_MULTI_CORE_WORK_BUF_SKIP_FRAME, + VENC_MULTI_CORE_WORK_BUF_RC_INFO_CORE1, + VENC_MULTI_CORE_WORK_BUF_FR_RC_INFO, + VENC_MULTI_CORE_WORK_BUF_MAX, +}; + /* * enum venc_h264_bs_mode - for bs_mode argument in h264_enc_vpu_encode */ @@ -193,6 +211,17 @@ struct venc_h264_vsi_34 { struct venc_h264_vpu_buf_34 work_bufs[VENC_H264_VPU_WORK_BUF_MAX]; }; =20 +/** + * struct venc_multi_core_vsi - Structure for VPU driver control and info = share + * Used for multi-core encode sharing + * @config: h264 encoder configuration + * @work_bufs: working buffer information in VPU side + */ +struct venc_multi_core_vsi { + struct venc_h264_vpu_config_ext config; + struct venc_h264_vpu_buf work_bufs[VENC_MULTI_CORE_WORK_BUF_MAX]; +}; + /* * struct venc_h264_inst - h264 encoder AP driver instance * @hw_base: h264 encoder hardware register base @@ -208,25 +237,29 @@ struct venc_h264_vsi_34 { * control and info share * @vsi_34: driver structure allocated by VPU side and shared to AP side f= or * control and info share, used for 34-bit iova sharing. + * @core_vsi: used for multi-core encode info sharing. * @ctx: context for v4l2 layer integration */ struct venc_h264_inst { - void __iomem *hw_base; - struct mtk_vcodec_mem work_bufs[VENC_H264_VPU_WORK_BUF_MAX]; + void __iomem *hw_base[MTK_VENC_HW_MAX]; + struct mtk_vcodec_mem work_bufs[VENC_MULTI_CORE_WORK_BUF_MAX]; struct mtk_vcodec_mem pps_buf; bool work_buf_allocated; unsigned int frm_cnt; unsigned int skip_frm_cnt; unsigned int prepend_hdr; struct venc_vpu_inst vpu_inst; - struct venc_h264_vsi *vsi; - struct venc_h264_vsi_34 *vsi_34; + union { + struct venc_h264_vsi *vsi; + struct venc_h264_vsi_34 *vsi_34; + struct venc_multi_core_vsi *core_vsi; + }; struct mtk_vcodec_ctx *ctx; }; =20 static inline u32 h264_read_reg(struct venc_h264_inst *inst, u32 addr) { - return readl(inst->hw_base + addr); + return readl(inst->hw_base[MTK_VENC_CORE_0] + addr); } =20 static unsigned int h264_get_profile(struct venc_h264_inst *inst, @@ -296,14 +329,20 @@ static unsigned int h264_get_level(struct venc_h264_i= nst *inst, =20 static void h264_enc_free_work_buf(struct venc_h264_inst *inst) { - int i; + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + int i, max_work_buf; =20 mtk_vcodec_debug_enter(inst); =20 + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) + max_work_buf =3D VENC_MULTI_CORE_WORK_BUF_MAX; + else + max_work_buf =3D VENC_H264_VPU_WORK_BUF_MAX; + /* Except the SKIP_FRAME buffers, * other buffers need to be freed by AP. */ - for (i =3D 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) { + for (i =3D 0; i < max_work_buf; i++) { if (i !=3D VENC_H264_VPU_WORK_BUF_SKIP_FRAME) mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]); } @@ -317,18 +356,25 @@ static int h264_enc_alloc_work_buf(struct venc_h264_i= nst *inst, bool is_34bit) { struct venc_h264_vpu_buf *wb =3D NULL; struct venc_h264_vpu_buf_34 *wb_34 =3D NULL; - int i; + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + int i, max_work_buf; u32 vpua, wb_size; int ret =3D 0; =20 mtk_vcodec_debug_enter(inst); =20 - if (is_34bit) + if (is_34bit) { wb_34 =3D inst->vsi_34->work_bufs; - else + max_work_buf =3D VENC_H264_VPU_WORK_BUF_MAX; + } else if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + wb =3D inst->core_vsi->work_bufs; + max_work_buf =3D VENC_MULTI_CORE_WORK_BUF_MAX; + } else { wb =3D inst->vsi->work_bufs; + max_work_buf =3D VENC_H264_VPU_WORK_BUF_MAX; + } =20 - for (i =3D 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) { + for (i =3D 0; i < max_work_buf; i++) { /* * This 'wb' structure is set by VPU side and shared to AP for * buffer allocation and IO virtual addr mapping. For most of @@ -537,6 +583,9 @@ static int h264_encode_frame(struct venc_h264_inst *ins= t, if (MTK_ENC_IOVA_IS_34BIT(ctx)) { gop_size =3D inst->vsi_34->config.gop_size; intra_period =3D inst->vsi_34->config.intra_period; + } else if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + gop_size =3D inst->core_vsi->config.gop_size; + intra_period =3D inst->core_vsi->config.intra_period; } else { gop_size =3D inst->vsi->config.gop_size; intra_period =3D inst->vsi->config.intra_period; @@ -602,8 +651,8 @@ static void h264_encode_filler(struct venc_h264_inst *i= nst, void *buf, static int h264_enc_init(struct mtk_vcodec_ctx *ctx) { const bool is_ext =3D MTK_ENC_CTX_IS_EXT(ctx); - int ret =3D 0; struct venc_h264_inst *inst; + int ret, i; =20 inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); if (!inst) @@ -612,16 +661,24 @@ static int h264_enc_init(struct mtk_vcodec_ctx *ctx) inst->ctx =3D ctx; inst->vpu_inst.ctx =3D ctx; inst->vpu_inst.id =3D is_ext ? SCP_IPI_VENC_H264 : IPI_VENC_H264; - inst->hw_base =3D mtk_vcodec_get_reg_addr(inst->ctx, VENC_SYS); + inst->hw_base[0] =3D mtk_vcodec_get_reg_addr(inst->ctx, VENC_SYS); =20 mtk_vcodec_debug_enter(inst); =20 ret =3D vpu_enc_init(&inst->vpu_inst); =20 - if (MTK_ENC_IOVA_IS_34BIT(ctx)) + if (MTK_ENC_IOVA_IS_34BIT(ctx)) { inst->vsi_34 =3D (struct venc_h264_vsi_34 *)inst->vpu_inst.vsi; - else + } else if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + inst->core_vsi =3D + (struct venc_multi_core_vsi *)inst->vpu_inst.vsi; + + for (i =3D 1; i < MTK_VENC_HW_MAX; i++) + inst->hw_base[i] =3D + mtk_venc_get_core_reg_addr(inst->ctx, i); + } else { inst->vsi =3D (struct venc_h264_vsi *)inst->vpu_inst.vsi; + } =20 mtk_vcodec_debug_leave(inst); =20 @@ -766,6 +823,25 @@ static void h264_enc_set_vsi_34_configs(struct venc_h2= 64_inst *inst, inst->vsi_34->config.wfd =3D 0; } =20 +static void h264_enc_set_core_configs(struct venc_h264_inst *inst, + struct venc_enc_param *enc_prm) +{ + inst->core_vsi->config.input_fourcc =3D enc_prm->input_yuv_fmt; + inst->core_vsi->config.bitrate =3D enc_prm->bitrate; + inst->core_vsi->config.pic_w =3D enc_prm->width; + inst->core_vsi->config.pic_h =3D enc_prm->height; + inst->core_vsi->config.buf_w =3D enc_prm->buf_width; + inst->core_vsi->config.buf_h =3D enc_prm->buf_height; + inst->core_vsi->config.gop_size =3D enc_prm->gop_size; + inst->core_vsi->config.framerate =3D enc_prm->frm_rate; + inst->core_vsi->config.intra_period =3D enc_prm->intra_period; + inst->core_vsi->config.profile =3D + h264_get_profile(inst, enc_prm->h264_profile); + inst->core_vsi->config.level =3D + h264_get_level(inst, enc_prm->h264_level); + inst->core_vsi->config.wfd =3D 0; +} + static int h264_enc_set_param(void *handle, enum venc_set_param_type type, struct venc_enc_param *enc_prm) @@ -781,6 +857,8 @@ static int h264_enc_set_param(void *handle, case VENC_SET_PARAM_ENC: if (is_34bit) h264_enc_set_vsi_34_configs(inst, enc_prm); + else if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) + h264_enc_set_core_configs(inst, enc_prm); else h264_enc_set_vsi_configs(inst, enc_prm); ret =3D vpu_enc_set_param(&inst->vpu_inst, type, enc_prm); --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77C5CC433FE for ; Sat, 1 Oct 2022 03:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232477AbiJAD1G (ORCPT ); Fri, 30 Sep 2022 23:27:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233185AbiJADZn (ORCPT ); Fri, 30 Sep 2022 23:25:43 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FF65F8095; Fri, 30 Sep 2022 20:17:52 -0700 (PDT) X-UUID: 243a680043f84d5ca87b194cdfa2e66c-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=2cnWDnSWQ4A3CSpnDFyqTwoZZOSmTBmzT9j2HEBromc=; b=poIpXeR6hsImaQOD6ZdBp7tMch65W2sNIkp09LCH/LTOXEWQFeyDFc3NKwSwl7AWYxuakgFg1DAC/sRq9FxGRJzHJMZrozmObAji+yMd9nT0/4j5XHxB8HXD8t+6ERxRchlUl3jyDCaYW9ZuRZAmGz4FBbSy9mjb57iJ686xF/A=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:aa44a2e9-6ab0-43ef-a41c-d2b5b93c4c2c,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:8caba107-1cee-4c38-b21b-a45f9682fdc0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 243a680043f84d5ca87b194cdfa2e66c-20221001 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1927029966; Sat, 01 Oct 2022 11:17:48 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:46 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:45 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , "Tzung-Bi Shih" , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , "Irui Wang" , , , , , , Subject: [PATCH v6, 5/8] media: mediatek: vcodec: Add venc power on/off function Date: Sat, 1 Oct 2022 11:17:34 +0800 Message-ID: <20221001031737.18266-6-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" when enable multi-core encoding, all available encoder cores' power need to be on/off, add new functions for encoder cores' power management. Signed-off-by: Irui Wang --- .../platform/mediatek/vcodec/mtk_vcodec_enc.c | 31 +++---- .../mediatek/vcodec/mtk_vcodec_enc_pm.c | 83 +++++++++++++++++++ .../mediatek/vcodec/mtk_vcodec_enc_pm.h | 2 + .../platform/mediatek/vcodec/venc_drv_if.c | 6 -- 4 files changed, 97 insertions(+), 25 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c index d810a78dde51..66e08e88dcc8 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c @@ -8,10 +8,10 @@ #include #include #include -#include =20 #include "mtk_vcodec_drv.h" #include "mtk_vcodec_enc.h" +#include "mtk_vcodec_enc_pm.h" #include "mtk_vcodec_intr.h" #include "mtk_vcodec_util.h" #include "venc_drv_if.h" @@ -879,8 +879,7 @@ static int vb2ops_venc_start_streaming(struct vb2_queue= *q, unsigned int count) { struct mtk_vcodec_ctx *ctx =3D vb2_get_drv_priv(q); struct venc_enc_param param; - int ret, pm_ret; - int i; + int ret, i; =20 /* Once state turn into MTK_STATE_ABORT, we need stop_streaming * to clear it @@ -899,18 +898,12 @@ static int vb2ops_venc_start_streaming(struct vb2_que= ue *q, unsigned int count) return 0; } =20 - ret =3D pm_runtime_resume_and_get(&ctx->dev->plat_dev->dev); - if (ret < 0) { - mtk_v4l2_err("pm_runtime_resume_and_get fail %d", ret); - goto err_start_stream; - } - mtk_venc_set_param(ctx, ¶m); ret =3D venc_if_set_param(ctx, VENC_SET_PARAM_ENC, ¶m); if (ret) { mtk_v4l2_err("venc_if_set_param failed=3D%d", ret); ctx->state =3D MTK_STATE_ABORT; - goto err_set_param; + goto err_start_stream; } ctx->param_change =3D MTK_ENCODE_PARAM_NONE; =20 @@ -923,17 +916,19 @@ static int vb2ops_venc_start_streaming(struct vb2_que= ue *q, unsigned int count) if (ret) { mtk_v4l2_err("venc_if_set_param failed=3D%d", ret); ctx->state =3D MTK_STATE_ABORT; - goto err_set_param; + goto err_start_stream; } ctx->state =3D MTK_STATE_HEADER; } =20 - return 0; + ret =3D mtk_vcodec_enc_power_on(ctx); + if (ret) { + mtk_v4l2_err("mtk_vcodec_enc_power_on failed=3D%d", ret); + ctx->state =3D MTK_STATE_ABORT; + goto err_start_stream; + } =20 -err_set_param: - pm_ret =3D pm_runtime_put(&ctx->dev->plat_dev->dev); - if (pm_ret < 0) - mtk_v4l2_err("pm_runtime_put fail %d", pm_ret); + return 0; =20 err_start_stream: for (i =3D 0; i < q->num_buffers; ++i) { @@ -1018,9 +1013,7 @@ static void vb2ops_venc_stop_streaming(struct vb2_que= ue *q) if (ret) mtk_v4l2_err("venc_if_deinit failed=3D%d", ret); =20 - ret =3D pm_runtime_put(&ctx->dev->plat_dev->dev); - if (ret < 0) - mtk_v4l2_err("pm_runtime_put fail %d", ret); + mtk_vcodec_enc_power_off(ctx); =20 ctx->state =3D MTK_STATE_FREE; } diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c index 75de5031d292..213c3f50e9eb 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c @@ -9,6 +9,7 @@ #include #include =20 +#include "mtk_vcodec_enc_hw.h" #include "mtk_vcodec_enc_pm.h" #include "mtk_vcodec_util.h" =20 @@ -56,6 +57,88 @@ int mtk_vcodec_init_enc_clk(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(mtk_vcodec_init_enc_clk); =20 +static int mtk_enc_core_power_on(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_venc_hw_dev *sub_core; + int ret, i; + + /* multi-core encoding need power on all available cores */ + for (i =3D 0; i < MTK_VENC_HW_MAX; i++) { + sub_core =3D (struct mtk_venc_hw_dev *)ctx->dev->enc_hw_dev[i]; + if (!sub_core) + continue; + + ret =3D pm_runtime_resume_and_get(&sub_core->plat_dev->dev); + if (ret) { + mtk_v4l2_err("power on sub_core[%d] fail %d", i, ret); + goto pm_on_fail; + } + } + return ret; + +pm_on_fail: + for (i -=3D 1; i >=3D 0; i--) { + sub_core =3D (struct mtk_venc_hw_dev *)ctx->dev->enc_hw_dev[i]; + pm_runtime_put_sync(&sub_core->plat_dev->dev); + } + return ret; +} + +int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_vcodec_pm *pm =3D &ctx->dev->pm; + int ret; + + ret =3D pm_runtime_resume_and_get(pm->dev); + if (ret) { + mtk_v4l2_err("pm_runtime_resume_and_get fail %d", ret); + return ret; + } + + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + ret =3D mtk_enc_core_power_on(ctx); + if (ret) { + mtk_v4l2_err("mtk_enc_core_power_on fail %d", ret); + goto core_error; + } + } + return ret; + +core_error: + pm_runtime_put_sync(pm->dev); + return ret; +} + +static void mtk_enc_core_power_off(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_venc_hw_dev *sub_core; + int ret, i; + + /* multi-core encoding need power off all available cores */ + for (i =3D 0; i < MTK_VENC_HW_MAX; i++) { + sub_core =3D (struct mtk_venc_hw_dev *)ctx->dev->enc_hw_dev[i]; + if (!sub_core) + continue; + + ret =3D pm_runtime_put_sync(&sub_core->plat_dev->dev); + if (ret) + mtk_v4l2_err("power off sub_core[%d] fail %d", i, ret); + } +} + +void mtk_vcodec_enc_power_off(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_vcodec_pm *pm =3D &ctx->dev->pm; + int ret; + + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) + mtk_enc_core_power_off(ctx); + + ret =3D pm_runtime_put_sync(pm->dev); + if (ret) + mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); +} + void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm) { struct mtk_vcodec_clk *enc_clk =3D &pm->venc_clk; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h index 361dec5be47f..9065dec4ed4f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h @@ -12,6 +12,8 @@ int mtk_vcodec_init_enc_clk(struct platform_device *pdev, struct mtk_vcodec_pm *pm); =20 +int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx); +void mtk_vcodec_enc_power_off(struct mtk_vcodec_ctx *ctx); void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm); void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm); =20 diff --git a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c b/drivers= /media/platform/mediatek/vcodec/venc_drv_if.c index ce0bce811615..65a27e39ef5b 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc_drv_if.c @@ -32,9 +32,7 @@ int venc_if_init(struct mtk_vcodec_ctx *ctx, unsigned int= fourcc) } =20 mtk_venc_lock(ctx); - mtk_vcodec_enc_clock_on(&ctx->dev->pm); ret =3D ctx->enc_if->init(ctx); - mtk_vcodec_enc_clock_off(&ctx->dev->pm); mtk_venc_unlock(ctx); =20 return ret; @@ -46,9 +44,7 @@ int venc_if_set_param(struct mtk_vcodec_ctx *ctx, int ret =3D 0; =20 mtk_venc_lock(ctx); - mtk_vcodec_enc_clock_on(&ctx->dev->pm); ret =3D ctx->enc_if->set_param(ctx->drv_handle, type, in); - mtk_vcodec_enc_clock_off(&ctx->dev->pm); mtk_venc_unlock(ctx); =20 return ret; @@ -89,9 +85,7 @@ int venc_if_deinit(struct mtk_vcodec_ctx *ctx) return 0; =20 mtk_venc_lock(ctx); - mtk_vcodec_enc_clock_on(&ctx->dev->pm); ret =3D ctx->enc_if->deinit(ctx->drv_handle); - mtk_vcodec_enc_clock_off(&ctx->dev->pm); mtk_venc_unlock(ctx); =20 ctx->drv_handle =3D NULL; --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46938C433F5 for ; Sat, 1 Oct 2022 03:27:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233192AbiJAD1Q (ORCPT ); Fri, 30 Sep 2022 23:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233269AbiJADZp (ORCPT ); Fri, 30 Sep 2022 23:25:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 302B7F80AB; Fri, 30 Sep 2022 20:17:54 -0700 (PDT) X-UUID: faca22d3819b4747866305462f157480-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6YODgIkJ5B15rmZrHBBzn4vXZqLJDx2Vv+ld3YAklVw=; b=BeKcGngxtsDwUgxfExAHhJ62eqMc67XCvWM9wwq9dHVb4jLKLqcqNdm5rDBu05Pncg+kPhfiowWuqdnRwBMK+Iwn72B7E5PbZkzQ5IA53gNPRXRdowSOr+mqK135ByJUNeR67niW3CueeNs9Ong0IRYF+yyRSOXglYN04Ex0m5Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:42a16988-44c9-4e81-bcd4-e7d27477ff69,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:cb3ed6e4-87f9-4bb0-97b6-34957dc0fbbe,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: faca22d3819b4747866305462f157480-20221001 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 124696460; Sat, 01 Oct 2022 11:17:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:47 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:46 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , "Tzung-Bi Shih" , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , "Irui Wang" , , , , , , Subject: [PATCH v6, 6/8] media: mediatek: vcodec: Refactor encoder clock on/off function Date: Sat, 1 Oct 2022 11:17:35 +0800 Message-ID: <20221001031737.18266-7-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" when enable multi-core encoding, encoder cores use their own clock, refactor clock management functions with used encoder hardware id. Signed-off-by: Irui Wang --- .../mediatek/vcodec/mtk_vcodec_enc_pm.c | 89 ++++++++++++++++--- .../mediatek/vcodec/mtk_vcodec_enc_pm.h | 6 +- .../platform/mediatek/vcodec/venc_drv_if.c | 4 +- 3 files changed, 84 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c index 213c3f50e9eb..2f83aade779a 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c @@ -60,7 +60,9 @@ EXPORT_SYMBOL_GPL(mtk_vcodec_init_enc_clk); static int mtk_enc_core_power_on(struct mtk_vcodec_ctx *ctx) { struct mtk_venc_hw_dev *sub_core; + struct mtk_vcodec_clk *clk; int ret, i; + int j =3D 0; =20 /* multi-core encoding need power on all available cores */ for (i =3D 0; i < MTK_VENC_HW_MAX; i++) { @@ -73,12 +75,27 @@ static int mtk_enc_core_power_on(struct mtk_vcodec_ctx = *ctx) mtk_v4l2_err("power on sub_core[%d] fail %d", i, ret); goto pm_on_fail; } + + clk =3D &sub_core->pm.venc_clk; + for (j =3D 0; j < clk->clk_num; j++) { + ret =3D clk_prepare(clk->clk_info[j].vcodec_clk); + if (ret) { + mtk_v4l2_err("prepare clk [%s] fail %d", + clk->clk_info[j].clk_name, ret); + goto pm_on_fail; + } + } } return ret; =20 pm_on_fail: for (i -=3D 1; i >=3D 0; i--) { sub_core =3D (struct mtk_venc_hw_dev *)ctx->dev->enc_hw_dev[i]; + + clk =3D &sub_core->pm.venc_clk; + for (j -=3D 1; j >=3D 0; j--) + clk_unprepare(clk->clk_info[j].vcodec_clk); + pm_runtime_put_sync(&sub_core->plat_dev->dev); } return ret; @@ -87,7 +104,9 @@ static int mtk_enc_core_power_on(struct mtk_vcodec_ctx *= ctx) int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx) { struct mtk_vcodec_pm *pm =3D &ctx->dev->pm; + struct mtk_vcodec_clk *clk; int ret; + int i =3D 0; =20 ret =3D pm_runtime_resume_and_get(pm->dev); if (ret) { @@ -95,6 +114,16 @@ int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx) return ret; } =20 + clk =3D &pm->venc_clk; + for (i =3D 0; i < clk->clk_num; i++) { + ret =3D clk_prepare(clk->clk_info[i].vcodec_clk); + if (ret) { + mtk_v4l2_err("prepare clk [%s] fail %d", + clk->clk_info[i].clk_name, ret); + goto clk_error; + } + } + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { ret =3D mtk_enc_core_power_on(ctx); if (ret) { @@ -104,6 +133,9 @@ int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx) } return ret; =20 +clk_error: + for (i -=3D 1; i >=3D 0; i--) + clk_unprepare(clk->clk_info[i].vcodec_clk); core_error: pm_runtime_put_sync(pm->dev); return ret; @@ -112,7 +144,8 @@ int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx) static void mtk_enc_core_power_off(struct mtk_vcodec_ctx *ctx) { struct mtk_venc_hw_dev *sub_core; - int ret, i; + struct mtk_vcodec_clk *clk; + int ret, i, j; =20 /* multi-core encoding need power off all available cores */ for (i =3D 0; i < MTK_VENC_HW_MAX; i++) { @@ -120,6 +153,10 @@ static void mtk_enc_core_power_off(struct mtk_vcodec_c= tx *ctx) if (!sub_core) continue; =20 + clk =3D &sub_core->pm.venc_clk; + for (j =3D clk->clk_num - 1; j >=3D 0; j--) + clk_unprepare(clk->clk_info[j].vcodec_clk); + ret =3D pm_runtime_put_sync(&sub_core->plat_dev->dev); if (ret) mtk_v4l2_err("power off sub_core[%d] fail %d", i, ret); @@ -129,26 +166,44 @@ static void mtk_enc_core_power_off(struct mtk_vcodec_= ctx *ctx) void mtk_vcodec_enc_power_off(struct mtk_vcodec_ctx *ctx) { struct mtk_vcodec_pm *pm =3D &ctx->dev->pm; - int ret; + struct mtk_vcodec_clk *clk; + int ret, i; =20 if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) mtk_enc_core_power_off(ctx); =20 + clk =3D &pm->venc_clk; + for (i =3D clk->clk_num - 1; i >=3D 0; i--) + clk_unprepare(clk->clk_info[i].vcodec_clk); + ret =3D pm_runtime_put_sync(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); } =20 -void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm) +void mtk_vcodec_enc_clock_on(struct mtk_vcodec_dev *dev, + enum mtk_venc_hw_id hw_id) { - struct mtk_vcodec_clk *enc_clk =3D &pm->venc_clk; + struct mtk_venc_hw_dev *sub_core; + struct mtk_vcodec_clk *enc_clk; + int ret, i =3D 0; =20 + if (hw_id =3D=3D MTK_VENC_CORE_0) { + enc_clk =3D &dev->pm.venc_clk; + } else if (hw_id =3D=3D MTK_VENC_CORE_1) { + sub_core =3D (struct mtk_venc_hw_dev *)dev->enc_hw_dev[hw_id]; + enc_clk =3D &sub_core->pm.venc_clk; + } else { + mtk_v4l2_err("invalid hw id : %d", hw_id); + return; + } + for (i =3D 0; i < enc_clk->clk_num; i++) { - ret =3D clk_prepare_enable(enc_clk->clk_info[i].vcodec_clk); + ret =3D clk_enable(enc_clk->clk_info[i].vcodec_clk); if (ret) { - mtk_v4l2_err("venc clk_prepare_enable %d %s fail %d", i, - enc_clk->clk_info[i].clk_name, ret); + mtk_v4l2_err("venc clk_enable %d %s fail %d", i, + enc_clk->clk_info[i].clk_name, ret); goto clkerr; } } @@ -157,14 +212,26 @@ void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm) =20 clkerr: for (i -=3D 1; i >=3D 0; i--) - clk_disable_unprepare(enc_clk->clk_info[i].vcodec_clk); + clk_disable(enc_clk->clk_info[i].vcodec_clk); } =20 -void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm) +void mtk_vcodec_enc_clock_off(struct mtk_vcodec_dev *dev, + enum mtk_venc_hw_id hw_id) { - struct mtk_vcodec_clk *enc_clk =3D &pm->venc_clk; + struct mtk_venc_hw_dev *sub_core; + struct mtk_vcodec_clk *enc_clk; int i =3D 0; =20 + if (hw_id =3D=3D MTK_VENC_CORE_0) { + enc_clk =3D &dev->pm.venc_clk; + } else if (hw_id =3D=3D MTK_VENC_CORE_1) { + sub_core =3D (struct mtk_venc_hw_dev *)dev->enc_hw_dev[hw_id]; + enc_clk =3D &sub_core->pm.venc_clk; + } else { + mtk_v4l2_err("invalid hw id : %d", hw_id); + return; + } + for (i =3D enc_clk->clk_num - 1; i >=3D 0; i--) - clk_disable_unprepare(enc_clk->clk_info[i].vcodec_clk); + clk_disable(enc_clk->clk_info[i].vcodec_clk); } diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h index 9065dec4ed4f..a2906d2971ee 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.h @@ -14,7 +14,9 @@ int mtk_vcodec_init_enc_clk(struct platform_device *pdev, =20 int mtk_vcodec_enc_power_on(struct mtk_vcodec_ctx *ctx); void mtk_vcodec_enc_power_off(struct mtk_vcodec_ctx *ctx); -void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm); -void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm); +void mtk_vcodec_enc_clock_on(struct mtk_vcodec_dev *dev, + enum mtk_venc_hw_id hw_id); +void mtk_vcodec_enc_clock_off(struct mtk_vcodec_dev *dev, + enum mtk_venc_hw_id hw_id); =20 #endif /* _MTK_VCODEC_ENC_PM_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c b/drivers= /media/platform/mediatek/vcodec/venc_drv_if.c index 65a27e39ef5b..6cbdb7e30bb3 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc_drv_if.c @@ -64,10 +64,10 @@ int venc_if_encode(struct mtk_vcodec_ctx *ctx, ctx->dev->curr_ctx =3D ctx; spin_unlock_irqrestore(&ctx->dev->irqlock, flags); =20 - mtk_vcodec_enc_clock_on(&ctx->dev->pm); + mtk_vcodec_enc_clock_on(ctx->dev, 0); ret =3D ctx->enc_if->encode(ctx->drv_handle, opt, frm_buf, bs_buf, result); - mtk_vcodec_enc_clock_off(&ctx->dev->pm); + mtk_vcodec_enc_clock_off(ctx->dev, 0); =20 spin_lock_irqsave(&ctx->dev->irqlock, flags); ctx->dev->curr_ctx =3D NULL; --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E67F0C433FE for ; Sat, 1 Oct 2022 03:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233346AbiJAD1L (ORCPT ); Fri, 30 Sep 2022 23:27:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233213AbiJADZp (ORCPT ); Fri, 30 Sep 2022 23:25:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A5F2F80AC; Fri, 30 Sep 2022 20:17:55 -0700 (PDT) X-UUID: 5098f5f47bd443d6ba401e0c840e03b9-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1nRZij7FBP7nArpzIx+WOULHnjCn1SIwkAQdsuKIz9w=; b=CXikUgcIhAQ9AE8WP1DhnWbke+fNtpRctiPDn92gh/wQ29PnWzImEsgkZOy4GAE1OeL0BhRvkj2mxUvbX7yn2NXgs+D8QagqqsrmEFffmWr4sBjyLT9WRfZmriASgi6sBo89RlZxot0mzgMIO3pf+KTIhW37f5+YH7jgFX5Ndl8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:4c382812-cfc9-43ec-bfa9-eb212fe930d4,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:9aaba107-1cee-4c38-b21b-a45f9682fdc0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5098f5f47bd443d6ba401e0c840e03b9-20221001 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 68640158; Sat, 01 Oct 2022 11:17:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:48 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:47 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , "Tzung-Bi Shih" , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , "Irui Wang" , , , , , , Subject: [PATCH v6, 7/8] media: mediatek: vcodec: Add multi-core encoding process Date: Sat, 1 Oct 2022 11:17:36 +0800 Message-ID: <20221001031737.18266-8-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT8195 has two encoder hardware cores, when enable multi-core encoding, it is possiable to trying to use the two cores. According to hardware requirements, input frame 0 uses core0, frame 1 uses core1, then frame 2 uses core0, lock the device and enable clock by used core, and for sequence header encoding, it always use core0. Signed-off-by: Irui Wang --- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 7 +- .../platform/mediatek/vcodec/mtk_vcodec_enc.c | 10 +-- .../platform/mediatek/vcodec/mtk_vcodec_enc.h | 4 +- .../mediatek/vcodec/mtk_vcodec_enc_drv.c | 8 ++- .../mediatek/vcodec/mtk_vcodec_enc_hw.c | 7 +- .../mediatek/vcodec/mtk_vcodec_enc_hw.h | 2 - .../mediatek/vcodec/venc/venc_h264_if.c | 15 ++-- .../mediatek/vcodec/venc/venc_vp8_if.c | 3 +- .../platform/mediatek/vcodec/venc_drv_if.c | 69 ++++++++++++++----- .../platform/mediatek/vcodec/venc_drv_if.h | 4 ++ .../platform/mediatek/vcodec/venc_vpu_if.c | 25 +++++-- .../platform/mediatek/vcodec/venc_vpu_if.h | 3 +- 12 files changed, 110 insertions(+), 47 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index e074198a12ad..a75ba675f72b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -290,6 +290,7 @@ struct vdec_pic_info { * * @msg_queue: msg queue used to store lat buffer information. * @q_mutex: vb2_queue mutex. + * @encoded_frame_cnt: number of encoded frames */ struct mtk_vcodec_ctx { enum mtk_instance_type type; @@ -338,6 +339,7 @@ struct mtk_vcodec_ctx { struct vdec_msg_queue msg_queue; =20 struct mutex q_mutex; + int encoded_frame_cnt; }; =20 /* @@ -482,6 +484,7 @@ struct mtk_vcodec_enc_pdata { * @vdec_racing_info: record register value * @dec_racing_info_mutex: mutex lock used for inner racing mode * @enc_hw_dev: used to store venc core device + * @curr_enc_ctx: used to store current used enc context */ struct mtk_vcodec_dev { struct v4l2_device v4l2_dev; @@ -515,7 +518,8 @@ struct mtk_vcodec_dev { =20 /* decoder hardware mutex lock */ struct mutex dec_mutex[MTK_VDEC_HW_MAX]; - struct mutex enc_mutex; + /* encoder hardware mutex lock */ + struct mutex enc_mutex[MTK_VENC_HW_MAX]; =20 struct mtk_vcodec_pm pm; unsigned int dec_capability; @@ -534,6 +538,7 @@ struct mtk_vcodec_dev { struct mutex dec_racing_info_mutex; =20 void *enc_hw_dev[MTK_VENC_HW_MAX]; + struct mtk_vcodec_ctx *curr_enc_ctx[MTK_VENC_HW_MAX]; }; =20 static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c index 66e08e88dcc8..d15e106fb246 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c @@ -1242,6 +1242,8 @@ static void mtk_venc_worker(struct work_struct *work) enc_result.bs_size); } =20 + ctx->encoded_frame_cnt++; + v4l2_m2m_job_finish(ctx->dev->m2m_dev_enc, ctx->m2m_ctx); =20 mtk_v4l2_debug(1, "<=3D=3D=3D src_buf[%d] dst_buf[%d] venc_if_encode ret= =3D%d Size=3D%u=3D=3D=3D>", @@ -1451,19 +1453,19 @@ int mtk_vcodec_enc_queue_init(void *priv, struct vb= 2_queue *src_vq, return vb2_queue_init(dst_vq); } =20 -int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx) +int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx, int hw_id) { struct mtk_vcodec_dev *dev =3D ctx->dev; =20 - mutex_unlock(&dev->enc_mutex); + mutex_unlock(&dev->enc_mutex[hw_id]); return 0; } =20 -int mtk_venc_lock(struct mtk_vcodec_ctx *ctx) +int mtk_venc_lock(struct mtk_vcodec_ctx *ctx, int hw_id) { struct mtk_vcodec_dev *dev =3D ctx->dev; =20 - mutex_lock(&dev->enc_mutex); + mutex_lock(&dev->enc_mutex[hw_id]); return 0; } =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h index 513ee7993e34..29f5c8d1b59f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h @@ -39,8 +39,8 @@ struct mtk_video_enc_buf { extern const struct v4l2_ioctl_ops mtk_venc_ioctl_ops; extern const struct v4l2_m2m_ops mtk_venc_m2m_ops; =20 -int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx); -int mtk_venc_lock(struct mtk_vcodec_ctx *ctx); +int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx, int hw_id); +int mtk_venc_lock(struct mtk_vcodec_ctx *ctx, int hw_id); int mtk_vcodec_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq); void mtk_vcodec_enc_release(struct mtk_vcodec_ctx *ctx); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index 5bfbf4eead13..ba9c19a4d2cc 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -91,7 +91,7 @@ static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, vo= id *priv) void __iomem *addr; =20 spin_lock_irqsave(&dev->irqlock, flags); - ctx =3D dev->curr_ctx; + ctx =3D dev->curr_enc_ctx[MTK_VENC_CORE_0]; spin_unlock_irqrestore(&dev->irqlock, flags); =20 mtk_v4l2_debug(1, "id=3D%d coreid:%d", ctx->id, dev->venc_pdata->core_id); @@ -231,7 +231,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) struct video_device *vfd_enc; phandle rproc_phandle; enum mtk_vcodec_fw_type fw_type; - int ret; + int ret, i; =20 dev =3D devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); if (!dev) @@ -296,7 +296,9 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_res; } =20 - mutex_init(&dev->enc_mutex); + for (i =3D 0; i < MTK_VENC_HW_MAX; i++) + mutex_init(&dev->enc_mutex[i]); + mutex_init(&dev->dev_mutex); spin_lock_init(&dev->irqlock); =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c index 1ed4279925b7..6df5221b742f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c @@ -46,13 +46,14 @@ static void clean_hw_irq_status(unsigned int irq_status= , void __iomem *addr) static irqreturn_t mtk_enc_hw_irq_handler(int irq, void *priv) { struct mtk_venc_hw_dev *dev =3D priv; + struct mtk_vcodec_dev *main_dev =3D dev->main_dev; struct mtk_vcodec_ctx *ctx; unsigned long flags; void __iomem *addr; =20 - spin_lock_irqsave(&dev->main_dev->irqlock, flags); - ctx =3D dev->curr_ctx; - spin_unlock_irqrestore(&dev->main_dev->irqlock, flags); + spin_lock_irqsave(&main_dev->irqlock, flags); + ctx =3D main_dev->curr_enc_ctx[dev->hw_id]; + spin_unlock_irqrestore(&main_dev->irqlock, flags); if (!ctx) return IRQ_HANDLED; =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h index 9daea9665659..e8dfd46b3b01 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.h @@ -14,7 +14,6 @@ * @plat_dev: platform_device * @main_dev: main device * @pm: power management data - * @curr_ctx: the context that is waiting for venc hardware * @reg_base: mapped address of venc registers * @irq_status: venc hardware irq status * @enc_irq: venc device irq @@ -25,7 +24,6 @@ struct mtk_venc_hw_dev { struct mtk_vcodec_dev *main_dev; =20 struct mtk_vcodec_pm pm; - struct mtk_vcodec_ctx *curr_ctx; =20 void __iomem *reg_base; unsigned int irq_status; diff --git a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c b/d= rivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c index d7ed5c753a0e..32497a35afb1 100644 --- a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c @@ -500,7 +500,8 @@ static int h264_encode_sps(struct venc_h264_inst *inst, =20 mtk_vcodec_debug_enter(inst); =20 - ret =3D vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_SPS, NULL, bs_buf, N= ULL); + ret =3D vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_SPS, NULL, + bs_buf, NULL, MTK_VENC_CORE_0); if (ret) return ret; =20 @@ -526,7 +527,8 @@ static int h264_encode_pps(struct venc_h264_inst *inst, =20 mtk_vcodec_debug_enter(inst); =20 - ret =3D vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_PPS, NULL, bs_buf, N= ULL); + ret =3D vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_PPS, NULL, + bs_buf, NULL, MTK_VENC_CORE_0); if (ret) return ret; =20 @@ -568,7 +570,8 @@ static int h264_encode_header(struct venc_h264_inst *in= st, static int h264_encode_frame(struct venc_h264_inst *inst, struct venc_frm_buf *frm_buf, struct mtk_vcodec_mem *bs_buf, - unsigned int *bs_size) + unsigned int *bs_size, + int hw_id) { int ret =3D 0; unsigned int gop_size; @@ -599,7 +602,7 @@ static int h264_encode_frame(struct venc_h264_inst *ins= t, frame_info.frm_type); =20 ret =3D vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_FRAME, - frm_buf, bs_buf, &frame_info); + frm_buf, bs_buf, &frame_info, hw_id); if (ret) return ret; =20 @@ -728,7 +731,7 @@ static int h264_enc_encode(void *handle, =20 if (!inst->prepend_hdr) { ret =3D h264_encode_frame(inst, frm_buf, bs_buf, - &result->bs_size); + &result->bs_size, ctx->hw_id); if (ret) goto encode_err; result->is_key_frm =3D inst->vpu_inst.is_key_frm; @@ -756,7 +759,7 @@ static int h264_enc_encode(void *handle, tmp_bs_buf.size =3D bs_buf->size - (hdr_sz + filler_sz); =20 ret =3D h264_encode_frame(inst, frm_buf, &tmp_bs_buf, - &bs_size_frm); + &bs_size_frm, ctx->hw_id); if (ret) goto encode_err; =20 diff --git a/drivers/media/platform/mediatek/vcodec/venc/venc_vp8_if.c b/dr= ivers/media/platform/mediatek/vcodec/venc/venc_vp8_if.c index 56ce58f761f1..9eed39a4faa2 100644 --- a/drivers/media/platform/mediatek/vcodec/venc/venc_vp8_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc/venc_vp8_if.c @@ -302,7 +302,8 @@ static int vp8_enc_encode_frame(struct venc_vp8_inst *i= nst, =20 mtk_vcodec_debug(inst, "->frm_cnt=3D%d", inst->frm_cnt); =20 - ret =3D vpu_enc_encode(&inst->vpu_inst, 0, frm_buf, bs_buf, NULL); + ret =3D vpu_enc_encode(&inst->vpu_inst, 0, frm_buf, + bs_buf, NULL, MTK_VENC_CORE_0); if (ret) return ret; =20 diff --git a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c b/drivers= /media/platform/mediatek/vcodec/venc_drv_if.c index 6cbdb7e30bb3..53fa9a91d3fa 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc_drv_if.c @@ -16,6 +16,8 @@ #include "mtk_vcodec_enc.h" #include "mtk_vcodec_enc_pm.h" =20 +#define ODD_VENC_FRAME 0x1 + int venc_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc) { int ret =3D 0; @@ -31,9 +33,9 @@ int venc_if_init(struct mtk_vcodec_ctx *ctx, unsigned int= fourcc) return -EINVAL; } =20 - mtk_venc_lock(ctx); + mtk_venc_lock(ctx, ctx->hw_id); ret =3D ctx->enc_if->init(ctx); - mtk_venc_unlock(ctx); + mtk_venc_unlock(ctx, ctx->hw_id); =20 return ret; } @@ -43,9 +45,9 @@ int venc_if_set_param(struct mtk_vcodec_ctx *ctx, { int ret =3D 0; =20 - mtk_venc_lock(ctx); + mtk_venc_lock(ctx, ctx->hw_id); ret =3D ctx->enc_if->set_param(ctx->drv_handle, type, in); - mtk_venc_unlock(ctx); + mtk_venc_unlock(ctx, ctx->hw_id); =20 return ret; } @@ -56,24 +58,13 @@ int venc_if_encode(struct mtk_vcodec_ctx *ctx, struct venc_done_result *result) { int ret =3D 0; - unsigned long flags; =20 - mtk_venc_lock(ctx); + venc_encode_prepare(ctx, opt); =20 - spin_lock_irqsave(&ctx->dev->irqlock, flags); - ctx->dev->curr_ctx =3D ctx; - spin_unlock_irqrestore(&ctx->dev->irqlock, flags); - - mtk_vcodec_enc_clock_on(ctx->dev, 0); ret =3D ctx->enc_if->encode(ctx->drv_handle, opt, frm_buf, bs_buf, result); - mtk_vcodec_enc_clock_off(ctx->dev, 0); - - spin_lock_irqsave(&ctx->dev->irqlock, flags); - ctx->dev->curr_ctx =3D NULL; - spin_unlock_irqrestore(&ctx->dev->irqlock, flags); =20 - mtk_venc_unlock(ctx); + venc_encode_unprepare(ctx, opt, ret); return ret; } =20 @@ -84,11 +75,51 @@ int venc_if_deinit(struct mtk_vcodec_ctx *ctx) if (!ctx->drv_handle) return 0; =20 - mtk_venc_lock(ctx); + mtk_venc_lock(ctx, ctx->hw_id); ret =3D ctx->enc_if->deinit(ctx->drv_handle); - mtk_venc_unlock(ctx); + mtk_venc_unlock(ctx, ctx->hw_id); =20 ctx->drv_handle =3D NULL; =20 return ret; } + +void venc_encode_prepare(struct mtk_vcodec_ctx *ctx, + enum venc_start_opt opt) +{ + unsigned long flags; + + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + if (ctx->encoded_frame_cnt & ODD_VENC_FRAME) + ctx->hw_id =3D MTK_VENC_CORE_1; + else + ctx->hw_id =3D MTK_VENC_CORE_0; + } else { + ctx->hw_id =3D MTK_VENC_CORE_0; + } + + mtk_venc_lock(ctx, ctx->hw_id); + + spin_lock_irqsave(&ctx->dev->irqlock, flags); + ctx->dev->curr_enc_ctx[ctx->hw_id] =3D ctx; + spin_unlock_irqrestore(&ctx->dev->irqlock, flags); + + mtk_vcodec_enc_clock_on(ctx->dev, ctx->hw_id); +} + +void venc_encode_unprepare(struct mtk_vcodec_ctx *ctx, + enum venc_start_opt opt, int ret) +{ + unsigned long flags; + + if (ret || !IS_VENC_MULTICORE(ctx->dev->enc_capability) || + opt =3D=3D VENC_START_OPT_ENCODE_SEQUENCE_HEADER) { + mtk_vcodec_enc_clock_off(ctx->dev, ctx->hw_id); + + spin_lock_irqsave(&ctx->dev->irqlock, flags); + ctx->dev->curr_enc_ctx[ctx->hw_id] =3D NULL; + spin_unlock_irqrestore(&ctx->dev->irqlock, flags); + + mtk_venc_unlock(ctx, ctx->hw_id); + } +} diff --git a/drivers/media/platform/mediatek/vcodec/venc_drv_if.h b/drivers= /media/platform/mediatek/vcodec/venc_drv_if.h index 0b04a1020873..e676ccf6bd25 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/venc_drv_if.h @@ -167,4 +167,8 @@ int venc_if_encode(struct mtk_vcodec_ctx *ctx, struct mtk_vcodec_mem *bs_buf, struct venc_done_result *result); =20 +void venc_encode_prepare(struct mtk_vcodec_ctx *ctx, + enum venc_start_opt opt); +void venc_encode_unprepare(struct mtk_vcodec_ctx *ctx, + enum venc_start_opt opt, int ret); #endif /* _VENC_DRV_IF_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c b/drivers= /media/platform/mediatek/vcodec/venc_vpu_if.c index 09e7eaa25aab..fb1565a2ca49 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c @@ -226,7 +226,8 @@ static int vpu_enc_encode_32bits(struct venc_vpu_inst *= vpu, unsigned int bs_mode, struct venc_frm_buf *frm_buf, struct mtk_vcodec_mem *bs_buf, - struct venc_frame_info *frame_info) + struct venc_frame_info *frame_info, + int hw_id) { const bool is_ext =3D MTK_ENC_CTX_IS_EXT(vpu->ctx); size_t msg_size =3D is_ext ? @@ -262,6 +263,12 @@ static int vpu_enc_encode_32bits(struct venc_vpu_inst = *vpu, out.data[1] =3D frame_info->skip_frm_count; out.data[2] =3D frame_info->frm_type; } + + if (IS_VENC_MULTICORE(vpu->ctx->dev->enc_capability)) { + out.data_item =3D 4; + out.data[3] =3D hw_id; + } + if (vpu_enc_send_msg(vpu, &out, msg_size)) { mtk_vcodec_err(vpu, "AP_IPIMSG_ENC_ENCODE %d fail", bs_mode); @@ -275,7 +282,8 @@ static int vpu_enc_encode_34bits(struct venc_vpu_inst *= vpu, unsigned int bs_mode, struct venc_frm_buf *frm_buf, struct mtk_vcodec_mem *bs_buf, - struct venc_frame_info *frame_info) + struct venc_frame_info *frame_info, + int hw_id) { struct venc_ap_ipi_msg_enc_ext_34 out; size_t msg_size =3D sizeof(struct venc_ap_ipi_msg_enc_ext_34); @@ -309,6 +317,12 @@ static int vpu_enc_encode_34bits(struct venc_vpu_inst = *vpu, out.data[1] =3D frame_info->skip_frm_count; out.data[2] =3D frame_info->frm_type; } + + if (IS_VENC_MULTICORE(vpu->ctx->dev->enc_capability)) { + out.data_item =3D 4; + out.data[3] =3D hw_id; + } + if (vpu_enc_send_msg(vpu, &out, msg_size)) { mtk_vcodec_err(vpu, "AP_IPIMSG_ENC_ENCODE %d fail", bs_mode); @@ -321,16 +335,17 @@ static int vpu_enc_encode_34bits(struct venc_vpu_inst= *vpu, int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode, struct venc_frm_buf *frm_buf, struct mtk_vcodec_mem *bs_buf, - struct venc_frame_info *frame_info) + struct venc_frame_info *frame_info, + int hw_id) { int ret; =20 if (MTK_ENC_IOVA_IS_34BIT(vpu->ctx)) ret =3D vpu_enc_encode_34bits(vpu, bs_mode, - frm_buf, bs_buf, frame_info); + frm_buf, bs_buf, frame_info, hw_id); else ret =3D vpu_enc_encode_32bits(vpu, bs_mode, - frm_buf, bs_buf, frame_info); + frm_buf, bs_buf, frame_info, hw_id); =20 if (ret) return ret; diff --git a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.h b/drivers= /media/platform/mediatek/vcodec/venc_vpu_if.h index f83bc1b3f2bf..23efcea8d510 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.h +++ b/drivers/media/platform/mediatek/vcodec/venc_vpu_if.h @@ -45,7 +45,8 @@ int vpu_enc_set_param(struct venc_vpu_inst *vpu, int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode, struct venc_frm_buf *frm_buf, struct mtk_vcodec_mem *bs_buf, - struct venc_frame_info *frame_info); + struct venc_frame_info *frame_info, + int hw_id); int vpu_enc_deinit(struct venc_vpu_inst *vpu); =20 #endif --=20 2.18.0 From nobody Sat Apr 27 20:11:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D178C433FE for ; Sat, 1 Oct 2022 03:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232350AbiJAD1X (ORCPT ); Fri, 30 Sep 2022 23:27:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233273AbiJADZq (ORCPT ); Fri, 30 Sep 2022 23:25:46 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 208D9F80AE; Fri, 30 Sep 2022 20:17:55 -0700 (PDT) X-UUID: d1fa1afec6fe49afbf67a3593defbebe-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=YXsaGgrWcfTxB6frm3Y9+mK7+MQIPFMyxzTV3FpAegI=; b=Yn15yPPeK8pQd6DZDmC/ZJSyb0nhWHE+7GVAbiYWR2iqOrEScJDyF44eSc8cDvsptBIaJrhjUfHu/D/BD6qGkhJ68hn5sDCufQ9e66M1NuXIj6mjaOoIbj7wBL3ZXqGOgZnUnzVwW69ewFaBRawoF66C/ztj8USXpD44Sho3O44=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:9929a7da-49ce-44b0-a5cf-348f7a3305f3,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:ababa107-1cee-4c38-b21b-a45f9682fdc0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: d1fa1afec6fe49afbf67a3593defbebe-20221001 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1048704068; Sat, 01 Oct 2022 11:17:51 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 11:17:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 11:17:48 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Tzung-Bi Shih , , , Tiffany Lin CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , Subject: [PATCH v6, 8/8] media: mediatek: vcodec: Return encoding result in asynchronous mode Date: Sat, 1 Oct 2022 11:17:37 +0800 Message-ID: <20221001031737.18266-9-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001031737.18266-1-irui.wang@mediatek.com> References: <20221001031737.18266-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" when enable multi-core encoding, the wait IRQ done synchronous function should not be called, so the encoding result can't return to client in device_run. Move the buffer done function in IRQ handler. Signed-off-by: Irui Wang --- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 6 ++ .../platform/mediatek/vcodec/mtk_vcodec_enc.c | 72 +++++++++++++++++-- .../platform/mediatek/vcodec/mtk_vcodec_enc.h | 7 +- .../mediatek/vcodec/mtk_vcodec_enc_drv.c | 28 +++++++- .../mediatek/vcodec/mtk_vcodec_enc_hw.c | 13 +++- .../mediatek/vcodec/mtk_vcodec_enc_pm.c | 1 + .../mediatek/vcodec/mtk_vcodec_util.h | 1 + .../mediatek/vcodec/venc/venc_h264_if.c | 20 ++++-- .../platform/mediatek/vcodec/venc_drv_if.h | 2 + 9 files changed, 137 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index a75ba675f72b..d9c27ebcf3c3 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -291,6 +291,9 @@ struct vdec_pic_info { * @msg_queue: msg queue used to store lat buffer information. * @q_mutex: vb2_queue mutex. * @encoded_frame_cnt: number of encoded frames + * @pfrm_buf: used to store current ctx's frame buffer + * @pbs_buf: used to store current ctx's bitstream buffer + * @hdr_size: used to store prepend header size */ struct mtk_vcodec_ctx { enum mtk_instance_type type; @@ -340,6 +343,9 @@ struct mtk_vcodec_ctx { =20 struct mutex q_mutex; int encoded_frame_cnt; + struct vb2_v4l2_buffer *pfrm_buf[MTK_VENC_HW_MAX]; + struct vb2_v4l2_buffer *pbs_buf[MTK_VENC_HW_MAX]; + unsigned int hdr_size; }; =20 /* diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c index d15e106fb246..3424da4aaa26 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c @@ -958,6 +958,8 @@ static void vb2ops_venc_stop_streaming(struct vb2_queue= *q) =20 mtk_v4l2_debug(2, "[%d]-> type=3D%d", ctx->id, q->type); =20 + mtk_venc_lock_all(ctx); + if (q->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { while ((dst_buf =3D v4l2_m2m_dst_buf_remove(ctx->m2m_ctx))) { vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); @@ -1193,6 +1195,7 @@ static void mtk_venc_worker(struct work_struct *work) * is dequeued. */ if (src_buf =3D=3D &ctx->empty_flush_buf.vb) { + mtk_venc_lock_all(ctx); vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); dst_buf->flags |=3D V4L2_BUF_FLAG_LAST; v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); @@ -1207,9 +1210,12 @@ static void mtk_venc_worker(struct work_struct *work) frm_buf.fb_addr[i].size =3D (size_t)src_buf->vb2_buf.planes[i].length; } + frm_buf.frm_addr =3D src_buf; + bs_buf.va =3D vb2_plane_vaddr(&dst_buf->vb2_buf, 0); bs_buf.dma_addr =3D vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); bs_buf.size =3D (size_t)dst_buf->vb2_buf.planes[0].length; + bs_buf.buf =3D dst_buf; =20 mtk_v4l2_debug(2, "Framebuf PA=3D%llx Size=3D0x%zx;PA=3D0x%llx Size=3D0x%zx;PA=3D0x%llx S= ize=3D%zu", @@ -1235,11 +1241,14 @@ static void mtk_venc_worker(struct work_struct *wor= k) v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); mtk_v4l2_err("venc_if_encode failed=3D%d", ret); } else { - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_result.bs_size); - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); - mtk_v4l2_debug(2, "venc_if_encode bs size=3D%d", - enc_result.bs_size); + if (!IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + enc_result.bs_size); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + mtk_v4l2_debug(2, "venc_if_encode bs size=3D%d", + enc_result.bs_size); + } } =20 ctx->encoded_frame_cnt++; @@ -1453,6 +1462,34 @@ int mtk_vcodec_enc_queue_init(void *priv, struct vb2= _queue *src_vq, return vb2_queue_init(dst_vq); } =20 +void mtk_venc_buf_done(struct mtk_vcodec_ctx *ctx, int hw_id, + unsigned int bs_size, bool time_out, bool key_frame) +{ + struct vb2_v4l2_buffer *src_vb2_v4l2 =3D NULL; + struct vb2_v4l2_buffer *dst_vb2_v4l2 =3D NULL; + + /* + * the frm_buf(src_buf) and bs_buf(dst_buf) can be obtained from ctx, + * then put them to done list, user can get them by dqbuf call + */ + src_vb2_v4l2 =3D ctx->pfrm_buf[hw_id]; + dst_vb2_v4l2 =3D ctx->pbs_buf[hw_id]; + + if (src_vb2_v4l2 && dst_vb2_v4l2) { + dst_vb2_v4l2->vb2_buf.timestamp =3D + src_vb2_v4l2->vb2_buf.timestamp; + dst_vb2_v4l2->timecode =3D src_vb2_v4l2->timecode; + + if (key_frame) + dst_vb2_v4l2->flags |=3D V4L2_BUF_FLAG_KEYFRAME; + + v4l2_m2m_buf_done(src_vb2_v4l2, VB2_BUF_STATE_DONE); + vb2_set_plane_payload(&dst_vb2_v4l2->vb2_buf, 0, bs_size); + v4l2_m2m_buf_done(dst_vb2_v4l2, VB2_BUF_STATE_DONE); + } +} +EXPORT_SYMBOL_GPL(mtk_venc_buf_done); + int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx, int hw_id) { struct mtk_vcodec_dev *dev =3D ctx->dev; @@ -1460,6 +1497,7 @@ int mtk_venc_unlock(struct mtk_vcodec_ctx *ctx, int h= w_id) mutex_unlock(&dev->enc_mutex[hw_id]); return 0; } +EXPORT_SYMBOL_GPL(mtk_venc_unlock); =20 int mtk_venc_lock(struct mtk_vcodec_ctx *ctx, int hw_id) { @@ -1468,6 +1506,30 @@ int mtk_venc_lock(struct mtk_vcodec_ctx *ctx, int hw= _id) mutex_lock(&dev->enc_mutex[hw_id]); return 0; } +EXPORT_SYMBOL_GPL(mtk_venc_lock); + +void mtk_venc_lock_all(struct mtk_vcodec_ctx *ctx) +{ + unsigned int i; + struct mtk_vcodec_dev *dev =3D ctx->dev; + + /* + * For multi-core mode encoding, there are may be bufs being encoded + * when get the empty flush buffer or stop streaming, for example, the + * buffer with LAST flag will return to client before the encoding + * buffers, which will cause frame lost. + * The encoder device mutex will be locked during encoding process, + * when encode done, the mutex unlocked. So if all encoder device mutex + * can be locked, which means there are no bufs being encoded at this + * time, then the buffer with LAST flag can return to client properly. + */ + + for (i =3D 0; i < MTK_VENC_HW_MAX; i++) { + mutex_lock(&dev->enc_mutex[i]); + mutex_unlock(&dev->enc_mutex[i]); + } +} +EXPORT_SYMBOL_GPL(mtk_venc_lock_all); =20 void mtk_vcodec_enc_release(struct mtk_vcodec_ctx *ctx) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h index 29f5c8d1b59f..5ab17381c7ba 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.h @@ -20,6 +20,9 @@ =20 #define MTK_VENC_IRQ_STATUS_OFFSET 0x05C #define MTK_VENC_IRQ_ACK_OFFSET 0x060 +#define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098 +#define VENC_PIC_FRM_TYPE 0x0010 +#define VENC_PIC_KEY_FRM 0x2 =20 /** * struct mtk_video_enc_buf - Private data related to each VB2 buffer. @@ -46,5 +49,7 @@ int mtk_vcodec_enc_queue_init(void *priv, struct vb2_queu= e *src_vq, void mtk_vcodec_enc_release(struct mtk_vcodec_ctx *ctx); int mtk_vcodec_enc_ctrls_setup(struct mtk_vcodec_ctx *ctx); void mtk_vcodec_enc_set_default_params(struct mtk_vcodec_ctx *ctx); - +void mtk_venc_buf_done(struct mtk_vcodec_ctx *ctx, int hw_id, + unsigned int bs_size, bool time_out, bool key_frame); +void mtk_venc_lock_all(struct mtk_vcodec_ctx *ctx); #endif /* _MTK_VCODEC_ENC_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index ba9c19a4d2cc..b34d7583fccc 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -89,6 +89,9 @@ static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, vo= id *priv) struct mtk_vcodec_ctx *ctx; unsigned long flags; void __iomem *addr; + unsigned int bs_size; + unsigned int frm_type; + bool is_key_frame =3D 0; =20 spin_lock_irqsave(&dev->irqlock, flags); ctx =3D dev->curr_enc_ctx[MTK_VENC_CORE_0]; @@ -101,8 +104,32 @@ static irqreturn_t mtk_vcodec_enc_irq_handler(int irq,= void *priv) ctx->irq_status =3D readl(dev->reg_base[dev->venc_pdata->core_id] + (MTK_VENC_IRQ_STATUS_OFFSET)); =20 + bs_size =3D readl(dev->reg_base[dev->venc_pdata->core_id] + + (VENC_PIC_BITSTREAM_BYTE_CNT)); + frm_type =3D readl(dev->reg_base[dev->venc_pdata->core_id] + + (VENC_PIC_FRM_TYPE)); + clean_irq_status(ctx->irq_status, addr); =20 + if (IS_VENC_MULTICORE(dev->enc_capability)) { + if (ctx->irq_status & MTK_VENC_IRQ_STATUS_FRM) { + if (ctx->hdr_size !=3D 0) { + bs_size +=3D ctx->hdr_size; + ctx->hdr_size =3D 0; + } + + if (frm_type & VENC_PIC_KEY_FRM) + is_key_frame =3D 1; + + mtk_venc_buf_done(ctx, 0, bs_size, 0, is_key_frame); + mtk_vcodec_enc_clock_off(dev, 0); + mtk_venc_unlock(ctx, 0); + } else { + wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0); + } + return IRQ_HANDLED; + } + wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0); return IRQ_HANDLED; } @@ -284,7 +311,6 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_res; } =20 - irq_set_status_flags(dev->enc_irq, IRQ_NOAUTOEN); ret =3D devm_request_irq(&pdev->dev, dev->enc_irq, mtk_vcodec_enc_irq_handler, 0, pdev->name, dev); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c index 6df5221b742f..0367e59b20a9 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_hw.c @@ -50,6 +50,9 @@ static irqreturn_t mtk_enc_hw_irq_handler(int irq, void *= priv) struct mtk_vcodec_ctx *ctx; unsigned long flags; void __iomem *addr; + unsigned int bs_size; + unsigned int frm_type; + bool is_key_frame =3D 0; =20 spin_lock_irqsave(&main_dev->irqlock, flags); ctx =3D main_dev->curr_enc_ctx[dev->hw_id]; @@ -61,9 +64,17 @@ static irqreturn_t mtk_enc_hw_irq_handler(int irq, void = *priv) =20 addr =3D dev->reg_base + MTK_VENC_IRQ_ACK_OFFSET; ctx->irq_status =3D readl(dev->reg_base + MTK_VENC_IRQ_STATUS_OFFSET); + bs_size =3D readl(dev->reg_base + VENC_PIC_BITSTREAM_BYTE_CNT); + frm_type =3D readl(dev->reg_base + VENC_PIC_FRM_TYPE); clean_hw_irq_status(ctx->irq_status, addr); =20 - wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0); + if (frm_type & VENC_PIC_KEY_FRM) + is_key_frame =3D 1; + + mtk_venc_buf_done(ctx, dev->hw_id, bs_size, 0, is_key_frame); + mtk_vcodec_enc_clock_off(main_dev, dev->hw_id); + mtk_venc_unlock(ctx, dev->hw_id); + return IRQ_HANDLED; } =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c index 2f83aade779a..af2968a8d2e5 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_pm.c @@ -235,3 +235,4 @@ void mtk_vcodec_enc_clock_off(struct mtk_vcodec_dev *de= v, for (i =3D enc_clk->clk_num - 1; i >=3D 0; i--) clk_disable(enc_clk->clk_info[i].vcodec_clk); } +EXPORT_SYMBOL_GPL(mtk_vcodec_enc_clock_off); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h b/dri= vers/media/platform/mediatek/vcodec/mtk_vcodec_util.h index 0033c53d5589..cecf78d6d4c6 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h @@ -15,6 +15,7 @@ struct mtk_vcodec_mem { size_t size; void *va; dma_addr_t dma_addr; + void *buf; }; =20 struct mtk_vcodec_fb { diff --git a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c b/d= rivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c index 32497a35afb1..a6990221d845 100644 --- a/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc/venc_h264_if.c @@ -22,7 +22,6 @@ static const char h264_filler_marker[] =3D {0x0, 0x0, 0x0, 0x1, 0xc}; =20 #define H264_FILLER_MARKER_SIZE ARRAY_SIZE(h264_filler_marker) -#define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098 =20 /* * enum venc_h264_frame_type - h264 encoder output bitstream frame type @@ -620,6 +619,11 @@ static int h264_encode_frame(struct venc_h264_inst *in= st, return ret; } =20 + if (IS_VENC_MULTICORE(ctx->dev->enc_capability)) { + ++inst->frm_cnt; + return ret; + } + irq_status =3D h264_enc_wait_venc_done(inst); if (irq_status !=3D MTK_VENC_IRQ_STATUS_FRM) { mtk_vcodec_err(inst, "irq_status=3D%d failed", irq_status); @@ -705,8 +709,6 @@ static int h264_enc_encode(void *handle, =20 mtk_vcodec_debug(inst, "opt %d ->", opt); =20 - enable_irq(ctx->dev->enc_irq); - switch (opt) { case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: { unsigned int bs_size_hdr; @@ -729,6 +731,13 @@ static int h264_enc_encode(void *handle, unsigned int bs_size_hdr; unsigned int bs_size_frm; =20 + /* + * the frm_buf and bs_buf need to recorded into current ctx, + * when encoding done, the target buffers can be got from ctx. + */ + ctx->pfrm_buf[ctx->hw_id] =3D frm_buf->frm_addr; + ctx->pbs_buf[ctx->hw_id] =3D bs_buf->buf; + if (!inst->prepend_hdr) { ret =3D h264_encode_frame(inst, frm_buf, bs_buf, &result->bs_size, ctx->hw_id); @@ -763,7 +772,9 @@ static int h264_enc_encode(void *handle, if (ret) goto encode_err; =20 - result->bs_size =3D hdr_sz + filler_sz + bs_size_frm; + ctx->hdr_size =3D hdr_sz + filler_sz; + + result->bs_size =3D ctx->hdr_size + bs_size_frm; =20 mtk_vcodec_debug(inst, "hdr %d filler %d frame %d bs %d", hdr_sz, filler_sz, bs_size_frm, @@ -782,7 +793,6 @@ static int h264_enc_encode(void *handle, =20 encode_err: =20 - disable_irq(ctx->dev->enc_irq); mtk_vcodec_debug(inst, "opt %d <-", opt); =20 return ret; diff --git a/drivers/media/platform/mediatek/vcodec/venc_drv_if.h b/drivers= /media/platform/mediatek/vcodec/venc_drv_if.h index e676ccf6bd25..7e24b7f573d7 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/venc_drv_if.h @@ -108,9 +108,11 @@ struct venc_frame_info { /* * struct venc_frm_buf - frame buffer information used in venc_if_encode() * @fb_addr: plane frame buffer addresses + * @frm_addr: current v4l2 buffer address */ struct venc_frm_buf { struct mtk_vcodec_fb fb_addr[MTK_VCODEC_MAX_PLANES]; + void *frm_addr; }; =20 /* --=20 2.18.0