From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EDBAC433F5 for ; Sat, 1 Oct 2022 03:10:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232763AbiJADKE (ORCPT ); Fri, 30 Sep 2022 23:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231261AbiJADHp (ORCPT ); Fri, 30 Sep 2022 23:07:45 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D36F112756B; Fri, 30 Sep 2022 20:07:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664593635; x=1696129635; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HGeHmBa6YcmbjD9Y00yOaHackZg+P1/x9KaKApAyEZo=; b=gWh6q09YlnxvwmfIuPbZOCTAj9E50wNwYLyZcmKurANS2LGLxyRtIAm0 Eq5hIMXbpCJ1aglytfLBkPdz3YgwkQzrzTSESN4gop0MU31ow2SYcKUyi yA9sNg/yHHasVZq1UyaNYnnk5V+FCYxxRHHt3Z9Dzm2OjF7WCJrtM2IZF 0=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 30 Sep 2022 20:07:12 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:07:12 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:12 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Date: Fri, 30 Sep 2022 20:06:38 -0700 Message-ID: <20221001030656.29365-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to boot to shell with console on these SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 + arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 + 3 files changed, 390 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi new file mode 100644 index 000000000000..3610f94bef35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen: chosen { }; + + + clocks { + xo_board: xo_board { + compatible =3D "fixed-clock"; + clock-frequency =3D <19200000>; + clock-output-names =3D "xo_board"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&L2_0>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + next-level-cache =3D <&L2_100>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + next-level-cache =3D <&L2_200>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + next-level-cache =3D <&L2_300>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + SILVER_OFF: silver-c4 { /* C4 */ + compatible =3D "arm,idle-state"; + idle-state-name =3D "rail-pc"; + entry-latency-us =3D <274>; + exit-latency-us =3D <480>; + min-residency-us =3D <3934>; + arm,psci-suspend-param =3D <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible =3D "domain-idle-state"; + idle-state-name =3D "l3-off"; + entry-latency-us =3D <584>; + exit-latency-us =3D <2332>; + min-residency-us =3D <6118>; + arm,psci-suspend-param =3D <0x41000044>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible =3D "domain-idle-state"; + idle-state-name =3D "llcc-off"; + entry-latency-us =3D <2893>; + exit-latency-us =3D <4023>; + min-residency-us =3D <9987>; + arm,psci-suspend-param =3D <0x41003344>; + }; + }; + + firmware { + qcom_scm { + compatible =3D "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; + #reset-cells =3D <1>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&SILVER_OFF>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&SILVER_OFF>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&SILVER_OFF>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&SILVER_OFF>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_PWR_DN &APSS_OFF>; + }; + }; + + soc: soc@0 { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + compatible =3D "simple-bus"; + + gcc: clock-controller@80000 { + compatible =3D "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; + reg =3D <0x0 0x80000 0x0 0x1f4200>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names =3D "bi_tcxo", "sleep_clk"; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x9c0000 0x0 0x2000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + uart7: serial@99c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x99c000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,pdc"; + reg =3D <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + reg-names =3D "pdc-interrupt-base", "apss-shared-spi-cfg"; + qcom,pdc-ranges =3D <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17200000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + reg =3D <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ + interrupts =3D ; + }; + + timer@17420000 { + compatible =3D "arm,armv7-timer-mem"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + reg =3D <0x0 0x17420000 0x0 0x1000>; + clock-frequency =3D <19200000>; + + frame@17421000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0 0x17423000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17425000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0 0x17425000 0x0 0x1000>, + <0x0 0x17426000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17427000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0 0x17427000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17429000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0 0x17429000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@1742b000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0 0x1742b000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@1742d000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0 0x1742d000 0x0 0x1000>; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label =3D "apps_rsc"; + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + + apps_bcm_voter: bcm_voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + clock-frequency =3D <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qc= om/qdu1000.dtsi new file mode 100644 index 000000000000..ba195e7ffc38 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdru1000.dtsi" + +/ { + qcom,msm-id =3D <545 0x10000>, <587 0x10000>; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qc= om/qru1000.dtsi new file mode 100644 index 000000000000..1639a4b3c1fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdru1000.dtsi" + +/ { + qcom,msm-id =3D <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000= >; +}; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F18E6C4332F for ; Sat, 1 Oct 2022 03:11:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233130AbiJADLH (ORCPT ); Fri, 30 Sep 2022 23:11:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232692AbiJADHu (ORCPT ); Fri, 30 Sep 2022 23:07:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24A5F163B72; Fri, 30 Sep 2022 20:07:20 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912vYjd003214; Sat, 1 Oct 2022 03:07:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=qg785rpN0qJdVgEHE8JUNmbmgO9HtAOsYqhjC9sU78E=; b=J9brdKE3wD+ZPDdOUYzhb0s4shuO6VmETzek7GAjaNZqX0G71NAED3V+rx/m8wdC3mou WsM9LJdY1sf3hRwtjDcaWtWqRiGiwxof/gerEkL97xO0HEcDZpG7K9YCcchdL4Vn1dnL H/J/Vg5ZsagZu60bT/yBII4ErvnX+bLOMRIUAFZtGf5bgydH6iuaWDmAU673U6xn1weY oGweypZYY7xtbA7mYGmetRsc38VrTiO1xHaG8l+MW7SJOGLgxT0uhwT7/m1tw/Zvg2mR cvFkg4mA3X3qBbi7T34SOxAoB402f1FMRhRTMo+gjIsyGVYtN5/mIfjArQcAocB/k5V1 QQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jwwfck4cu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:07:13 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29137DjO031535 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:07:13 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:12 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Date: Fri, 30 Sep 2022 20:06:39 -0700 Message-ID: <20221001030656.29365-3-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4GqglR6j17rXFfgvvi5kAuoUxCQgmije X-Proofpoint-ORIG-GUID: 4GqglR6j17rXFfgvvi5kAuoUxCQgmije X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=925 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1d86a33de528..398920c530b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8350-sony-xperia-sagami-= pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8350-sony-xperia-sagami-pdx215.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts= /qcom/qdu1000-idp.dts new file mode 100644 index 000000000000..0ecf9a7c41ec --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "qdu1000.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. QDU1000 IDP"; + compatible =3D "qcom,qdu1000-idp", "qcom,qdu1000"; + qcom,board-id =3D <0x22 0x0>; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&uart7 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts= /qcom/qru1000-idp.dts new file mode 100644 index 000000000000..ddb4ea17f7d2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "qru1000.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. QRU1000 IDP"; + compatible =3D "qcom,qru1000-idp", "qcom,qru1000"; + qcom,board-id =3D <0x22 0x0>; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&uart7 { + status =3D "okay"; +}; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8CFAC433FE for ; Sat, 1 Oct 2022 03:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232846AbiJADKY (ORCPT ); Fri, 30 Sep 2022 23:10:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231854AbiJADHq (ORCPT ); Fri, 30 Sep 2022 23:07:46 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D290B98A78; Fri, 30 Sep 2022 20:07:16 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912uJSm004685; Sat, 1 Oct 2022 03:07:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=hFnUFuEMF5I0mO528pZxcMDQLBDaselO4QfZjPs0xds=; b=cCrUdczWYX5vb/+WLNrX5y9P9+xTE1NKi/wMfcn4jAWaD5B26z55fcXlLUAqP4j+tkEb 078tgiSlCFE5uixMmJ2ggIlxxkw1tOusNcRhTKIUZxZ20i8qJAHaz7/VmExhQop9Y2ly EgTfv5hNsSd1sh4NXqpuT/4AMT6YVVoyWPhLJHbjiRF5fMbKUT7zxwK4WVE13tPf3ta/ QTMu84EzZacp5sLP0nHofuiJCewi97B9OjU3IZU9/MYj2gpLxVKa71hXokGwWUwcE5o2 uhDK/BGWPwglDS9Rs1sxYpbpJVW9PtPfT8f4lqXD3P8Xy4wmTU+OvY0SoDpPo+dai/dm yg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jx6by8tws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:07:13 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29137DH9009833 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:07:13 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:12 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Date: Fri, 30 Sep 2022 20:06:40 -0700 Message-ID: <20221001030656.29365-4-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 17URZsvXSK8cBqRqnA9EHj9gNI-Ri6WI X-Proofpoint-ORIG-GUID: 17URZsvXSK8cBqRqnA9EHj9gNI-Ri6WI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=716 bulkscore=0 spamscore=0 phishscore=0 mlxscore=0 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin configuration. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 3610f94bef35..39b9a00d3ad8 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -235,6 +235,8 @@ uart7: serial@99c000 { reg =3D <0x0 0x99c000 0x0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart7_default>; interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + tlmm: pinctrl@f000000 { + compatible =3D "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; + reg =3D <0x0 0xf000000 0x0 0x1000000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 151>; + wakeup-parent =3D <&pdc>; + + qup_uart7_default: qup-uart7-default { + tx { + pins =3D "gpio134"; + function =3D "qup0_se7_l2"; + drive-strength =3D <2>; + bias-disable; + }; + + rx { + pins =3D "gpio135"; + function =3D "qup0_se7_l3"; + drive-strength =3D <2>; + bias-disable; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,pdc"; reg =3D <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EF8EC433FE for ; Sat, 1 Oct 2022 03:10:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233077AbiJADK3 (ORCPT ); Fri, 30 Sep 2022 23:10:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232578AbiJADHq (ORCPT ); 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charset="utf-8" Add reserved memory nodes for QDU1000 SoCs based on downstream documentation. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 150 ++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qc= om/qdu1000.dtsi index ba195e7ffc38..e836b2c1b8df 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -7,4 +7,154 @@ =20 / { qcom,msm-id =3D <545 0x10000>, <587 0x10000>; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: memory@80000000 { + no-map; + reg =3D <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dt_log_mem: memory@80600000 { + no-map; + reg =3D <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: memory@80640000 { + no-map; + reg =3D <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: memory@80800000 { + no-map; + reg =3D <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible =3D "qcom,cmd-db"; + no-map; + reg =3D <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: memory@80880000 { + no-map; + reg =3D <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: memory@808a0000 { + no-map; + reg =3D <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: memory@808e0000 { + no-map; + reg =3D <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: memory@808e4000 { + no-map; + reg =3D <0x0 0x808e4000 0x0 0x10000>; + }; + + /* secdata region can be reused by apps */ + + smem_mem: memory@80900000 { + compatible =3D "qcom,smem"; + no-map; + reg =3D <0x0 0x80900000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: memory@80b00000 { + no-map; + reg =3D <0x0 0x80b00000 0x0 0x100000>; + }; + + xbl_sc_mem: memory@80c00000 { + no-map; + reg =3D <0x0 0x80c00000 0x0 0x40000>; + }; + + /* uefi region can be reused by apps */ + + tz_stat_mem: memory@81d00000 { + no-map; + reg =3D <0x0 0x81d00000 0x0 0x100000>; + }; + + tags_mem: memory@81e00000 { + no-map; + reg =3D <0x0 0x81e00000 0x0 0x500000>; + }; + + qtee_mem: memory@82300000 { + no-map; + reg =3D <0x0 0x82300000 0x0 0x500000>; + }; + + ta_mem: memory@82800000 { + no-map; + reg =3D <0x0 0x82800000 0x0 0xa00000>; + }; + + fs1_mem: memory@83200000 { + no-map; + reg =3D <0x0 0x83200000 0x0 0x400000>; + }; + + fs2_mem: memory@83600000 { + no-map; + reg =3D <0x0 0x83600000 0x0 0x400000>; + }; + + fs3_mem: memory@83a00000 { + no-map; + reg =3D <0x0 0x83a00000 0x0 0x400000>; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: memory@8be00000 { + no-map; + reg =3D <0x0 0x8be00000 0x0 0x10000>; + }; + + ipa_gsi_mem: memory@8be10000 { + no-map; + reg =3D <0x0 0x8be10000 0x0 0x14000>; + }; + + mpss_mem: memory@8c000000 { + no-map; + reg =3D <0x0 0x8c000000 0x0 0x12c00000>; + }; + + q6_mpss_dtb_mem: memory@9ec00000 { + no-map; + reg =3D <0x0 0x9ec00000 0x0 0x80000>; + }; + + tenx_mem: memory@a0000000 { + no-map; + reg =3D <0x0 0xa0000000 0x0 0x19600000>; + }; + + oem_tenx_mem: memory@b9600000 { + no-map; + reg =3D <0x0 0xb9600000 0x0 0x6a00000>; + }; + + tenx_q6_buffer_mem: memory@c0000000 { + no-map; + reg =3D <0x0 0xc0000000 0x0 0x3200000>; + }; + + ipa_buffer_mem: memory@c3200000 { + no-map; + reg =3D <0x0 0xc3200000 0x0 0x12c00000>; + }; + }; }; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42309C433F5 for ; Sat, 1 Oct 2022 03:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233080AbiJADKd (ORCPT ); Fri, 30 Sep 2022 23:10:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232512AbiJADHq (ORCPT ); Fri, 30 Sep 2022 23:07:46 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4805DCEE95; Fri, 30 Sep 2022 20:07:17 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912eaC0005418; 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Sat, 1 Oct 2022 03:07:13 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:13 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 05/19] arm64: dts: qcom: qru1000: Add reserved memory nodes Date: Fri, 30 Sep 2022 20:06:42 -0700 Message-ID: <20221001030656.29365-6-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gDgFBaSCng6g957E273jzm8Wr3UaJyFi X-Proofpoint-ORIG-GUID: gDgFBaSCng6g957E273jzm8Wr3UaJyFi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 mlxlogscore=765 adultscore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add reserved memory nodes for QRU1000 SoCs based on downstream documentation. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qru1000.dtsi | 145 ++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qc= om/qru1000.dtsi index 1639a4b3c1fb..be74be4bee4b 100644 --- a/arch/arm64/boot/dts/qcom/qru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -7,4 +7,149 @@ =20 / { qcom,msm-id =3D <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000= >; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: memory@80000000 { + no-map; + reg =3D <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dt_log_mem: memory@80600000 { + no-map; + reg =3D <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: memory@80640000 { + no-map; + reg =3D <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: memory@80800000 { + no-map; + reg =3D <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible =3D "qcom,cmd-db"; + no-map; + reg =3D <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: memory@80880000 { + no-map; + reg =3D <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: memory@808a0000 { + no-map; + reg =3D <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: memory@808e0000 { + no-map; + reg =3D <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: memory@808e4000 { + no-map; + reg =3D <0x0 0x808e4000 0x0 0x10000>; + }; + + /* secdata region can be reused by apps */ + + smem_mem: memory@80900000 { + compatible =3D "qcom,smem"; + no-map; + reg =3D <0x0 0x80900000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: memory@80b00000 { + no-map; + reg =3D <0x0 0x80b00000 0x0 0x100000>; + }; + + xbl_sc_mem: memory@80c00000 { + no-map; + reg =3D <0x0 0x80c00000 0x0 0x40000>; + }; + + /* uefi region can be reused by apps */ + + tz_stat_mem: memory@81d00000 { + no-map; + reg =3D <0x0 0x81d00000 0x0 0x100000>; + }; + + tags_mem: memory@81e00000 { + no-map; + reg =3D <0x0 0x81e00000 0x0 0x500000>; + }; + + qtee_mem: memory@82300000 { + no-map; + reg =3D <0x0 0x82300000 0x0 0x500000>; + }; + + truested_apps_mem: memory@82800000 { + no-map; + reg =3D <0x0 0x82800000 0x0 0xa00000>; + }; + + fs1_mem: memory@83200000 { + no-map; + reg =3D <0x0 0x83200000 0x0 0x400000>; + }; + + fs2_mem: memory@83600000 { + no-map; + reg =3D <0x0 0x83600000 0x0 0x400000>; + }; + + fs3_mem: memory@83a00000 { + no-map; + reg =3D <0x0 0x83a00000 0x0 0x400000>; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: memory@8be00000 { + no-map; + reg =3D <0x0 0x8be00000 0x0 0x10000>; + }; + + ipa_gsi_mem: memory@8be10000 { + no-map; + reg =3D <0x0 0x8be10000 0x0 0x14000>; + }; + + mpss_mem: memory@8c000000 { + no-map; + reg =3D <0x0 0x8c000000 0x0 0x12c00000>; + }; + + q6_mpss_dtb_mem: memory@9ec00000 { + no-map; + reg =3D <0x0 0x9ec00000 0x0 0x80000>; + }; + + oem_tenx_mem: memory@a0000000 { + no-map; + reg =3D <0x0 0xa0000000 0x0 0x6400000>; + }; + + mpss_diag_buffer_mem: memory@aea00000 { + no-map; + reg =3D <0x0 0xaea00000 0x0 0x6400000>; + }; + + tenx_q6_buffer_mem: memory@b4e00000 { + no-map; + reg =3D <0x0 0xb4e00000 0x0 0x3200000>; + }; + }; }; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A568CC433FE for ; Sat, 1 Oct 2022 03:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232673AbiJADKL (ORCPT ); Fri, 30 Sep 2022 23:10:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232470AbiJADHp (ORCPT ); Fri, 30 Sep 2022 23:07:45 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D392615FC71; Fri, 30 Sep 2022 20:07:14 -0700 (PDT) DKIM-Signature: v=1; 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charset="utf-8" Add smmu nodes for the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 ++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 39b9a00d3ad8..8c2af08b8329 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -396,5 +396,62 @@ arch_timer: timer { ; clock-frequency =3D <19200000>; }; + + apps_smmu: apps-smmu@15000000 { + compatible =3D "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; }; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E0AAC433F5 for ; Sat, 1 Oct 2022 03:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233105AbiJADKy (ORCPT ); Fri, 30 Sep 2022 23:10:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232229AbiJADHt (ORCPT ); Fri, 30 Sep 2022 23:07:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23FA7163B47; Fri, 30 Sep 2022 20:07:19 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29136Ubh020631; Sat, 1 Oct 2022 03:07:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=0aqwhcP2681e88QJCWfSaOCEPi+FRlsHU8/h2e7vaoA=; b=nds/c8fJlX3SW1kiPEwOVLqQmx+6x6Oy81EssljojkalFSPW11xKxwWEcPGlKy03NLU+ Sqog0ZliQjoZb03rZ+o/rB+mNwQBQPrEl/ckpSJVwNuoH1oSRyu+ZEkL5b644ci/TDJD /p+wrnS8Ej5LeV3vEZZWb8h9sncIkz2wyxYNlNm3P2Kda/wLXwOCNpNHja3EO9T/T5AO 3wqClPIE3Czcv4Lgwinaiu7x6V6aOdxERgcfUuoYooZ/Lq+KRQNxeCyVo0yRAZjxZuxh Pv9yN9MLbFAIF/Z8cHnljG3JslAf2c5yyOmRXEmISuBa15a1SHgMR1RATM8953+OpS2h 3A== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jwj1bvdyx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:07:15 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29137EfU031567 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:07:14 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:14 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Date: Fri, 30 Sep 2022 20:06:44 -0700 Message-ID: <20221001030656.29365-8-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DPalbrIehKeJhCwA-XEW66wKFps3HuBN X-Proofpoint-ORIG-GUID: DPalbrIehKeJhCwA-XEW66wKFps3HuBN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=806 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 mlxscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add RPMH regulators for the QDU1000 IDP platform. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 200 +++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts= /qcom/qdu1000-idp.dts index 0ecf9a7c41ec..654b50220c2e 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -5,6 +5,7 @@ =20 /dts-v1/; =20 +#include #include "qdu1000.dtsi" =20 / { @@ -19,6 +20,205 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + ppvar_sys: ppvar-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&ppvar_sys>; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + + vdd-l1-l8-l11-supply =3D <&vreg_s6a_0p9>; + vdd-l2-l10-supply =3D <&vph_pwr>; + vdd-l3-l4-l5-l18-supply =3D <&vreg_s5a_2p0>; + vdd-l6-l9-supply =3D <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply =3D <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name =3D "vreg_s2a_0p5"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name =3D "vreg_s3a_1p05"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name =3D "vreg_s4a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name =3D "vreg_s5a_2p0"; + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name =3D "vreg_s6a_0p9"; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name =3D "vreg_s7a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name =3D "vreg_s8a_1p3"; + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name =3D "vreg_l1a_0p91"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name =3D "vreg_l2a_2p3"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name =3D "vreg_l3a_1p2"; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name =3D "vreg_l5a_0p8"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name =3D "vreg_l6a_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name =3D "vreg_l7a_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name =3D "vreg_l8a_0p91"; + regulator-min-microvolt =3D <888000>; + regulator-max-microvolt =3D <925000>; + regulator-initial-mode =3D ; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name =3D "vreg_l8a_0p91"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name =3D "vreg_l10a_2p95"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name =3D "vreg_l11a_0p91"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name =3D "vreg_l12a_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name =3D "vreg_l14a_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name =3D "vreg_l15a_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name =3D "vreg_l16a_1p8"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name =3D "vreg_l17a_3p3"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name =3D "vreg_l18a_1p2"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + }; }; =20 &qupv3_id_0 { --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F24D0C433FE for ; Sat, 1 Oct 2022 03:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233100AbiJADKp (ORCPT ); Fri, 30 Sep 2022 23:10:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231938AbiJADHq (ORCPT ); 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Fri, 30 Sep 2022 20:07:14 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 08/19] arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes Date: Fri, 30 Sep 2022 20:06:45 -0700 Message-ID: <20221001030656.29365-9-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add RPMH regulators for the QRU1000 IDP platform. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 200 +++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts= /qcom/qru1000-idp.dts index ddb4ea17f7d2..8d27923dc470 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -5,6 +5,7 @@ =20 /dts-v1/; =20 +#include #include "qru1000.dtsi" =20 / { @@ -19,6 +20,205 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + ppvar_sys: ppvar-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&ppvar_sys>; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + + vdd-l1-l8-l11-supply =3D <&vreg_s6a_0p9>; + vdd-l2-l10-supply =3D <&vph_pwr>; + vdd-l3-l4-l5-l18-supply =3D <&vreg_s5a_2p0>; + vdd-l6-l9-supply =3D <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply =3D <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name =3D "vreg_s2a_0p5"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name =3D "vreg_s3a_1p05"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name =3D "vreg_s4a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name =3D "vreg_s5a_2p0"; + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name =3D "vreg_s6a_0p9"; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name =3D "vreg_s7a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name =3D "vreg_s8a_1p3"; + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name =3D "vreg_l1a_0p91"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name =3D "vreg_l2a_2p3"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name =3D "vreg_l3a_1p2"; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name =3D "vreg_l5a_0p8"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name =3D "vreg_l6a_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name =3D "vreg_l7a_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name =3D "vreg_l8a_0p91"; + regulator-min-microvolt =3D <888000>; + regulator-max-microvolt =3D <925000>; + regulator-initial-mode =3D ; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name =3D "vreg_l8a_0p91"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name =3D "vreg_l10a_2p95"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name =3D "vreg_l11a_0p91"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name =3D "vreg_l12a_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name =3D "vreg_l14a_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name =3D "vreg_l15a_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name =3D "vreg_l16a_1p8"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name =3D "vreg_l17a_3p3"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name =3D "vreg_l18a_1p2"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + }; }; =20 &qupv3_id_0 { --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA13C433F5 for ; Sat, 1 Oct 2022 03:10:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233088AbiJADKi (ORCPT ); Fri, 30 Sep 2022 23:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232580AbiJADHr (ORCPT ); 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charset="utf-8" Add interconnect nodes for the QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 8c2af08b8329..b85ffd8baf4b 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include =20 / { @@ -453,5 +454,31 @@ apps_smmu: apps-smmu@15000000 { , ; }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1{ + compatible =3D "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1640000 { + reg =3D <0x0 0x1640000 0x0 0x45080>; + compatible =3D "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + reg =3D <0x0 0x19100000 0x0 0xB8080>; + compatible =3D "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; }; }; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 877DFC433FE for ; Sat, 1 Oct 2022 03:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233046AbiJADLh (ORCPT ); Fri, 30 Sep 2022 23:11:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbiJADHs (ORCPT ); Fri, 30 Sep 2022 23:07:48 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5095163B43; 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charset="utf-8" Add rpmhpd node and opps for QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 51 ++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index b85ffd8baf4b..c5acdc447074 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include =20 / { @@ -386,6 +387,56 @@ rpmhcc: clock-controller { clock-names =3D "xo"; clocks =3D <&xo_board>; }; + + rpmhpd: power-controller { + compatible =3D "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; }; =20 arch_timer: timer { --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE59CC433FE for ; Sat, 1 Oct 2022 03:11:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232954AbiJADLW (ORCPT ); Fri, 30 Sep 2022 23:11:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232685AbiJADHu (ORCPT ); Fri, 30 Sep 2022 23:07:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76710163B73; 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charset="utf-8" Add the spmi bus for the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index c5acdc447074..62a6a6e8ca59 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -252,6 +252,24 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc500000 0x0 0x400000>, + <0x0 0xc440000 0x0 0x80000>, + <0x0 0xc4c0000 0x0 0x10000>, + <0x0 0xc42d000 0x0 0x4000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + tlmm: pinctrl@f000000 { compatible =3D "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; 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charset="utf-8" Include the pmic file for the QDU1000 IDP platform. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts= /qcom/qdu1000-idp.dts index 654b50220c2e..847ed8cc7be0 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -7,6 +7,7 @@ =20 #include #include "qdu1000.dtsi" +#include "pm8150.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. 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Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts= /qcom/qru1000-idp.dts index 8d27923dc470..c32211e3963d 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -7,6 +7,7 @@ =20 #include #include "qru1000.dtsi" +#include "pm8150.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. QRU1000 IDP"; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74D0BC433FE for ; Sat, 1 Oct 2022 03:11:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233147AbiJADLo (ORCPT ); Fri, 30 Sep 2022 23:11:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232597AbiJADHs (ORCPT ); Fri, 30 Sep 2022 23:07:48 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69B74DD346; Fri, 30 Sep 2022 20:07:19 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912gWPJ024311; Sat, 1 Oct 2022 03:07:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=alFR7iOVLCnTvfLTSQt8bXQiwXcQpDECjWx0pLV0QXo=; b=oRDWHwIVdoV5JjsMPUCe+cObOgtWmQcIoJEJBp2UVuECH8OfrCvV5f7U3gdK8rpwNtG3 idigY2FAalEvVZ3bFOY9qSJ8rp3PcpJ0KJk+iQ9flKc71F7caN8PnZbiYtIAR6+N4Zkg cx5fo5LceswIS2RAgn8iqXz+Dw/eaGu45EEJHPavSN5q8w/tfMqI+UrrSXw7ldTUW6yg PtviTfdIOw8aNmA8s70VN5RHoDFtgqGYTVtxLhOuu8yLGk7PKvREGNIevReIPaqO2Jj5 cEfGz2eFstLvDARfcuitS0D9spvCh0CHtBmc8PNt395hBlxPKRKcqIqauzrXsnr9WR3V jQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jwwfck4cx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:07:17 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29137G5b031984 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:07:16 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:16 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support Date: Fri, 30 Sep 2022 20:06:51 -0700 Message-ID: <20221001030656.29365-15-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GsNt-ce9_3dmcfSGOP-A6OU03_h9VBk5 X-Proofpoint-ORIG-GUID: GsNt-ce9_3dmcfSGOP-A6OU03_h9VBk5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=820 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add cpufreq-epss node for the QDU1000 and QRU1000 SoCs and add references to it from the cpu nodes. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 62a6a6e8ca59..2fd449df3706 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -45,6 +45,7 @@ CPU0: cpu@0 { enable-method =3D "psci"; power-domain-names =3D "psci"; power-domains =3D <&CPU_PD0>; + qcom,freq-domains =3D <&cpufreq_hw 0>; next-level-cache =3D <&L2_0>; L2_0: l2-cache { compatible =3D "cache"; @@ -62,6 +63,7 @@ CPU1: cpu@100 { enable-method =3D "psci"; power-domains =3D <&CPU_PD1>; power-domain-names =3D "psci"; + qcom,freq-domains =3D <&cpufreq_hw 0>; next-level-cache =3D <&L2_100>; L2_100: l2-cache { compatible =3D "cache"; @@ -77,6 +79,7 @@ CPU2: cpu@200 { enable-method =3D "psci"; power-domains =3D <&CPU_PD2>; power-domain-names =3D "psci"; + qcom,freq-domains =3D <&cpufreq_hw 0>; next-level-cache =3D <&L2_200>; L2_200: l2-cache { compatible =3D "cache"; @@ -91,6 +94,7 @@ CPU3: cpu@300 { enable-method =3D "psci"; power-domains =3D <&CPU_PD3>; power-domain-names =3D "psci"; + qcom,freq-domains =3D <&cpufreq_hw 0>; next-level-cache =3D <&L2_300>; L2_300: l2-cache { compatible =3D "cache"; @@ -246,6 +250,18 @@ uart7: serial@99c000 { }; }; =20 + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-eps= s", + "qcom,cpufreq-epss"; + reg =3D <0x0 0x17d91000 0x0 0x1000>; + reg-names =3D "freq-domain0"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + interrupts =3D ; + interrupt-names =3D "dcvsh0_int"; + #freq-domain-cells =3D <1>; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x1f40000 0x0 0x20000>; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28290C433FE for ; Sat, 1 Oct 2022 03:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233152AbiJADLv (ORCPT ); Fri, 30 Sep 2022 23:11:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232592AbiJADHs (ORCPT ); Fri, 30 Sep 2022 23:07:48 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8975163B44; Fri, 30 Sep 2022 20:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664593638; x=1696129638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WN4Tl3wluvZ9Vte2Ue7sbfq3vm2YAEU9SdtRXds6Zrw=; b=R4Q2tDsUC1JV3BYNr27mFdIfTJNZlH+omjUq2kVJzxrwI3vVLkUYS4xm frzfl1YmeUKmYGReJFC/IzF3/14u+UADjKqbz9bUx5ZLdrafCaTe+0r// OePKOxLj+XMobAqRl6cg4ofHNKV3zgnA5j/XrGMx5w0xE9N9G0nUKCx5F 8=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Sep 2022 20:07:18 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:07:18 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:16 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes Date: Fri, 30 Sep 2022 20:06:52 -0700 Message-ID: <20221001030656.29365-16-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add additional QUP nodes and update previous nodes with approrpiate interconnects and iommus. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 2fd449df3706..5d3932ad67a1 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -231,6 +231,15 @@ qupv3_id_0: geniqup@9c0000 { clock-names =3D "m-ahb", "s-ahb"; clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus =3D <&apps_smmu 0xe3 0x0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names =3D "qup-core"; + qcom,iommu-dma-addr-pool =3D <0x40000000 0x10000000>; + qcom,iommu-geometry =3D <0x40000000 0x10000000>; + qcom,iommu-dma =3D "fastmap"; + dma-coherent; + #address-cells =3D <2>; #size-cells =3D <2>; ranges; @@ -250,6 +259,21 @@ uart7: serial@99c000 { }; }; =20 + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0xac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus =3D <&apps_smmu 0x103 0x0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clock-names =3D "m-ahb", "s-ahb"; + + ranges; + status =3D "disabled"; + }; + + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-eps= s", "qcom,cpufreq-epss"; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9007C433FE for ; Sat, 1 Oct 2022 03:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233162AbiJADMB (ORCPT ); Fri, 30 Sep 2022 23:12:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232693AbiJADHv (ORCPT ); Fri, 30 Sep 2022 23:07:51 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD49F3120B; Fri, 30 Sep 2022 20:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664593642; x=1696129642; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HfqxfIIh0PJaRBXnhpEKQJDvwicLwQxNHHW2gL59Xko=; b=YLq/isvVo5dy87yTuDhYukSdvQcDRcmCgXAk9MOWKy71S0LUI87P7QDe rW/xg8d/50la8h5qhHPSGwnLXfBvxWFi1XIeGigByccB0xqCFR13wEG2l u/am2A7L1ZAm+9KncjchFBzxPzHoFp5PZC41XdddDzeOkxp72V7HRtsIj 0=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Sep 2022 20:07:18 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:07:18 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:16 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes Date: Fri, 30 Sep 2022 20:06:53 -0700 Message-ID: <20221001030656.29365-17-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPI DMA is used tof DMA operations for QUP devices, so add the two gpi_dma instances on the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 5d3932ad67a1..c105bc15995b 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -225,6 +226,50 @@ gcc: clock-controller@80000 { clock-names =3D "bi_tcxo", "sleep_clk"; }; =20 + gpi_dma0: dma-controller@900000 { + compatible =3D "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; + #dma-cells =3D <5>; + reg =3D <0x0 0x900000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <12>; + dma-channel-mask =3D <0x3f>; + iommus =3D <&apps_smmu 0xf6 0x0>; + status =3D "ok"; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; + #dma-cells =3D <5>; + reg =3D <0x0 0xa00000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <12>; + dma-channel-mask =3D <0x3f>; + iommus =3D <&apps_smmu 0x116 0x0>; + status =3D "ok"; + }; + qupv3_id_0: geniqup@9c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x9c0000 0x0 0x2000>; --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB213C433FE for ; Sat, 1 Oct 2022 03:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233169AbiJADMG (ORCPT ); Fri, 30 Sep 2022 23:12:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232696AbiJADHw (ORCPT ); Fri, 30 Sep 2022 23:07:52 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1CAA34734; Fri, 30 Sep 2022 20:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664593642; x=1696129642; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LOScalpbL+4y0Lpsx+kZowKCfEy9BlxhV7SRAQvzu2c=; b=KUiY+is3l1kKslJAbwbct9QW47dwlz/sr84tllp+eGh/f91QXPnDJj/9 W2IGLeXHvF4jNVmZiy3GFlnyl4yc5WcfmZmS5aLJUrAfzLCGBnDPuPZQl B0WVRaG0hDU6NPnO0xoOyB6fjZ5c74HMIKoeoeLdIaVzTXwT3y8gl+AOb 0=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Sep 2022 20:07:18 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:07:18 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:17 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Date: Fri, 30 Sep 2022 20:06:54 -0700 Message-ID: <20221001030656.29365-18-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add I2C nodes to the QUP along with pinconf for these nodes. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 365 +++++++++++++++++++++++++ 1 file changed, 365 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index c105bc15995b..40d7cc4c1f3d 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -302,6 +302,132 @@ uart7: serial@99c000 { #size-cells =3D <0>; status =3D "disabled"; }; + + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x984000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c1_data_clk>; + dmas =3D <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x988000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c2_data_clk>; + dmas =3D <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c3_data_clk>; + dmas =3D <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x990000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c4_data_clk>; + dmas =3D <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x994000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c5_data_clk>; + dmas =3D <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@998000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x998000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c6_data_clk>; + dmas =3D <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; }; =20 qupv3_id_1: geniqup@ac0000 { @@ -316,6 +442,153 @@ qupv3_id_1: geniqup@ac0000 { =20 ranges; status =3D "disabled"; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c9_data_clk>; + dmas =3D <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c10_data_clk>; + dmas =3D <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,i2c-geni"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c11_data_clk>; + dmas =3D <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa90000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interrupts =3D ; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c12_data_clk>; + dmas =3D <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c13: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c13_data_clk>; + dmas =3D <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c14: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa98000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c14_data_clk>; + dmas =3D <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa9c000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c15_data_clk>; + dmas =3D <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; }; =20 =20 @@ -381,6 +654,98 @@ rx { bias-disable; }; }; + + qup_i2c1_data_clk: qup-i2c1-data-clk { + pins =3D "gpio10", "gpio11"; + function =3D "qup0_se1_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk { + pins =3D "gpio12", "gpio13"; + function =3D "qup0_se2_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk { + pins =3D "gpio14", "gpio15"; + function =3D "qup0_se3_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk { + pins =3D "gpio16", "gpio17"; + function =3D "qup0_se4_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk { + pins =3D "gpio130", "gpio131"; + function =3D "qup0_se5_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk { + pins =3D "gpio132", "gpio133"; + function =3D "qup0_se6_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk { + pins =3D "gpio22", "gpio23"; + function =3D "qup1_se1_l0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk { + pins =3D "gpio24", "gpio25"; + function =3D "qup1_se2_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk { + pins =3D "gpio26", "gpio27"; + function =3D "qup1_se3_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk { + pins =3D "gpio28", "gpio29"; + function =3D "qup1_se4_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins =3D "gpio30", "gpio31"; + function =3D "qup1_se5_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins =3D "gpio34", "gpio35"; + function =3D "qup1_se6_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk { + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se7_l0"; + drive-strength =3D <2>; + bias-pulll-up; + }; + }; =20 pdc: interrupt-controller@b220000 { --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32173C433F5 for ; Sat, 1 Oct 2022 03:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233180AbiJADML (ORCPT ); Fri, 30 Sep 2022 23:12:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232705AbiJADHw (ORCPT ); Fri, 30 Sep 2022 23:07:52 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BD4CE006F; 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Fri, 30 Sep 2022 20:07:17 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes Date: Fri, 30 Sep 2022 20:06:55 -0700 Message-ID: <20221001030656.29365-19-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add SPI devices to the QUP nodes for the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 441 +++++++++++++++++++++++++ 1 file changed, 441 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 40d7cc4c1f3d..930bb8c8ba5b 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -428,6 +428,132 @@ i2c6: i2c@998000 { #size-cells =3D <0>; status =3D "disabled"; }; + + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x984000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + dmas =3D <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x988000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + dmas =3D <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + dmas =3D <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x990000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + dmas =3D <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x994000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + dmas =3D <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x998000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + dmas =3D <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; }; =20 qupv3_id_1: geniqup@ac0000 { @@ -589,6 +715,153 @@ i2c15: i2c@a9c000 { #size-cells =3D <0>; status =3D "disabled"; }; + + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + dmas =3D <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + dmas =3D <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + dmas =3D <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa90000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; + dmas =3D <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; + dmas =3D <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa98000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + dmas =3D <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa9c000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + interconnects =3D + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + dmas =3D <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; }; =20 =20 @@ -746,6 +1019,174 @@ qup_i2c15_data_clk: qup-i2c15-data-clk { bias-pulll-up; }; =20 + qup_spi1_data_clk: qup-spi1-data-clk { + pins =3D "gpio10", "gpio11", "gpio12"; + function =3D "qup0_se1_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs { + pins =3D "gpio13"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { + pins =3D "gpio12", "gpio13", "gpio10"; + function =3D "qup0_se2_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs { + pins =3D "gpio11"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { + pins =3D "gpio14", "gpio15", "gpio16"; + function =3D "qup0_se3_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs { + pins =3D "gpio17"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { + pins =3D "gpio16", "gpio17", "gpio14"; + function =3D "qup0_se4_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs { + pins =3D "gpio15"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { + pins =3D "gpio130", "gpio131", "gpio132"; + function =3D "qup0_se5_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs { + pins =3D "gpio133"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { + pins =3D "gpio132", "gpio133", "gpio130"; + function =3D "qup0_se6_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs { + pins =3D "gpio131"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { + pins =3D "gpio22", "gpio23", "gpio24"; + function =3D "qup1_se1_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs { + pins =3D "gpio25"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { + pins =3D "gpio24", "gpio25", "gpio22"; + function =3D "qup1_se2_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs { + pins =3D "gpio23"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { + pins =3D "gpio26", "gpio27", "gpio28"; + function =3D "qup1_se3_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs { + pins =3D "gpio29"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { + pins =3D "gpio28", "gpio29", "gpio26"; + function =3D "qup1_se4_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs { + pins =3D "gpio27"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { + pins =3D "gpio30", "gpio31", "gpio32"; + function =3D "qup1_se5_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs { + pins =3D "gpio33"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { + pins =3D "gpio34", "gpio35", "gpio36"; + function =3D "qup1_se6_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs { + pins =3D "gpio37", "gpio38"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { + pins =3D "gpio40", "gpio41", "gpio30"; + function =3D "qup1_se7_l0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs { + pins =3D "gpio31"; + drive-strength =3D <6>; + bias-disable; + }; }; =20 pdc: interrupt-controller@b220000 { --=20 2.37.3 From nobody Sun Feb 8 17:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 841CDC433F5 for ; Sat, 1 Oct 2022 03:12:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233058AbiJADMQ (ORCPT ); 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30 Sep 2022 20:07:18 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:07:18 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:17 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances Date: Fri, 30 Sep 2022 20:06:56 -0700 Message-ID: <20221001030656.29365-20-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add remaining UART instances to the QUP nodes for the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 +++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/q= com/qdru1000.dtsi index 930bb8c8ba5b..21938e3a613e 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -290,6 +290,19 @@ qupv3_id_0: geniqup@9c0000 { ranges; status =3D "disabled"; =20 + uart0: serial@980000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x980000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart0_default>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + uart7: serial@99c000 { compatible =3D "qcom,geni-debug-uart"; reg =3D <0x0 0x99c000 0x0 0x4000>; @@ -569,6 +582,33 @@ qupv3_id_1: geniqup@ac0000 { ranges; status =3D "disabled"; =20 + uart8: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart8_default>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart13: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart13_default>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0xa84000 0x0 0x4000>; @@ -912,7 +952,12 @@ tlmm: pinctrl@f000000 { gpio-ranges =3D <&tlmm 0 0 151>; wakeup-parent =3D <&pdc>; =20 - qup_uart7_default: qup-uart7-default { + qup_uart0_default: qup-uart0-default { + pins =3D "gpio6", "gpio7", "gpio8", "gpio9"; + function =3D "qup0_se0_l0"; + }; + + qup_uart7_default: qup-uart3-default { tx { pins =3D "gpio134"; function =3D "qup0_se7_l2"; @@ -928,6 +973,16 @@ rx { }; }; =20 + qup_uart8_default: qup-uart8-default { + pins =3D "gpio18", "gpio19", "gpio20", "gpio21"; + function =3D "qup1_se0_l0"; + }; + + qup_uart13_default: qup-uart13-default { + pins =3D "gpio30", "gpio31", "gpio32", "gpio33"; + function =3D "qup1_se5_l0"; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk { pins =3D "gpio10", "gpio11"; function =3D "qup0_se1_l0"; --=20 2.37.3