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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id bq13-20020a5d5a0d000000b002365921c9aesm13332818wrb.77.2022.11.02.08.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 08:18:13 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 02 Nov 2022 16:18:08 +0100 Subject: [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v6-2-be4fe8da254b@baylibre.com> References: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> In-Reply-To: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> To: Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Rob Herring , Robin Murphy , Will Deacon , Yong Wu Cc: linux-kernel@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, Amjad Ouled-Ameur , Markus Schneider-Pargmann , linux-arm-kernel@lists.infradead.org, Fabien Parent , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2748; i=amergnat@baylibre.com; h=from:subject:message-id; bh=12NL2NIpCRtKtHudS7M2vbMHWUQeZ96+QJE5QCrHjlQ=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjYooyslmq6zZt3zk7YPwEA4DTWaC6O3ikzGVN+bRB b1hhTYKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2KKMgAKCRArRkmdfjHURROMD/ 4kETHOn8ZygXYS5ED3s+0Z7ynhPWo4sQxfCbaMUfm3/IGXPeENWKxwHswgWmMBaGBTmgsGkabZChFS r+sf3hFkHm4q924vR2L1jp0A4qohhZIC5XZG3tOhi8leNLmgyY3QHoif9dlsnMz9GKpz7P0NU0FhhC BN1pscvvk5tu/YUHUAaDJIiAU6rGx7AlIih3KhCdhTNMi1lPsMHKCOJ4YBpzIyv77mbynPTdbAISo0 HVDwxSxe8I+Tl5/FXZMJ7UivJlcNYRwHcQjqUIdCuy1DPgQYpxil+lNKdGGltl3iZXD44s0TTJrv0V 22+G/nLQ8S3p6psdJxOEyzwivXF7t/EUimjbox0xqdZRTDLKAutMLhNoAjuH+6ulC0e/6FHw8GweNO UyuYkquVDKxwanLxCfd+7FdrRVJHM/NfBcIXV2T1hFVT8jTjW+QEH6IQ0bPceRkfMkqYYZcDKi4xlH v/w4zzmSAgcIYCAJxwW52b1kOY86TOn9cq0vjhb4EDDzNDNOFIDEosW+C44WcQqJQkW7jt67rASnqW 64ud2CzK9ZbjbEutURBcdXhCsk7ngii4jWyx9FKxTDGekzxBJeJXihZ2oiycaPyEEi6KjkKpnrfjmB mt0fgO1W9KPQbhBmEdhbCuh6jkZW+LzYV3jvsT91gJDGCcF/ZlUHTBOrqN4g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to add extra macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order to support 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu Signed-off-by: Alexandre Mergnat --- drivers/iommu/mtk_iommu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..563e3c54a0e2 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,12 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) +/* Macro for 5 bits length port ID field (default) */ #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +/* Macro for 6 bits length port ID field */ +#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) +#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) =20 #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -139,6 +143,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) +#define INT_ID_PORT_WIDTH_6 BIT(19) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -441,14 +446,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) fault_pa |=3D (u64)pa34_32 << 32; =20 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port =3D F_MMU_INT_ID_PORT_ID(regval); if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { + fault_port =3D F_MMU_INT_ID_PORT_ID_WID_6(regval); + fault_larb =3D F_MMU_INT_ID_LARB_ID_WID_6(regval); } else { + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); } fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; --=20 b4 0.10.1