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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id bq13-20020a5d5a0d000000b002365921c9aesm13332818wrb.77.2022.11.02.08.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 08:18:12 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 02 Nov 2022 16:18:07 +0100 Subject: [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v6-1-be4fe8da254b@baylibre.com> References: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> In-Reply-To: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> To: Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Rob Herring , Robin Murphy , Will Deacon , Yong Wu Cc: linux-kernel@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, Amjad Ouled-Ameur , Markus Schneider-Pargmann , linux-arm-kernel@lists.infradead.org, Fabien Parent , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6368; i=amergnat@baylibre.com; h=from:subject:message-id; bh=5/uPU5oCsnBuU7Z/wg3JNmSvklPo8fkTK5NWaHQiobk=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjYooyBuYKC7CMc3q48r1T+qWWNhdb6+Q47Hp59WyC M8Lv8EuJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2KKMgAKCRArRkmdfjHURd7RD/ 4gnKP6mMK1wgnySZx6fAyfIpjbtOMuAnLyYCjtXGMQjnvrgEVoneED6a1x0aAVud8ATbRdpX/dwnq3 wl9hJG5LUUGebUGkqs4agVaDr1yJ8T4rjk4ffmlrj94Qk/LTvEEu/k/IoBdUrfsQyUl1cyGm91KugU Tg99PYFBrmKRSjWtV7xO008WdrW4+/UxZDvVDlxdevfxJud0pFozMOuC0FwNSoh40rxQO8AyAq9+jf obGeOVVT6mi0e2SYF+6bBcR650Cq4+EIf1/2kPqNLvmWhaJN4n1rRtmWXIu3m5fnN5dk410sRS7ShB yH3i3k6FdSjqZpSAJuGX6ePrbz3amlFpkUKKfiKEZ2IilkqedJO41XClFjce601yfmdyqFVGGFmHou AbjjuPfMon707u+4Z+V2sfN2HdktUXA1LvD5W3PWc7AFwvtNWqHIUAIUN5JH4dfrlZaNOHMnPb1ODm 8TkWKRXBtNbwZzARYXYDEEjopW4/w+arsthWErF6PiMEANf5miX5D2ZfCmAaZ8S3vfONyuHSy4iMdQ l/SmqCild6fzzMTDjKpm1sAeOnuoE7Bnkw161ap7RJWW62730BNESCtNM3CeZTo/myOMnivefmqVUy h+scmSBxihUEtdJzWry8D/6rRdXt7zLHHBKpMW2zrsbUSlVmJaY7NVKI2S1A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add IOMMU binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: Yong Wu Signed-off-by: Alexandre Mergnat Reviewed-by: Matthias Brugger --- .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 + .../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++= ++++ 2 files changed, 92 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/= Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index fee0241b5098..725434d9d646 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -81,6 +81,7 @@ properties: - mediatek,mt8195-iommu-vdo # generation two - mediatek,mt8195-iommu-vpp # generation two - mediatek,mt8195-iommu-infra # generation two + - mediatek,mt8365-m4u # generation two =20 - description: mt7623 generation one items: @@ -130,6 +131,7 @@ properties: dt-binding/memory/mt8186-memory-port.h for mt8186, dt-binding/memory/mt8192-larb-port.h for mt8192. dt-binding/memory/mt8195-memory-port.h for mt8195. + dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365. =20 power-domains: maxItems: 1 diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/inclu= de/dt-bindings/memory/mediatek,mt8365-larb-port.h new file mode 100644 index 000000000000..56d5a5dd519e --- /dev/null +++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ + +#include + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) + +/* larb1 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16) +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17) +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18) +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19) +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20) +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21) +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22) +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23) + +/* larb3 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10) + +#endif --=20 b4 0.10.1 From nobody Sat Sep 21 09:24:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id bq13-20020a5d5a0d000000b002365921c9aesm13332818wrb.77.2022.11.02.08.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 08:18:13 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 02 Nov 2022 16:18:08 +0100 Subject: [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v6-2-be4fe8da254b@baylibre.com> References: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> In-Reply-To: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> To: Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Rob Herring , Robin Murphy , Will Deacon , Yong Wu Cc: linux-kernel@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, Amjad Ouled-Ameur , Markus Schneider-Pargmann , linux-arm-kernel@lists.infradead.org, Fabien Parent , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2748; i=amergnat@baylibre.com; h=from:subject:message-id; bh=12NL2NIpCRtKtHudS7M2vbMHWUQeZ96+QJE5QCrHjlQ=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjYooyslmq6zZt3zk7YPwEA4DTWaC6O3ikzGVN+bRB b1hhTYKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2KKMgAKCRArRkmdfjHURROMD/ 4kETHOn8ZygXYS5ED3s+0Z7ynhPWo4sQxfCbaMUfm3/IGXPeENWKxwHswgWmMBaGBTmgsGkabZChFS r+sf3hFkHm4q924vR2L1jp0A4qohhZIC5XZG3tOhi8leNLmgyY3QHoif9dlsnMz9GKpz7P0NU0FhhC BN1pscvvk5tu/YUHUAaDJIiAU6rGx7AlIih3KhCdhTNMi1lPsMHKCOJ4YBpzIyv77mbynPTdbAISo0 HVDwxSxe8I+Tl5/FXZMJ7UivJlcNYRwHcQjqUIdCuy1DPgQYpxil+lNKdGGltl3iZXD44s0TTJrv0V 22+G/nLQ8S3p6psdJxOEyzwivXF7t/EUimjbox0xqdZRTDLKAutMLhNoAjuH+6ulC0e/6FHw8GweNO UyuYkquVDKxwanLxCfd+7FdrRVJHM/NfBcIXV2T1hFVT8jTjW+QEH6IQ0bPceRkfMkqYYZcDKi4xlH v/w4zzmSAgcIYCAJxwW52b1kOY86TOn9cq0vjhb4EDDzNDNOFIDEosW+C44WcQqJQkW7jt67rASnqW 64ud2CzK9ZbjbEutURBcdXhCsk7ngii4jWyx9FKxTDGekzxBJeJXihZ2oiycaPyEEi6KjkKpnrfjmB mt0fgO1W9KPQbhBmEdhbCuh6jkZW+LzYV3jvsT91gJDGCcF/ZlUHTBOrqN4g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to add extra macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order to support 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu Signed-off-by: Alexandre Mergnat Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..563e3c54a0e2 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,12 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) +/* Macro for 5 bits length port ID field (default) */ #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +/* Macro for 6 bits length port ID field */ +#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) +#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) =20 #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -139,6 +143,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) +#define INT_ID_PORT_WIDTH_6 BIT(19) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -441,14 +446,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) fault_pa |=3D (u64)pa34_32 << 32; =20 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port =3D F_MMU_INT_ID_PORT_ID(regval); if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { + fault_port =3D F_MMU_INT_ID_PORT_ID_WID_6(regval); + fault_larb =3D F_MMU_INT_ID_LARB_ID_WID_6(regval); } else { + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); } fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; --=20 b4 0.10.1 From nobody Sat Sep 21 09:24:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D270C43217 for ; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id bq13-20020a5d5a0d000000b002365921c9aesm13332818wrb.77.2022.11.02.08.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 08:18:14 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 02 Nov 2022 16:18:09 +0100 Subject: [PATCH v6 3/3] iommu/mediatek: add support for MT8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v6-3-be4fe8da254b@baylibre.com> References: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> In-Reply-To: <20221001-iommu-support-v6-0-be4fe8da254b@baylibre.com> To: Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Rob Herring , Robin Murphy , Will Deacon , Yong Wu Cc: linux-kernel@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, Amjad Ouled-Ameur , Markus Schneider-Pargmann , linux-arm-kernel@lists.infradead.org, Fabien Parent , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2006; i=amergnat@baylibre.com; h=from:subject:message-id; bh=Q4NYYQifFh9zAugrVsdD24zlf7qYZx8w4pW2A66Dgc4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjYooyAnt/3uDKzQTl89xfXRYOhl4D1bU+Q7od77hw ErFRlkKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2KKMgAKCRArRkmdfjHURUUFD/ 93Y7hT8/4BU2SdrJ0KdhJzQYPpku8B/wTpGm45+uiAJV6r77tTcgbr7cZSyBAy+xZY+qRMrPGUBVqU Ajk7HHfEUF/WzcXIHzB6KHGSf9c+3D+rNDm6yBs9CXUg0xfe0jkc81bUSf/+aC6XtdBECiWrNn70Xv z5QtntaQBOINOB63LBBI96uXqH0grV99uYxelModQWaNKjnnyBzEdHxp8ey/RqZ0oQfTDV7oFTgjA7 otXN+ux0mGGPdZ8oBe/GvEX7L5kok0LuiJZcKejE4YliRSfIv38O7OauoXtk1LSHQs91f/ddL+dRQ/ D/6p8qf/2vv/21M10jkcf8Vk4zfQDIEnzYEFFVeBl9/nvHmPrT2oszCCkzDs0hPP+zvuvmkZIgY4CI OmxgXt/hKzfsvct9x2WMTlzCxfeeVIxdCJA2d085AYXb6LA6Y71MFI4I9mcLrMqxo1v4+vhdbJPpOQ nY62Wdcvc1qqNbkJy+SJeKRq5wGQNEItSFfJ6+zZgY8aXAKh/1KIkUZhzpAHk7yY9THS1T/eoTjH/z 5M0Trb/g65/NJvhAz1Qyl8HK/QEaIFN/SNGss5FWTgsbx0b8C8HXFFpcQFm9qXM2DGFncyqqxx1QCp 5n+o0IQHkJLe15tSnQyvryaHLrSaEv3uepvuEH7vMOAwwx+nTTeoRryGDb0g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add IOMMU support for MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: Amjad Ouled-Ameur Tested-by: Amjad Ouled-Ameur Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu Signed-off-by: Alexandre Mergnat Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 563e3c54a0e2..aff7a9190749 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -170,6 +170,7 @@ enum mtk_iommu_plat { M4U_MT8186, M4U_MT8192, M4U_MT8195, + M4U_MT8365, }; =20 struct mtk_iommu_iova_region { @@ -1525,6 +1526,17 @@ static const struct mtk_iommu_plat_data mt8195_data_= vpp =3D { {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, }; =20 +static const struct mtk_iommu_plat_data mt8365_data =3D { + .m4u_plat =3D M4U_MT8365, + .flags =3D RESET_AXI | INT_ID_PORT_WIDTH_6, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, + .banks_num =3D 1, + .banks_enable =3D {true}, + .iova_region =3D single_domain, + .iova_region_nr =3D ARRAY_SIZE(single_domain), + .larbid_remap =3D {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ +}; + static const struct of_device_id mtk_iommu_of_ids[] =3D { { .compatible =3D "mediatek,mt2712-m4u", .data =3D &mt2712_data}, { .compatible =3D "mediatek,mt6779-m4u", .data =3D &mt6779_data}, @@ -1537,6 +1549,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, { .compatible =3D "mediatek,mt8195-iommu-vpp", .data =3D &mt8195_data_v= pp}, + { .compatible =3D "mediatek,mt8365-m4u", .data =3D &mt8365_data}, {} }; =20 --=20 b4 0.10.1