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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id h5-20020adfe985000000b002322bff5b3bsm22966355wrm.54.2022.10.21.06.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:42:21 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 21 Oct 2022 15:42:17 +0200 Subject: [PATCH v5 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v5-2-92cdbb83bbb8@baylibre.com> References: <20221001-iommu-support-v5-0-92cdbb83bbb8@baylibre.com> In-Reply-To: <20221001-iommu-support-v5-0-92cdbb83bbb8@baylibre.com> To: Robin Murphy , Joerg Roedel , Yong Wu , Krzysztof Kozlowski , Will Deacon , Rob Herring , Matthias Brugger Cc: Alexandre Mergnat , linux-kernel@vger.kernel.org, Amjad Ouled-Ameur , devicetree@vger.kernel.org, Fabien Parent , linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann , linux-mediatek@lists.infradead.org, iommu@lists.linux.dev, AngeloGioacchino Del Regno , Krzysztof Kozlowski X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2703; i=amergnat@baylibre.com; h=from:subject:message-id; bh=MoEet6B6VXSSp8bcExDnQBc+mSaQhOo/W6ZW7xDSJ1M=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjUqG7pUZ+phrWMxCNEdvxMKQ0eD2JmCEsamlEU4kP 73CMikiJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY1KhuwAKCRArRkmdfjHURXeBEA CApVh33ghEZK+kDfwj5T840sxHThUAsf3eiBpjL4lK8Pmj3DRZTsduYCWyf2JudtZrSX8b7x4piVc+ 0M/3Epe+pSIWd4j4NGxOTTR+lDJ0OD1UtLzA7/wZac3UTaZmN1RHsJPyf9/ML3tAHbnuP/UmJZ5ft9 9y5KXs0k4/kOAOrnLFz3Ry28vxpxwZXhyjPcr/N89KWiuRJPC+F711PABdvWYncrwi9Rkash/qncwE Mq357kSgh0dTZwL7UvAR8O3LsnGlfcSRkrdBvRVIILaIRkUXxHEUZe87qZdUcOITqCb7tQZKO2MoFT +WbBIcwCvdjwbFxde8cZvDUaRsq0zpW5Ji3poARdQ0qHR06HE6uoTSs6HmitqpVaM/G8hxwLqfaYdu F2VZUhCW5sbI10kp1u+3a9lLQPS9JHCtGRIZJJWWbIy6as7RavrbvC170Vy8v3AFd7EEAK/Lo/IB1Q +IDj71IczmLVv1F9Js1tgrM/AyRFyJjqssnZPmKanYUjTOzVbAoqP9tchUzT+zHAN15abowFvkgUdj hFQXuhF7tcB7ZUVobsFM3idBwtkTPsPzHhQDJk3HjJU67qGEPSY04rqRE98w09GAQtvTnLU8QtAWIB LTU1cZZj0cH7nG3AfqLW4xtMzypnrVmd4vOk38DrxdgK9PZMRUVnkD89klJA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to add extra macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order to support 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/iommu/mtk_iommu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..563e3c54a0e2 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,12 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) +/* Macro for 5 bits length port ID field (default) */ #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +/* Macro for 6 bits length port ID field */ +#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) +#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) =20 #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -139,6 +143,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) +#define INT_ID_PORT_WIDTH_6 BIT(19) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -441,14 +446,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) fault_pa |=3D (u64)pa34_32 << 32; =20 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port =3D F_MMU_INT_ID_PORT_ID(regval); if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { + fault_port =3D F_MMU_INT_ID_PORT_ID_WID_6(regval); + fault_larb =3D F_MMU_INT_ID_LARB_ID_WID_6(regval); } else { + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); } fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; --=20 b4 0.10.1