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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a1c2606000000b003c452678025sm6684633wmm.4.2022.10.14.01.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 01:45:33 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 14 Oct 2022 10:45:29 +0200 Subject: [PATCH v4 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v4-1-f1e13438dfd2@baylibre.com> References: <20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com> In-Reply-To: <20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com> To: Rob Herring , Yong Wu , Krzysztof Kozlowski , Matthias Brugger , Robin Murphy , Joerg Roedel , Will Deacon Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann , Amjad Ouled-Ameur , Fabien Parent , devicetree@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6314; i=amergnat@baylibre.com; h=from:subject:message-id; bh=veY/apXDPl5JMIMezq7x83zfGltq7KQ6mfnT4iv01CU=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjSSGrhq0TEcFEc1lz1vsbXk564BtZHQWu+3GtCWRm JjPq7u2JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY0khqwAKCRArRkmdfjHURQxID/ 9KEI/aU1lXOcwXiIqR3Ee+66WlY3ezvJxXIOqeeQ8H1pXPY8RKgjMmh0Hd4S6WkpE+vjAWIhcy9Wv+ +8jnay2wcSZsaP0xfCiaEFMGtIoq/+d7PAwxQaouojcdkI8at/Uc1prm5B2rM++K8v23CvajfPqpPe t7o/7jydpAuquxMYTuib9+F2M2SFTsNGbfWSwf1bReMy6pJEZ2L6qjZzAUnbWHEuPiEOPJUWBupigF k1xWAaR6YnJ+VGBQcMS9kETqA3RJtyZN1WfNEtgzTUaMIiKOIafbp3IRhm5o8CfrsQLTvIFxwZYBu8 WQ3TLCxeVs7BYh04ySB7NWtld+c7pk+UL6l5+xFuh2lKq9ZVgfD5b3L0zNe3PwaN8Ev7mqQ9VhLlj0 j+so5bgeMEUwXDUbDtVaLHvSkQpmpmbtmUOsQamya/3S1D4W8DmFmatlvprRBHGtTFJjHBjkulw/Fj D+HFb0mSuxUVU7+fIJt4dWkKtbKuVovCRFaIBuNTvIkgppKPy3WuLWaHJg1iUfHpo+rwCpGILrFEGY w/f+0RKQBl3l4fHcthNKtpYFTJGeco1Apu2EGOUsoApiTAUpKnSGKsoXqar4ezzxkrRjipF9IfV9zO PkpB5wGQZnLMTPFlLHr3TIG19MTbR20Xth8HKAMAt5TityhYGOK/nnPNMqdA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add IOMMU binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Mergnat Reviewed-by: Yong Wu --- .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 + .../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++= ++++ 2 files changed, 92 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/= Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index fee0241b5098..4b8cf3ce6963 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -81,6 +81,7 @@ properties: - mediatek,mt8195-iommu-vdo # generation two - mediatek,mt8195-iommu-vpp # generation two - mediatek,mt8195-iommu-infra # generation two + - mediatek,mt8365-m4u # generation two =20 - description: mt7623 generation one items: @@ -130,6 +131,7 @@ properties: dt-binding/memory/mt8186-memory-port.h for mt8186, dt-binding/memory/mt8192-larb-port.h for mt8192. dt-binding/memory/mt8195-memory-port.h for mt8195. + dt-binding/memory/mt8365-larb-port.h for mt8365. =20 power-domains: maxItems: 1 diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/inclu= de/dt-bindings/memory/mediatek,mt8365-larb-port.h new file mode 100644 index 000000000000..56d5a5dd519e --- /dev/null +++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ + +#include + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) + +/* larb1 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16) +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17) +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18) +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19) +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20) +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21) +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22) +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23) + +/* larb3 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10) + +#endif --=20 b4 0.10.1 From nobody Sat Sep 21 11:46:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a1c2606000000b003c452678025sm6684633wmm.4.2022.10.14.01.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 01:45:34 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 14 Oct 2022 10:45:30 +0200 Subject: [PATCH v4 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v4-2-f1e13438dfd2@baylibre.com> References: <20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com> In-Reply-To: <20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com> To: Rob Herring , Yong Wu , Krzysztof Kozlowski , Matthias Brugger , Robin Murphy , Joerg Roedel , Will Deacon Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann , Amjad Ouled-Ameur , Fabien Parent , devicetree@vger.kernel.org, Alexandre Mergnat , iommu@lists.linux.dev, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2777; i=amergnat@baylibre.com; h=from:subject:message-id; bh=yHI2W23j32Eio+qvj5sArGXxqz+yEaFNsPuEi2F1ESI=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjSSGr72jkaVUfd01lHWlH70E3IlRnthih2tTn4S8f oPgszB2JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY0khqwAKCRArRkmdfjHURZcfD/ 4twP9fhese84RdEddlF784ECS6fOnHpJuYrStpE0X919HpgvHrCs1hKdO/vMDvxXxpNuvmoxwQzRRd /DHc7ulpPRkZB9Qj7f3N2O6Cf3OEHLUF7j2+XMbhEJ+tCr2Qr5nby1EXGdam8gM0efQQRBCFx0b/wY Pa3usFg0YPDrhhd3MfEYBq3U/C7WgOKtfxIB89WB7asYOzXEJY4PzmT3hUEYn+8X8OzR4k0Te66CG8 Yi+j/vZepY4WkPWcL3ZYmu1DIbf6yUhitPo9gsuTeOFN9OpBOhzWrDJDQPL++LUZutFu9ZWK3HWjfc vtQKNzPPe8tRoMtgFF8s3bcgkuU4xepPuF6o628AsSbq6ffS3CgZ34T40kbsRGXaG3OA3sRIMAHEiz JhSY0qz22z45OrDrHnjeq1pfrD8KPqW/Sh1ELyWTd18ZlaHdTblGBP/uEvTdQED673ZJiS1YV/JWzI amTnWPPAIPyjY69yPGVthl0XAgtHtvQ0fJKUdo8mCQiwFtkqtCmZHRXUE5BJbvI8aWaZnJNjjSJ8kp 7lGNUDntkhM1QGbZV+7eOV+K4pts5qbShv2iJfnEqUYYY0M3v8CxZV+Kgtz6cWp2wlh+G0CS5FtiMr KhyD1CZsisr9qmOML0uw8LqV4djKDRTsdLnWFYLQXcvKc/yRuZ5aumwLPw0g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to add extra macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order to support 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..50195a900611 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,12 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) +/* Macro for 5 bits length port ID field (default) */ #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +/* Macro for 6 bits length port ID field */ +#define F_MMU_INT_ID_LARB_ID_EXT(a) (((a) >> 8) & 0x7) +#define F_MMU_INT_ID_PORT_ID_EXT(a) (((a) >> 2) & 0x3f) =20 #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -139,6 +143,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) +#define HAS_INT_ID_PORT_WIDTH_6 BIT(19) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -441,7 +446,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_pa |=3D (u64)pa34_32 << 32; =20 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { + fault_port =3D F_MMU_INT_ID_PORT_ID_EXT(regval); + } else { + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + } if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); @@ -449,7 +458,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); } else { - fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); + if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { + fault_larb =3D F_MMU_INT_ID_LARB_ID_EXT(regval); + } else { + fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); + } } fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; } --=20 b4 0.10.1 From nobody Sat Sep 21 11:46:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42692C4332F for ; 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Signed-off-by: Fabien Parent Reviewed-by: Amjad Ouled-Ameur Tested-by: Amjad Ouled-Ameur Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 50195a900611..051ed5234538 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -170,6 +170,7 @@ enum mtk_iommu_plat { M4U_MT8186, M4U_MT8192, M4U_MT8195, + M4U_MT8365, }; =20 struct mtk_iommu_iova_region { @@ -1528,6 +1529,17 @@ static const struct mtk_iommu_plat_data mt8195_data_= vpp =3D { {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, }; =20 +static const struct mtk_iommu_plat_data mt8365_data =3D { + .m4u_plat =3D M4U_MT8365, + .flags =3D RESET_AXI | HAS_INT_ID_PORT_WIDTH_6, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, + .banks_num =3D 1, + .banks_enable =3D {true}, + .iova_region =3D single_domain, + .iova_region_nr =3D ARRAY_SIZE(single_domain), + .larbid_remap =3D {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ +}; + static const struct of_device_id mtk_iommu_of_ids[] =3D { { .compatible =3D "mediatek,mt2712-m4u", .data =3D &mt2712_data}, { .compatible =3D "mediatek,mt6779-m4u", .data =3D &mt6779_data}, @@ -1540,6 +1552,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, { .compatible =3D "mediatek,mt8195-iommu-vpp", .data =3D &mt8195_data_v= pp}, + { .compatible =3D "mediatek,mt8365-m4u", .data =3D &mt8365_data}, {} }; =20 --=20 b4 0.10.1