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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id v24-20020a1cf718000000b003a6125562e1sm9767020wmh.46.2022.10.10.05.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 05:54:17 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 10 Oct 2022 14:54:08 +0200 Subject: [PATCH v3 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221001-iommu-support-v3-2-c7b3059b0d16@baylibre.com> References: <20221001-iommu-support-v3-0-c7b3059b0d16@baylibre.com> In-Reply-To: <20221001-iommu-support-v3-0-c7b3059b0d16@baylibre.com> To: Matthias Brugger , Joerg Roedel , Robin Murphy , Rob Herring , Will Deacon , Yong Wu , Krzysztof Kozlowski Cc: iommu@lists.linux.dev, AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Fabien Parent , Alexandre Mergnat , Markus Schneider-Pargmann , Amjad Ouled-Ameur , linux-mediatek@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2694; i=amergnat@baylibre.com; h=from:subject:message-id; bh=BCe+/ykFa/fn5SOJye+/BgPzDIeybFkkbiXBZtITeNI=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjRBX2NMVamMxV4iKNdLs5Ytoj7x609EByzseEUlTr DCfCrwmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY0QV9gAKCRArRkmdfjHURXkqD/ 4kl4rMFWfYv99V/bLZVANdkEu77lQ589T720XVn8pm3TCt7R3wPnDPW1pQ5PFpUNw8QrFVzCl0FLTH rob/5QlnOXrSsP7UbptiAySmzifaGslwWa1nkumPRIWRn3yVfV+Lufs3rb7RoWdQuKX5VcN1rmg2kV uAeh4NkOxuUmjSiNJ6ZRBrVMye2vwFCk/3zQpB+vd/dVDKkaANhDrO7ZscT3xO+Mgy4Wjsuu85mHQk KETF3RFnwN51wwb90GaA8S4sfnT4tuG3RxGP+BFHaWCq80lpKo0EcxZXYbf9sNVUYUpNUThwqsGpOV KwGy0YIJ3rOSTQ31GyYYix6QuhUhqE/+K9jQjwSJJ5k4U5mpa+XEOinGJR/7G5CahDb5G6i2mxVXSW OrqyacrT2yjFKLO2s9HsO1sUUy5kbMIpQcUwlyIqMaxOBkK9QoLVQ2Q+DxtVP20ZyDeF6+NrmdHZB/ VK3EoniLFX22BqXAtrWrr+rGA2gfkCf0lfyce7LyP1u31swSk/lXzxxbrmDnK9ODBczX+4U2Ng5Eb+ n60sRNliqSmm/o3DBKXHSt2BU4IZyq5cizoPK29RPGjUuC/rJx7YD/n2QmwBIPs6j2QauZr+9b0sB5 5v4E94mRCBs8r8PgKsoyur1k6BK6w+wdwVfj5OIl/DZbyFRUbhEfvLzlvVnw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to add extra macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order to support 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..35e9731c3441 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,12 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) +/* Macro for 5 bits lenght port ID field (default) */ #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +/* Macro for 6 bits lenght port ID field */ +#define F_MMU_INT_ID_LARB_ID_EXT(a) (((a) >> 8) & 0x7) +#define F_MMU_INT_ID_PORT_ID_EXT(a) (((a) >> 2) & 0x3f) =20 #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -139,6 +143,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) +#define HAS_INT_ID_PORT_WIDTH_6 BIT(19) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -441,7 +446,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_pa |=3D (u64)pa34_32 << 32; =20 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { + fault_port =3D F_MMU_INT_ID_PORT_ID_EXT(regval); + } else { + fault_port =3D F_MMU_INT_ID_PORT_ID(regval); + } if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); @@ -449,7 +458,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); } else { - fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); + if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { + fault_larb =3D F_MMU_INT_ID_LARB_ID_EXT(regval); + } else { + fault_larb =3D F_MMU_INT_ID_LARB_ID(regval); + } } fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; } --=20 b4 0.10.1