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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id d10-20020ac2544a000000b00492f45cbbfcsm398876lfn.302.2022.09.30.13.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 13:05:42 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 22:05:28 +0200 Message-Id: <20220930200529.331223-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930200529.331223-1-krzysztof.kozlowski@linaro.org> References: <20220930200529.331223-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. The sdm854.dtsi file defined several pin configuration nodes which are customized by the boards. Therefore keep a additional "default-pins" node inside so the boards can add more of configuration nodes. Such additional configuration nodes always need 'function' property now (required by DT schema). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 344 +++++++----------- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 76 ++-- .../arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 60 ++- arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 60 ++- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 88 ++--- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 138 +++---- .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 6 +- .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 26 +- .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 30 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 305 +++++++--------- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 33 +- .../boot/dts/qcom/sdm850-samsung-w737.dts | 96 ++--- 13 files changed, 513 insertions(+), 751 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index b5f11fbcc300..3403cdcdd49c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -993,21 +993,21 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ =20 &qspi_cs0 { - pinconf { + default-pins { pins =3D "gpio90"; bias-disable; }; }; =20 &qspi_clk { - pinconf { + default-pins { pins =3D "gpio95"; bias-disable; }; }; =20 &qspi_data01 { - pinconf { + default-pins { pins =3D "gpio91", "gpio92"; =20 /* High-Z when no transfers; nice to park the lines */ @@ -1016,7 +1016,7 @@ pinconf { }; =20 &qup_i2c3_default { - pinconf { + default-pins { pins =3D "gpio41", "gpio42"; drive-strength =3D <2>; =20 @@ -1026,7 +1026,7 @@ pinconf { }; =20 &qup_i2c11_default { - pinconf { + default-pins { pins =3D "gpio31", "gpio32"; drive-strength =3D <2>; =20 @@ -1036,7 +1036,7 @@ pinconf { }; =20 &qup_i2c12_default { - pinconf { + default-pins { pins =3D "gpio49", "gpio50"; drive-strength =3D <2>; =20 @@ -1046,7 +1046,7 @@ pinconf { }; =20 &qup_i2c14_default { - pinconf { + default-pins { pins =3D "gpio33", "gpio34"; drive-strength =3D <2>; =20 @@ -1056,7 +1056,7 @@ pinconf { }; =20 &qup_spi0_default { - pinconf { + default-pins { pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength =3D <2>; bias-disable; @@ -1064,7 +1064,7 @@ pinconf { }; =20 &qup_spi5_default { - pinconf { + default-pins { pins =3D "gpio85", "gpio86", "gpio87", "gpio88"; drive-strength =3D <2>; bias-disable; @@ -1072,7 +1072,7 @@ pinconf { }; =20 &qup_spi10_default { - pinconf { + default-pins { pins =3D "gpio53", "gpio54", "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -1081,28 +1081,25 @@ pinconf { =20 &qup_uart6_default { /* Change pinmux to all 4 pins since CTS and RTS are connected */ - pinmux { - pins =3D "gpio45", "gpio46", - "gpio47", "gpio48"; - }; - - pinconf-cts { + cts-pins { /* * Configure a pull-down on 45 (CTS) to match the pull of * the Bluetooth module. */ pins =3D "gpio45"; + function =3D "qup6"; bias-pull-down; }; =20 - pinconf-rts-tx { + rts-tx-pins { /* We'll drive 46 (RTS) and 47 (TX), so no pull */ pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - pinconf-rx { + rx-pins { /* * Configure a pull-up on 48 (RX). This is needed to avoid * garbage data when the TX pin of the Bluetooth module is @@ -1110,19 +1107,22 @@ pinconf-rx { * signal yet). */ pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; =20 &qup_uart9_default { - pinconf-tx { + tx-pins { pins =3D "gpio4"; + function =3D "qup9"; drive-strength =3D <2>; bias-disable; }; =20 - pinconf-rx { + rx-pins { pins =3D "gpio5"; + function =3D "qup9"; drive-strength =3D <2>; bias-pull-up; }; @@ -1213,243 +1213,153 @@ ap-suspend-l-hog { output-low; }; =20 - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins =3D "gpio37"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio37"; - drive-strength =3D <2>; - bias-disable; - }; + ap_edp_bklten: ap-edp-bklten-state { + pins =3D "gpio37"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - bios_flash_wp_r_l: bios-flash-wp-r-l { - pinmux { - pins =3D "gpio128"; - function =3D "gpio"; - input-enable; - }; - - pinconf { - pins =3D "gpio128"; - bias-disable; - }; + bios_flash_wp_r_l: bios-flash-wp-r-l-state { + pins =3D "gpio128"; + function =3D "gpio"; + input-enable; + bias-disable; }; =20 - ec_ap_int_l: ec-ap-int-l { - pinmux { - pins =3D "gpio122"; - function =3D "gpio"; - input-enable; - }; - - pinconf { - pins =3D "gpio122"; - bias-pull-up; - }; + ec_ap_int_l: ec-ap-int-l-state { + pins =3D "gpio122"; + function =3D "gpio"; + input-enable; + bias-pull-up; }; =20 - edp_brij_en: edp-brij-en { - pinmux { - pins =3D "gpio102"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio102"; - drive-strength =3D <2>; - bias-disable; - }; + edp_brij_en: edp-brij-en-state { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - edp_brij_irq: edp-brij-irq { - pinmux { - pins =3D "gpio10"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio10"; - drive-strength =3D <2>; - bias-pull-down; - }; + edp_brij_irq: edp-brij-irq-state { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; }; =20 - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins =3D "gpio43"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio43"; - drive-strength =3D <2>; - bias-disable; - }; + en_pp3300_dx_edp: en-pp3300-dx-edp-state { + pins =3D "gpio43"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins =3D "gpio129"; - function =3D "gpio"; - input-enable; - }; - - pinconf { - pins =3D "gpio129"; - bias-pull-up; - }; + h1_ap_int_odl: h1-ap-int-odl-state { + pins =3D "gpio129"; + function =3D "gpio"; + input-enable; + bias-pull-up; }; =20 - pen_eject_odl: pen-eject-odl { - pinmux { - pins =3D "gpio119"; - function =3D "gpio"; - bias-pull-up; - }; + pen_eject_odl: pen-eject-odl-state { + pins =3D "gpio119"; + function =3D "gpio"; + bias-pull-up; }; =20 - pen_irq_l: pen-irq-l { - pinmux { - pins =3D "gpio24"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio24"; + pen_irq_l: pen-irq-l-state { + pins =3D "gpio24"; + function =3D "gpio"; =20 - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; =20 - pen_pdct_l: pen-pdct-l { - pinmux { - pins =3D "gpio63"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio63"; + pen_pdct_l: pen-pdct-l-state { + pins =3D "gpio63"; + function =3D "gpio"; =20 - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; =20 - pen_rst_l: pen-rst-l { - pinmux { - pins =3D "gpio23"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio23"; - bias-disable; - drive-strength =3D <2>; + pen_rst_l: pen-rst-l-state { + pins =3D "gpio23"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; =20 - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; =20 - sdc2_clk: sdc2-clk { - pinconf { - pins =3D "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins =3D "sdc2_clk"; + bias-disable; =20 - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength =3D <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16. + */ + drive-strength =3D <16>; }; =20 - sdc2_cmd: sdc2-cmd { - pinconf { - pins =3D "sdc2_cmd"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sdc2_data: sdc2-data { - pinconf { - pins =3D "sdc2_data"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_data: sdc2-data-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sd_cd_odl: sd-cd-odl { - pinmux { - pins =3D "gpio44"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio44"; - bias-pull-up; - }; + sd_cd_odl: sd-cd-odl-state { + pins =3D "gpio44"; + function =3D "gpio"; + bias-pull-up; }; =20 - ts_int_l: ts-int-l { - pinmux { - pins =3D "gpio125"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio125"; - bias-pull-up; - }; + ts_int_l: ts-int-l-state { + pins =3D "gpio125"; + function =3D "gpio"; + bias-pull-up; }; =20 - ts_reset_l: ts-reset-l { - pinmux { - pins =3D "gpio118"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio118"; - bias-disable; - drive-strength =3D <2>; - }; + ts_reset_l: ts-reset-l-state { + pins =3D "gpio118"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; }; =20 - ap_suspend_l_assert: ap_suspend_l_assert { - config { - pins =3D "gpio126"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - output-low; - }; + ap_suspend_l_assert: ap-suspend-l-assert-state { + pins =3D "gpio126"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + output-low; }; =20 - ap_suspend_l_deassert: ap_suspend_l_deassert { - config { - pins =3D "gpio126"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - output-high; - }; + ap_suspend_l_deassert: ap-suspend-l-deassert-state { + pins =3D "gpio126"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + output-high; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/d= ts/qcom/sdm845-db845c.dts index a157eab66dee..c5e17a718049 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -820,8 +820,8 @@ &spi2 { }; =20 &tlmm { - cam0_default: cam0_default { - rst { + cam0_default: cam0-default-state { + rst-pins { pins =3D "gpio9"; function =3D "gpio"; =20 @@ -829,7 +829,7 @@ rst { bias-disable; }; =20 - mclk0 { + mclk0-pins { pins =3D "gpio13"; function =3D "cam_mclk"; =20 @@ -838,8 +838,8 @@ mclk0 { }; }; =20 - cam3_default: cam3_default { - rst { + cam3_default: cam3-default-state { + rst-pins { function =3D "gpio"; pins =3D "gpio21"; =20 @@ -847,7 +847,7 @@ rst { bias-disable; }; =20 - mclk3 { + mclk3-pins { function =3D "cam_mclk"; pins =3D "gpio16"; =20 @@ -856,7 +856,7 @@ mclk3 { }; }; =20 - dsi_sw_sel: dsi-sw-sel { + dsi_sw_sel: dsi-sw-sel-state { pins =3D "gpio120"; function =3D "gpio"; =20 @@ -865,20 +865,20 @@ dsi_sw_sel: dsi-sw-sel { output-high; }; =20 - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins =3D "gpio84"; function =3D "gpio"; bias-disable; }; =20 - pcie0_default_state: pcie0-default { - clkreq { + pcie0_default_state: pcie0-default-state { + clkreq-pins { pins =3D "gpio36"; function =3D "pci_e0"; bias-pull-up; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio35"; function =3D "gpio"; =20 @@ -887,7 +887,7 @@ reset-n { bias-pull-down; }; =20 - wake-n { + wake-n-pins { pins =3D "gpio37"; function =3D "gpio"; =20 @@ -896,7 +896,7 @@ wake-n { }; }; =20 - pcie0_pwren_state: pcie0-pwren { + pcie0_pwren_state: pcie0-pwren-state { pins =3D "gpio90"; function =3D "gpio"; =20 @@ -904,8 +904,8 @@ pcie0_pwren_state: pcie0-pwren { bias-disable; }; =20 - pcie1_default_state: pcie1-default { - perst-n { + pcie1_default_state: pcie1-default-state { + perst-n-pins { pins =3D "gpio102"; function =3D "gpio"; =20 @@ -913,13 +913,13 @@ perst-n { bias-disable; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio103"; function =3D "pci_e1"; bias-pull-up; }; =20 - wake-n { + wake-n-pins { pins =3D "gpio11"; function =3D "gpio"; =20 @@ -927,7 +927,7 @@ wake-n { bias-pull-up; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio75"; function =3D "gpio"; =20 @@ -937,8 +937,8 @@ reset-n { }; }; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; bias-disable; =20 @@ -949,26 +949,26 @@ clk { drive-strength =3D <16>; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - data { + data-pins { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio126"; function =3D "gpio"; bias-pull-up; }; =20 - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins =3D <54>; function =3D "gpio"; =20 @@ -1123,20 +1123,20 @@ &wifi { =20 /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi2_default { - pinmux { + default-pins { drive-strength =3D <16>; }; }; =20 &qup_uart3_default{ - pinmux { + default-pins { pins =3D "gpio41", "gpio42", "gpio43", "gpio44"; function =3D "qup3"; }; }; =20 &qup_i2c10_default { - pinconf { + default-pins { pins =3D "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -1144,37 +1144,37 @@ pinconf { }; =20 &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-disable; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; =20 &qup_uart9_default { - pinconf-tx { + tx-pins { pins =3D "gpio4"; + function =3D "qup9"; drive-strength =3D <2>; bias-disable; }; =20 - pinconf-rx { + rx-pins { pins =3D "gpio5"; + function =3D "qup9"; drive-strength =3D <2>; bias-pull-up; }; @@ -1285,7 +1285,7 @@ ov7251_ep: endpoint { =20 /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi0_default { - config { + default-pins { drive-strength =3D <6>; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/bo= ot/dts/qcom/sdm845-lg-common.dtsi index 1eb423e4be24..3ccfbdb2880e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -558,48 +558,36 @@ &usb_1_qmpphy { &tlmm { gpio-reserved-ranges =3D <28 4>, <81 4>; =20 - sdc2_clk: sdc2-clk { - pinconf { - pins =3D "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - * - * TODO: copy-pasted from mtp, try other values - * on these devices. - */ - drive-strength =3D <16>; - }; + sdc2_clk: sdc2-clk-state { + pins =3D "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + * + * TODO: copy-pasted from mtp, try other values + * on these devices. + */ + drive-strength =3D <16>; }; =20 - sdc2_cmd: sdc2-cmd { - pinconf { - pins =3D "sdc2_cmd"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sdc2_data: sdc2-data { - pinconf { - pins =3D "sdc2_data"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_data: sdc2-data-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sd_card_det_n: sd-card-det-n { - pinmux { - pins =3D "gpio126"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins =3D "gpio126"; + function =3D "gpio"; + bias-pull-up; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boo= t/dts/qcom/sdm845-lg-judyln.dts index 7d967a104b3e..a12723310c8b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -58,7 +58,7 @@ &mss_pil { }; =20 &tlmm { - thinq_key_default: thinq-key-default { + thinq_key_default: thinq-key-default-state { pins =3D "gpio89"; function =3D "gpio"; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/= qcom/sdm845-mtp.dts index de2d10e0315a..b36befe60b08 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -719,7 +719,7 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ =20 &qup_i2c10_default { - pinconf { + default-pins { pins =3D "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -727,14 +727,16 @@ pinconf { }; =20 &qup_uart9_default { - pinconf-tx { + tx-pins { pins =3D "gpio4"; + function =3D "qup9"; drive-strength =3D <2>; bias-disable; }; =20 - pinconf-rx { + rx-pins { pins =3D "gpio5"; + function =3D "qup9"; drive-strength =3D <2>; bias-pull-up; }; @@ -743,44 +745,32 @@ pinconf-rx { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - sdc2_clk: sdc2-clk { - pinconf { - pins =3D "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins =3D "sdc2_clk"; + bias-disable; =20 - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength =3D <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength =3D <16>; }; =20 - sdc2_cmd: sdc2-cmd { - pinconf { - pins =3D "sdc2_cmd"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sdc2_data: sdc2-data { - pinconf { - pins =3D "sdc2_data"; - bias-pull-up; - drive-strength =3D <16>; - }; + sdc2_data: sdc2-data-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <16>; }; =20 - sd_card_det_n: sd-card-det-n { - pinmux { - pins =3D "gpio126"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins =3D "gpio126"; + function =3D "gpio"; + bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm= 64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 392461c29e76..02a1e056f465 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -470,7 +470,7 @@ &qupv3_id_0 { }; =20 &qup_i2c12_default { - mux { + default-pins { pins =3D "gpio49", "gpio50"; function =3D "qup12"; drive-strength =3D <2>; @@ -479,7 +479,7 @@ mux { }; =20 &qup_i2c10_default { - pinconf { + default-pins { pins =3D "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -487,14 +487,16 @@ pinconf { }; =20 &qup_uart9_default { - pinconf-tx { + tx-pins { pins =3D "gpio4"; + function =3D "qup9"; drive-strength =3D <2>; bias-disable; }; =20 - pinconf-rx { + rx-pins { pins =3D "gpio5"; + function =3D "qup9"; drive-strength =3D <2>; bias-pull-up; }; @@ -504,24 +506,22 @@ pinconf-rx { * Prevent garbage data on bluetooth UART lines */ &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-pull-down; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; @@ -607,51 +607,41 @@ &usb_1_hsphy { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - tri_state_key_default: tri_state_key_default { - mux { - pins =3D "gpio40", "gpio42", "gpio26"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; + tri_state_key_default: tri-state-key-default-state { + pins =3D "gpio40", "gpio42", "gpio26"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - ts_default_pins: ts-int { - mux { - pins =3D "gpio99", "gpio125"; - function =3D "gpio"; - drive-strength =3D <16>; - bias-pull-up; - }; + ts_default_pins: ts-int-state { + pins =3D "gpio99", "gpio125"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; }; =20 - panel_reset_pins: panel-reset { - mux { - pins =3D "gpio6", "gpio25", "gpio26"; - function =3D "gpio"; - drive-strength =3D <8>; - bias-disable; - }; + panel_reset_pins: panel-reset-state { + pins =3D "gpio6", "gpio25", "gpio26"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; }; =20 - panel_te_pin: panel-te { - mux { - pins =3D "gpio10"; - function =3D "mdp_vsync"; - drive-strength =3D <2>; - bias-disable; - input-enable; - }; + panel_te_pin: panel-te-state { + pins =3D "gpio10"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-disable; + input-enable; }; =20 - panel_esd_pin: panel-esd { - mux { - pins =3D "gpio30"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-down; - input-enable; - }; + panel_esd_pin: panel-esd-state { + pins =3D "gpio30"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64= /boot/dts/qcom/sdm845-shift-axolotl.dts index 83261c9bb4f2..7c752f621a23 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -559,14 +559,16 @@ led@5 { }; =20 &qup_uart9_default { - pinconf-rx { + rx-pins { pins =3D "gpio5"; + function =3D "qup9"; drive-strength =3D <2>; bias-pull-up; }; =20 - pinconf-tx { + tx-pins { pins =3D "gpio4"; + function =3D "qup9"; drive-strength =3D <2>; bias-disable; }; @@ -583,110 +585,62 @@ &qupv3_id_1 { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - sde_dsi_active: sde-dsi-active { - mux { - pins =3D "gpio6", "gpio11"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio6", "gpio11"; - drive-strength =3D <8>; - bias-disable; - }; + sde_dsi_active: sde-dsi-active-state { + pins =3D "gpio6", "gpio11"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; }; =20 - sde_dsi_suspend: sde-dsi-suspend { - mux { - pins =3D "gpio6", "gpio11"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio6", "gpio11"; - drive-strength =3D <2>; - bias-pull-down; - }; + sde_dsi_suspend: sde-dsi-suspend-state { + pins =3D "gpio6", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; }; =20 - sde_te_active: sde-te-active { - mux { - pins =3D "gpio10"; - function =3D "mdp_vsync"; - }; - - config { - pins =3D "gpio10"; - drive-strength =3D <2>; - bias-pull-down; - }; + sde_te_active: sde-te-active-state { + pins =3D "gpio10"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; }; =20 - sde_te_suspend: sde-te-suspend { - mux { - pins =3D "gpio10"; - function =3D "mdp_vsync"; - }; - - config { - pins =3D "gpio10"; - drive-strength =3D <2>; - bias-pull-down; - }; + sde_te_suspend: sde-te-suspend-state { + pins =3D "gpio10"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; }; =20 - ts_int_active: ts-int-active { - mux { - pins =3D "gpio125"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio125"; - drive-strength =3D <8>; - bias-pull-up; - input-enable; - }; + ts_int_active: ts-int-active-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + input-enable; }; =20 - ts_int_suspend: ts-int-suspend { - mux { - pins =3D "gpio125"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio125"; - drive-strength =3D <2>; - bias-pull-down; - input-enable; - }; + ts_int_suspend: ts-int-suspend-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; }; =20 - ts_reset_active: ts-reset-active { - mux { - pins =3D "gpio99"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio99"; - drive-strength =3D <8>; - bias-pull-up; - }; + ts_reset_active: ts-reset-active-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; }; =20 - ts_reset_suspend: ts-reset-suspend { - mux { - pins =3D "gpio99"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio99"; - drive-strength =3D <2>; - bias-pull-down; - }; + ts_reset_suspend: ts-reset-suspend-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/a= rm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 51ee42e3c995..3a920275dda3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -383,19 +383,19 @@ &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 sdc2_default_state: sdc2-default-state { - clk { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <10>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc2_data"; drive-strength =3D <10>; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/ar= m64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 0f470cf1ed1c..d6392f3486ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -442,33 +442,33 @@ codec { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; bias-disable; drive-strength =3D <16>; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - data { + data-pins { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio126"; function =3D "gpio"; bias-pull-up; }; =20 - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins =3D <54>; function =3D "gpio"; =20 @@ -571,24 +571,22 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ =20 &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-disable; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm6= 4/boot/dts/qcom/sdm845-xiaomi-polaris.dts index f98259489679..9a4e1ff1d3ba 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -573,7 +573,7 @@ &qupv3_id_1 { }; =20 &qup_i2c14_default { - pinconf { + default-pins { pins =3D "gpio33", "gpio34"; drive-strength =3D <2>; bias-disable; @@ -583,14 +583,14 @@ pinconf { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - ts_reset_default: ts-reset-default { + ts_reset_default: ts-reset-default-state { pins =3D "gpio99"; function =3D "gpio"; drive-strength =3D <16>; output-high; }; =20 - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins =3D "gpio125"; function =3D "gpio"; bias-pull-down; @@ -598,14 +598,14 @@ ts_int_default: ts-int-default { input-enable; }; =20 - ts_reset_sleep: ts-reset-sleep { + ts_reset_sleep: ts-reset-sleep-state { pins =3D "gpio99"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - ts_int_sleep: ts-int-sleep { + ts_int_sleep: ts-int-sleep-state { pins =3D "gpio125"; function =3D "gpio"; bias-pull-down; @@ -613,21 +613,21 @@ ts_int_sleep: ts-int-sleep { input-enable; }; =20 - sde_dsi_active: sde-dsi-active { + sde_dsi_active: sde-dsi-active-state { pins =3D "gpio6", "gpio10"; function =3D "gpio"; drive-strength =3D <8>; bias-disable; }; =20 - sde_dsi_suspend: sde-dsi-suspend { + sde_dsi_suspend: sde-dsi-suspend-state { pins =3D "gpio6", "gpio10"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - wcd_intr_default: wcd-intr-default { + wcd_intr_default: wcd-intr-default-state { pins =3D "gpio54"; function =3D "gpio"; input-enable; @@ -739,24 +739,22 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ =20 &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-disable; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index d761da47220d..915ef8dda023 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2641,7 +2641,7 @@ tlmm: pinctrl@3400000 { gpio-ranges =3D <&tlmm 0 0 151>; wakeup-parent =3D <&pdc_intc>; =20 - cci0_default: cci0-default { + cci0_default: cci0-default-state { /* SDA, SCL */ pins =3D "gpio17", "gpio18"; function =3D "cci_i2c"; @@ -2650,7 +2650,7 @@ cci0_default: cci0-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci0_sleep: cci0-sleep { + cci0_sleep: cci0-sleep-state { /* SDA, SCL */ pins =3D "gpio17", "gpio18"; function =3D "cci_i2c"; @@ -2659,7 +2659,7 @@ cci0_sleep: cci0-sleep { bias-pull-down; }; =20 - cci1_default: cci1-default { + cci1_default: cci1-default-state { /* SDA, SCL */ pins =3D "gpio19", "gpio20"; function =3D "cci_i2c"; @@ -2668,7 +2668,7 @@ cci1_default: cci1-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci1_sleep: cci1-sleep { + cci1_sleep: cci1-sleep-state { /* SDA, SCL */ pins =3D "gpio19", "gpio20"; function =3D "cci_i2c"; @@ -2677,531 +2677,486 @@ cci1_sleep: cci1-sleep { bias-pull-down; }; =20 - qspi_clk: qspi-clk { - pinmux { + qspi_clk: qspi-clk-state { + default-pins { pins =3D "gpio95"; function =3D "qspi_clk"; }; }; =20 - qspi_cs0: qspi-cs0 { - pinmux { + qspi_cs0: qspi-cs0-state { + default-pins { pins =3D "gpio90"; function =3D "qspi_cs"; }; }; =20 - qspi_cs1: qspi-cs1 { - pinmux { + qspi_cs1: qspi-cs1-state { + default-pins { pins =3D "gpio89"; function =3D "qspi_cs"; }; }; =20 - qspi_data01: qspi-data01 { - pinmux-data { + qspi_data01: qspi-data01-state { + default-pins { pins =3D "gpio91", "gpio92"; function =3D "qspi_data"; }; }; =20 - qspi_data12: qspi-data12 { - pinmux-data { + qspi_data12: qspi-data12-state { + default-pins { pins =3D "gpio93", "gpio94"; function =3D "qspi_data"; }; }; =20 - qup_i2c0_default: qup-i2c0-default { - pinmux { + qup_i2c0_default: qup-i2c0-default-state { + default-pins { pins =3D "gpio0", "gpio1"; function =3D "qup0"; }; }; =20 - qup_i2c1_default: qup-i2c1-default { - pinmux { + qup_i2c1_default: qup-i2c1-default-state { + default-pins { pins =3D "gpio17", "gpio18"; function =3D "qup1"; }; }; =20 - qup_i2c2_default: qup-i2c2-default { - pinmux { + qup_i2c2_default: qup-i2c2-default-state { + default-pins { pins =3D "gpio27", "gpio28"; function =3D "qup2"; }; }; =20 - qup_i2c3_default: qup-i2c3-default { - pinmux { + qup_i2c3_default: qup-i2c3-default-state { + default-pins { pins =3D "gpio41", "gpio42"; function =3D "qup3"; }; }; =20 - qup_i2c4_default: qup-i2c4-default { - pinmux { + qup_i2c4_default: qup-i2c4-default-state { + default-pins { pins =3D "gpio89", "gpio90"; function =3D "qup4"; }; }; =20 - qup_i2c5_default: qup-i2c5-default { - pinmux { + qup_i2c5_default: qup-i2c5-default-state { + default-pins { pins =3D "gpio85", "gpio86"; function =3D "qup5"; }; }; =20 - qup_i2c6_default: qup-i2c6-default { - pinmux { + qup_i2c6_default: qup-i2c6-default-state { + default-pins { pins =3D "gpio45", "gpio46"; function =3D "qup6"; }; }; =20 - qup_i2c7_default: qup-i2c7-default { - pinmux { + qup_i2c7_default: qup-i2c7-default-state { + default-pins { pins =3D "gpio93", "gpio94"; function =3D "qup7"; }; }; =20 - qup_i2c8_default: qup-i2c8-default { - pinmux { + qup_i2c8_default: qup-i2c8-default-state { + default-pins { pins =3D "gpio65", "gpio66"; function =3D "qup8"; }; }; =20 - qup_i2c9_default: qup-i2c9-default { - pinmux { + qup_i2c9_default: qup-i2c9-default-state { + default-pins { pins =3D "gpio6", "gpio7"; function =3D "qup9"; }; }; =20 - qup_i2c10_default: qup-i2c10-default { - pinmux { + qup_i2c10_default: qup-i2c10-default-state { + default-pins { pins =3D "gpio55", "gpio56"; function =3D "qup10"; }; }; =20 - qup_i2c11_default: qup-i2c11-default { - pinmux { + qup_i2c11_default: qup-i2c11-default-state { + default-pins { pins =3D "gpio31", "gpio32"; function =3D "qup11"; }; }; =20 - qup_i2c12_default: qup-i2c12-default { - pinmux { + qup_i2c12_default: qup-i2c12-default-state { + default-pins { pins =3D "gpio49", "gpio50"; function =3D "qup12"; }; }; =20 - qup_i2c13_default: qup-i2c13-default { - pinmux { + qup_i2c13_default: qup-i2c13-default-state { + default-pins { pins =3D "gpio105", "gpio106"; function =3D "qup13"; }; }; =20 - qup_i2c14_default: qup-i2c14-default { - pinmux { + qup_i2c14_default: qup-i2c14-default-state { + default-pins { pins =3D "gpio33", "gpio34"; function =3D "qup14"; }; }; =20 - qup_i2c15_default: qup-i2c15-default { - pinmux { + qup_i2c15_default: qup-i2c15-default-state { + default-pins { pins =3D "gpio81", "gpio82"; function =3D "qup15"; }; }; =20 - qup_spi0_default: qup-spi0-default { - pinmux { + qup_spi0_default: qup-spi0-default-state { + default-pins { pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; function =3D "qup0"; - }; - - config { - pins =3D "gpio0", "gpio1", - "gpio2", "gpio3"; drive-strength =3D <6>; bias-disable; }; }; =20 - qup_spi1_default: qup-spi1-default { - pinmux { + qup_spi1_default: qup-spi1-default-state { + default-pins { pins =3D "gpio17", "gpio18", "gpio19", "gpio20"; function =3D "qup1"; }; }; =20 - qup_spi2_default: qup-spi2-default { - pinmux { + qup_spi2_default: qup-spi2-default-state { + default-pins { pins =3D "gpio27", "gpio28", "gpio29", "gpio30"; function =3D "qup2"; }; }; =20 - qup_spi3_default: qup-spi3-default { - pinmux { + qup_spi3_default: qup-spi3-default-state { + default-pins { pins =3D "gpio41", "gpio42", "gpio43", "gpio44"; function =3D "qup3"; }; }; =20 - qup_spi4_default: qup-spi4-default { - pinmux { + qup_spi4_default: qup-spi4-default-state { + default-pins { pins =3D "gpio89", "gpio90", "gpio91", "gpio92"; function =3D "qup4"; }; }; =20 - qup_spi5_default: qup-spi5-default { - pinmux { + qup_spi5_default: qup-spi5-default-state { + default-pins { pins =3D "gpio85", "gpio86", "gpio87", "gpio88"; function =3D "qup5"; }; }; =20 - qup_spi6_default: qup-spi6-default { - pinmux { + qup_spi6_default: qup-spi6-default-state { + default-pins { pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; function =3D "qup6"; }; }; =20 - qup_spi7_default: qup-spi7-default { - pinmux { + qup_spi7_default: qup-spi7-default-state { + default-pins { pins =3D "gpio93", "gpio94", "gpio95", "gpio96"; function =3D "qup7"; }; }; =20 - qup_spi8_default: qup-spi8-default { - pinmux { + qup_spi8_default: qup-spi8-default-state { + default-pins { pins =3D "gpio65", "gpio66", "gpio67", "gpio68"; function =3D "qup8"; }; }; =20 - qup_spi9_default: qup-spi9-default { - pinmux { + qup_spi9_default: qup-spi9-default-state { + default-pins { pins =3D "gpio6", "gpio7", "gpio4", "gpio5"; function =3D "qup9"; }; }; =20 - qup_spi10_default: qup-spi10-default { - pinmux { + qup_spi10_default: qup-spi10-default-state { + default-pins { pins =3D "gpio55", "gpio56", "gpio53", "gpio54"; function =3D "qup10"; }; }; =20 - qup_spi11_default: qup-spi11-default { - pinmux { + qup_spi11_default: qup-spi11-default-state { + default-pins { pins =3D "gpio31", "gpio32", "gpio33", "gpio34"; function =3D "qup11"; }; }; =20 - qup_spi12_default: qup-spi12-default { - pinmux { + qup_spi12_default: qup-spi12-default-state { + default-pins { pins =3D "gpio49", "gpio50", "gpio51", "gpio52"; function =3D "qup12"; }; }; =20 - qup_spi13_default: qup-spi13-default { - pinmux { + qup_spi13_default: qup-spi13-default-state { + default-pins { pins =3D "gpio105", "gpio106", "gpio107", "gpio108"; function =3D "qup13"; }; }; =20 - qup_spi14_default: qup-spi14-default { - pinmux { + qup_spi14_default: qup-spi14-default-state { + default-pins { pins =3D "gpio33", "gpio34", "gpio31", "gpio32"; function =3D "qup14"; }; }; =20 - qup_spi15_default: qup-spi15-default { - pinmux { + qup_spi15_default: qup-spi15-default-state { + default-pins { pins =3D "gpio81", "gpio82", "gpio83", "gpio84"; function =3D "qup15"; }; }; =20 - qup_uart0_default: qup-uart0-default { - pinmux { + qup_uart0_default: qup-uart0-default-state { + default-pins { pins =3D "gpio2", "gpio3"; function =3D "qup0"; }; }; =20 - qup_uart1_default: qup-uart1-default { - pinmux { + qup_uart1_default: qup-uart1-default-state { + default-pins { pins =3D "gpio19", "gpio20"; function =3D "qup1"; }; }; =20 - qup_uart2_default: qup-uart2-default { - pinmux { + qup_uart2_default: qup-uart2-default-state { + default-pins { pins =3D "gpio29", "gpio30"; function =3D "qup2"; }; }; =20 - qup_uart3_default: qup-uart3-default { - pinmux { + qup_uart3_default: qup-uart3-default-state { + default-pins { pins =3D "gpio43", "gpio44"; function =3D "qup3"; }; }; =20 - qup_uart4_default: qup-uart4-default { - pinmux { + qup_uart4_default: qup-uart4-default-state { + default-pins { pins =3D "gpio91", "gpio92"; function =3D "qup4"; }; }; =20 - qup_uart5_default: qup-uart5-default { - pinmux { + qup_uart5_default: qup-uart5-default-state { + default-pins { pins =3D "gpio87", "gpio88"; function =3D "qup5"; }; }; =20 - qup_uart6_default: qup-uart6-default { - pinmux { + qup_uart6_default: qup-uart6-default-state { + default-pins { pins =3D "gpio47", "gpio48"; function =3D "qup6"; }; }; =20 - qup_uart7_default: qup-uart7-default { - pinmux { + qup_uart7_default: qup-uart7-default-state { + default-pins { pins =3D "gpio95", "gpio96"; function =3D "qup7"; }; }; =20 - qup_uart8_default: qup-uart8-default { - pinmux { + qup_uart8_default: qup-uart8-default-state { + default-pins { pins =3D "gpio67", "gpio68"; function =3D "qup8"; }; }; =20 - qup_uart9_default: qup-uart9-default { - pinmux { + qup_uart9_default: qup-uart9-default-state { + default-pins { pins =3D "gpio4", "gpio5"; function =3D "qup9"; }; }; =20 - qup_uart10_default: qup-uart10-default { - pinmux { + qup_uart10_default: qup-uart10-default-state { + default-pins { pins =3D "gpio53", "gpio54"; function =3D "qup10"; }; }; =20 - qup_uart11_default: qup-uart11-default { - pinmux { + qup_uart11_default: qup-uart11-default-state { + default-pins { pins =3D "gpio33", "gpio34"; function =3D "qup11"; }; }; =20 - qup_uart12_default: qup-uart12-default { - pinmux { + qup_uart12_default: qup-uart12-default-state { + default-pins { pins =3D "gpio51", "gpio52"; function =3D "qup12"; }; }; =20 - qup_uart13_default: qup-uart13-default { - pinmux { + qup_uart13_default: qup-uart13-default-state { + default-pins { pins =3D "gpio107", "gpio108"; function =3D "qup13"; }; }; =20 - qup_uart14_default: qup-uart14-default { - pinmux { + qup_uart14_default: qup-uart14-default-state { + default-pins { pins =3D "gpio31", "gpio32"; function =3D "qup14"; }; }; =20 - qup_uart15_default: qup-uart15-default { - pinmux { + qup_uart15_default: qup-uart15-default-state { + default-pins { pins =3D "gpio83", "gpio84"; function =3D "qup15"; }; }; =20 - quat_mi2s_sleep: quat_mi2s_sleep { - mux { + quat_mi2s_sleep: quat-mi2s-sleep-state { + default-pins { pins =3D "gpio58", "gpio59"; function =3D "gpio"; - }; - - config { - pins =3D "gpio58", "gpio59"; drive-strength =3D <2>; bias-pull-down; input-enable; }; }; =20 - quat_mi2s_active: quat_mi2s_active { - mux { + quat_mi2s_active: quat-mi2s-active-state { + default-pins { pins =3D "gpio58", "gpio59"; function =3D "qua_mi2s"; - }; - - config { - pins =3D "gpio58", "gpio59"; drive-strength =3D <8>; bias-disable; output-high; }; }; =20 - quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { - mux { + quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { + default-pins { pins =3D "gpio60"; function =3D "gpio"; - }; - - config { - pins =3D "gpio60"; drive-strength =3D <2>; bias-pull-down; input-enable; }; }; =20 - quat_mi2s_sd0_active: quat_mi2s_sd0_active { - mux { + quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { + default-pins { pins =3D "gpio60"; function =3D "qua_mi2s"; - }; - - config { - pins =3D "gpio60"; drive-strength =3D <8>; bias-disable; }; }; =20 - quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { - mux { + quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { + default-pins { pins =3D "gpio61"; function =3D "gpio"; - }; - - config { - pins =3D "gpio61"; drive-strength =3D <2>; bias-pull-down; input-enable; }; }; =20 - quat_mi2s_sd1_active: quat_mi2s_sd1_active { - mux { + quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { + default-pins { pins =3D "gpio61"; function =3D "qua_mi2s"; - }; - - config { - pins =3D "gpio61"; drive-strength =3D <8>; bias-disable; }; }; =20 - quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { - mux { + quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { + default-pins { pins =3D "gpio62"; function =3D "gpio"; - }; - - config { - pins =3D "gpio62"; drive-strength =3D <2>; bias-pull-down; input-enable; }; }; =20 - quat_mi2s_sd2_active: quat_mi2s_sd2_active { - mux { + quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { + default-pins { pins =3D "gpio62"; function =3D "qua_mi2s"; - }; - - config { - pins =3D "gpio62"; drive-strength =3D <8>; bias-disable; }; }; =20 - quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { - mux { + quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { + default-pins { pins =3D "gpio63"; function =3D "gpio"; - }; - - config { - pins =3D "gpio63"; drive-strength =3D <2>; bias-pull-down; input-enable; }; }; =20 - quat_mi2s_sd3_active: quat_mi2s_sd3_active { - mux { + quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { + default-pins { pins =3D "gpio63"; function =3D "qua_mi2s"; - }; - - config { - pins =3D "gpio63"; drive-strength =3D <8>; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/ar= m64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 74f43da51fa5..e4473b31cea9 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -479,7 +479,7 @@ &mss_pil { }; =20 &qup_i2c10_default { - pinconf { + default-pins { pins =3D "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -487,31 +487,29 @@ pinconf { }; =20 &qup_i2c12_default { - pinmux { + default-pins { drive-strength =3D <2>; bias-disable; }; }; =20 &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-pull-down; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; @@ -621,13 +619,14 @@ codec { &tlmm { gpio-reserved-ranges =3D <0 4>, <81 4>; =20 - sn65dsi86_pin_active: sn65dsi86-enable { + sn65dsi86_pin_active: sn65dsi86-enable-state { pins =3D "gpio96"; + function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c3_hid_active: i2c2-hid-active { + i2c3_hid_active: i2c2-hid-active-state { pins =3D "gpio37"; function =3D "gpio"; =20 @@ -636,7 +635,7 @@ i2c3_hid_active: i2c2-hid-active { drive-strength =3D <2>; }; =20 - i2c5_hid_active: i2c5-hid-active { + i2c5_hid_active: i2c5-hid-active-state { pins =3D "gpio125"; function =3D "gpio"; =20 @@ -645,7 +644,7 @@ i2c5_hid_active: i2c5-hid-active { drive-strength =3D <2>; }; =20 - i2c11_hid_active: i2c11-hid-active { + i2c11_hid_active: i2c11-hid-active-state { pins =3D "gpio92"; function =3D "gpio"; =20 @@ -654,7 +653,7 @@ i2c11_hid_active: i2c11-hid-active { drive-strength =3D <2>; }; =20 - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins =3D "gpio54"; function =3D "gpio"; =20 @@ -663,7 +662,7 @@ wcd_intr_default: wcd_intr_default { drive-strength =3D <2>; }; =20 - lid_pin_active: lid-pin { + lid_pin_active: lid-pin-state { pins =3D "gpio124"; function =3D "gpio"; =20 @@ -671,7 +670,7 @@ lid_pin_active: lid-pin { bias-disable; }; =20 - mode_pin_active: mode-pin { + mode_pin_active: mode-pin-state { pins =3D "gpio95"; function =3D "gpio"; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/= boot/dts/qcom/sdm850-samsung-w737.dts index d028a7eb364a..75b612fb4775 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -399,7 +399,7 @@ &mss_pil { }; =20 &qup_i2c10_default { - pinconf { + default-pins { pins =3D "gpio55", "gpio56"; drive-strength =3D <2>; bias-disable; @@ -407,7 +407,7 @@ pinconf { }; =20 &qup_i2c11_default { - pinconf { + default-pins { pins =3D "gpio31", "gpio32"; drive-strength =3D <2>; bias-disable; @@ -415,31 +415,29 @@ pinconf { }; =20 &qup_i2c12_default { - pinmux { + default-pins { drive-strength =3D <2>; bias-disable; }; }; =20 &qup_uart6_default { - pinmux { - pins =3D "gpio45", "gpio46", "gpio47", "gpio48"; - function =3D "qup6"; - }; - - cts { + cts-pins { pins =3D "gpio45"; + function =3D "qup6"; bias-pull-down; }; =20 - rts-tx { + rts-tx-pins { pins =3D "gpio46", "gpio47"; + function =3D "qup6"; drive-strength =3D <2>; bias-disable; }; =20 - rx { + rx-pins { pins =3D "gpio48"; + function =3D "qup6"; bias-pull-up; }; }; @@ -549,59 +547,41 @@ codec { &tlmm { gpio-reserved-ranges =3D <0 6>, <85 4>; =20 - pen_irq_l: pen-irq-l { - pinmux { - pins =3D "gpio119"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio119"; - bias-disable; - }; + pen_irq_l: pen-irq-l-state { + pins =3D "gpio119"; + function =3D "gpio"; + bias-disable; }; =20 - pen_pdct_l: pen-pdct-l { - pinmux { - pins =3D "gpio124"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio124"; - bias-disable; - drive-strength =3D <2>; - output-high; - }; + pen_pdct_l: pen-pdct-l-state { + pins =3D "gpio124"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + output-high; }; =20 - pen_rst_l: pen-rst-l { - pinmux { - pins =3D "gpio21"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio21"; - bias-disable; - drive-strength =3D <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + pen_rst_l: pen-rst-l-state { + pins =3D "gpio21"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; =20 - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins =3D "gpio54"; function =3D "gpio"; =20 --=20 2.34.1 From nobody Sun May 5 03:52:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4E3BC433FE for ; Fri, 30 Sep 2022 20:06:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232338AbiI3UGE (ORCPT ); Fri, 30 Sep 2022 16:06:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232269AbiI3UFy (ORCPT ); Fri, 30 Sep 2022 16:05:54 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A22B115D9A4 for ; Fri, 30 Sep 2022 13:05:46 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id o7so1191235lfk.7 for ; Fri, 30 Sep 2022 13:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=TDfPxCW8Vgo0Tr/WCtPhdAcw4zILqj9ZDUiozuEFfpY=; b=DURzC7s1QTJoBFUsSjVW7/YZObKxyO6fyXYfpb19Vk7XJpF+pruYuFON9bfe9G1j8C jfx7jmM6sdoDzc7GwCQm6qJIKW7UPdw+dmisyUfA9mI7ezD3BfO3wy5K0qvW5JFDAeaP Zb3pRHGROiJ7j+tVUa/Mum7cjdNNWetNh7+rK1xpwTrL+99BpU/iZmlQ0d6VPbsEy4vc CbnzBoRyxj/5gfcMa+cq2AK/R0mTvT+CS7XsXMDmS7ZHM/nrkmVE6jghIo12eh6irbTR 1KvgsYn9aseNL9asP/QxRIUWNhcavN/h72XeczgmxF4+MivPMhSf0JCzdS6v9DIJ5jQk CVBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=TDfPxCW8Vgo0Tr/WCtPhdAcw4zILqj9ZDUiozuEFfpY=; b=H+A+r0Y3477Ix7H7qWa5tV7XzCUitigqbKHLXSS+/C2/7VsKWJBTHKUyHxSPOmQ3yv X93dRFUFZ45/b8iC1Q0ZUi/aZPX/4gM00zmbyR9CmFLTK7Bu7746u1nYhxCLIk37rXdk aAvB+c4vGe4GT9uSAh9P5mi77MAx24tCRvh6GZDQrCMR5u+qZKghDD2pL+K7VqBazjxz M+bv8Xo2XC5McLOiqn2YZgGpnRIPefHwxKp4nQB6RIKDghtnf3j1VFRPZasQn9U4O4Yk iXfngld4OKb+869efGShPN9XA8jd+2/aHWnb6nBabNpadaVEV85LWbg6ztoSbXnz5GFo POaw== X-Gm-Message-State: ACrzQf0pqhKMdjoMNGkD7C8Og8SKPqmd1zKDdgHZdX4kVBafHziOLadP aAOwwbd3yPmjdcIkJdsB5xpdCw== X-Google-Smtp-Source: AMsMyM4YjejXrJlJWuN8ZSM3rqYmkZWZxj4N+lillQ+JPvlRZgz0/0y/3DIUYNsiInQgnk9Qy7a1nQ== X-Received: by 2002:a05:6512:2307:b0:49d:b4c1:f319 with SMTP id o7-20020a056512230700b0049db4c1f319mr3512295lfu.266.1664568344806; Fri, 30 Sep 2022 13:05:44 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id d10-20020ac2544a000000b00492f45cbbfcsm398876lfn.302.2022.09.30.13.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 13:05:44 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] dt-bindings: pinctrl: qcom,sdm845: convert to dtschema Date: Fri, 30 Sep 2022 22:05:29 +0200 Message-Id: <20220930200529.331223-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930200529.331223-1-krzysztof.kozlowski@linaro.org> References: <20220930200529.331223-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert Qualcomm SDM845 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 176 ------------------ .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 158 ++++++++++++++++ 2 files changed, 158 insertions(+), 176 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-p= inctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-p= inctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.= txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt deleted file mode 100644 index 7462e3743c68..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ /dev/null @@ -1,176 +0,0 @@ -Qualcomm SDM845 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -SDM845 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,sdm845-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of t= he -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for= a -pin, a group, or a list of pins or groups. This configuration can include = the -mux function to select on those pin(s)/group(s), and various pin configura= tion -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerat= ed -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are va= lid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio149 - Supports mux, bias and drive-strength - - sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - gpio, adsp_ext, agera_pll, atest_char, atest_tsens, - atest_tsens2, atest_usb1, atest_usb10, atest_usb11, - atest_usb12, atest_usb13, atest_usb2, atest_usb20, - atest_usb21, atest_usb22, atest_usb23, audio_ref, - btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, - cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, - cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, - ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, - gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, - lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, - mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, - pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, - pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, - qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, - qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, - qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, - qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, - sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, - tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, - tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, - tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, - uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, - uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, - vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, - wlan2_adc1, - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@3400000 { - compatible =3D "qcom,sdm845-pinctrl"; - reg =3D <0x03400000 0xc00000>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - interrupt-controller; - #interrupt-cells =3D <2>; - - qup9_active: qup9-active { - mux { - pins =3D "gpio4", "gpio5"; - function =3D "qup9"; - }; - - config { - pins =3D "gpio4", "gpio5"; - drive-strength =3D <2>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml new file mode 100644 index 000000000000..da0ef5698f3e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller node in Qualcomm SDM845 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdm845-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm845-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm845-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdm845-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, + atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_u= sb13, + atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_u= sb23, + audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi= 0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, + gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsyn= c2, + mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0, + pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_en= able, + qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup= 0, + qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, + qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, + sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu, + spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en, + tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinctrl@3400000 { + compatible =3D "qcom,sdm845-pinctrl"; + reg =3D <0x03400000 0xc00000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 151>; + wakeup-parent =3D <&pdc_intc>; + + cci0-default-state { + pins =3D "gpio17", "gpio18"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; + }; + + cam0-default-state { + rst-pins { + pins =3D "gpio9"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + }; + + mclk0-pins { + pins =3D "gpio13"; + function =3D "cam_mclk"; + + drive-strength =3D <16>; + bias-disable; + }; + }; + }; --=20 2.34.1