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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:29:57 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 01/16] arm64: dts: qcom: sm8250: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 21:29:39 +0200 Message-Id: <20220930192954.242546-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Drop also unneeded split between mux and config. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 +- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 38 +- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 16 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 556 +++++++----------- 4 files changed, 239 insertions(+), 383 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts= /qcom/qrb5165-rb5.dts index bf8077a1cf9a..62aa32f460ad 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1210,33 +1210,33 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; =20 - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins =3D "gpio63"; function =3D "gpio"; bias-disable; }; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; bias-disable; drive-strength =3D <16>; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - data { + data-pins { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio77"; function =3D "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8250-mtp.dts index a102aa5efa32..9db6136321b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -799,31 +799,19 @@ wcd_tx: wcd9380-tx@0,3 { &tlmm { gpio-reserved-ranges =3D <28 4>, <40 4>; =20 - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins =3D "gpio32"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio32"; - drive-strength =3D <16>; - output-high; - }; - }; - - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins =3D "gpio32"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio32"; - drive-strength =3D <16>; - bias-disable; - output-low; - }; + wcd938x_reset_default: wcd938x-reset-default-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <16>; + output-high; + }; + + wcd938x_reset_sleep: wcd938x-reset-sleep-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/ar= m64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 549e0a2aa9fe..72162852fae7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -582,34 +582,34 @@ &slpi { &tlmm { gpio-reserved-ranges =3D <40 4>, <52 4>; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <16>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc2_data"; drive-strength =3D <16>; bias-pull-up; }; }; =20 - mdm2ap_default: mdm2ap-default { + mdm2ap_default: mdm2ap-default-state { pins =3D "gpio1", "gpio3"; function =3D "gpio"; drive-strength =3D <8>; bias-disable; }; =20 - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins =3D "gpio39"; function =3D "gpio"; drive-strength =3D <2>; @@ -617,14 +617,14 @@ ts_int_default: ts-int-default { input-enable; }; =20 - ap2mdm_default: ap2mdm-default { + ap2mdm_default: ap2mdm-default-state { pins =3D "gpio56", "gpio57"; function =3D "gpio"; drive-strength =3D <16>; bias-disable; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio77"; function =3D "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index e0416d611b66..7eac3ba90c63 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3798,8 +3798,8 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 181>; wakeup-parent =3D <&pdc>; =20 - cci0_default: cci0-default { - cci0_i2c0_default: cci0-i2c0-default { + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { /* SDA, SCL */ pins =3D "gpio101", "gpio102"; function =3D "cci_i2c"; @@ -3808,7 +3808,7 @@ cci0_i2c0_default: cci0-i2c0-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci0_i2c1_default: cci0-i2c1-default { + cci0_i2c1_default: cci0-i2c1-default-pins { /* SDA, SCL */ pins =3D "gpio103", "gpio104"; function =3D "cci_i2c"; @@ -3818,8 +3818,8 @@ cci0_i2c1_default: cci0-i2c1-default { }; }; =20 - cci0_sleep: cci0-sleep { - cci0_i2c0_sleep: cci0-i2c0-sleep { + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { /* SDA, SCL */ pins =3D "gpio101", "gpio102"; function =3D "cci_i2c"; @@ -3828,7 +3828,7 @@ cci0_i2c0_sleep: cci0-i2c0-sleep { bias-pull-down; }; =20 - cci0_i2c1_sleep: cci0-i2c1-sleep { + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { /* SDA, SCL */ pins =3D "gpio103", "gpio104"; function =3D "cci_i2c"; @@ -3838,8 +3838,8 @@ cci0_i2c1_sleep: cci0-i2c1-sleep { }; }; =20 - cci1_default: cci1-default { - cci1_i2c0_default: cci1-i2c0-default { + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { /* SDA, SCL */ pins =3D "gpio105","gpio106"; function =3D "cci_i2c"; @@ -3848,7 +3848,7 @@ cci1_i2c0_default: cci1-i2c0-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci1_i2c1_default: cci1-i2c1-default { + cci1_i2c1_default: cci1-i2c1-default-pins { /* SDA, SCL */ pins =3D "gpio107","gpio108"; function =3D "cci_i2c"; @@ -3858,8 +3858,8 @@ cci1_i2c1_default: cci1-i2c1-default { }; }; =20 - cci1_sleep: cci1-sleep { - cci1_i2c0_sleep: cci1-i2c0-sleep { + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { /* SDA, SCL */ pins =3D "gpio105","gpio106"; function =3D "cci_i2c"; @@ -3868,7 +3868,7 @@ cci1_i2c0_sleep: cci1-i2c0-sleep { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci1_i2c1_sleep: cci1-i2c1-sleep { + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { /* SDA, SCL */ pins =3D "gpio107","gpio108"; function =3D "cci_i2c"; @@ -3878,22 +3878,22 @@ cci1_i2c1_sleep: cci1-i2c1-sleep { }; }; =20 - pri_mi2s_active: pri-mi2s-active { - sclk { + pri_mi2s_active: pri-mi2s-active-state { + sclk-pins { pins =3D "gpio138"; function =3D "mi2s0_sck"; drive-strength =3D <8>; bias-disable; }; =20 - ws { + ws-pins { pins =3D "gpio141"; function =3D "mi2s0_ws"; drive-strength =3D <8>; output-high; }; =20 - data0 { + data0-pins { pins =3D "gpio139"; function =3D "mi2s0_data0"; drive-strength =3D <8>; @@ -3901,7 +3901,7 @@ data0 { output-high; }; =20 - data1 { + data1-pins { pins =3D "gpio140"; function =3D "mi2s0_data1"; drive-strength =3D <8>; @@ -3909,632 +3909,500 @@ data1 { }; }; =20 - qup_i2c0_default: qup-i2c0-default { - mux { - pins =3D "gpio28", "gpio29"; - function =3D "qup0"; - }; - - config { - pins =3D "gpio28", "gpio29"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins =3D "gpio28", "gpio29"; + function =3D "qup0"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins =3D "gpio4", "gpio5"; - function =3D "qup1"; - }; - - config { - pins =3D "gpio4", "gpio5"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "qup1"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c2_default: qup-i2c2-default { - mux { - pins =3D "gpio115", "gpio116"; - function =3D "qup2"; - }; - - config { - pins =3D "gpio115", "gpio116"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins =3D "gpio115", "gpio116"; + function =3D "qup2"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c3_default: qup-i2c3-default { - mux { - pins =3D "gpio119", "gpio120"; - function =3D "qup3"; - }; - - config { - pins =3D "gpio119", "gpio120"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins =3D "gpio119", "gpio120"; + function =3D "qup3"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c4_default: qup-i2c4-default { - mux { - pins =3D "gpio8", "gpio9"; - function =3D "qup4"; - }; - - config { - pins =3D "gpio8", "gpio9"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins =3D "gpio8", "gpio9"; + function =3D "qup4"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c5_default: qup-i2c5-default { - mux { - pins =3D "gpio12", "gpio13"; - function =3D "qup5"; - }; - - config { - pins =3D "gpio12", "gpio13"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "qup5"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c6_default: qup-i2c6-default { - mux { - pins =3D "gpio16", "gpio17"; - function =3D "qup6"; - }; - - config { - pins =3D "gpio16", "gpio17"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins =3D "gpio16", "gpio17"; + function =3D "qup6"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c7_default: qup-i2c7-default { - mux { - pins =3D "gpio20", "gpio21"; - function =3D "qup7"; - }; - - config { - pins =3D "gpio20", "gpio21"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins =3D "gpio20", "gpio21"; + function =3D "qup7"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c8_default: qup-i2c8-default { - mux { - pins =3D "gpio24", "gpio25"; - function =3D "qup8"; - }; - - config { - pins =3D "gpio24", "gpio25"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins =3D "gpio24", "gpio25"; + function =3D "qup8"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c9_default: qup-i2c9-default { - mux { - pins =3D "gpio125", "gpio126"; - function =3D "qup9"; - }; - - config { - pins =3D "gpio125", "gpio126"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins =3D "gpio125", "gpio126"; + function =3D "qup9"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c10_default: qup-i2c10-default { - mux { - pins =3D "gpio129", "gpio130"; - function =3D "qup10"; - }; - - config { - pins =3D "gpio129", "gpio130"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins =3D "gpio129", "gpio130"; + function =3D "qup10"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c11_default: qup-i2c11-default { - mux { - pins =3D "gpio60", "gpio61"; - function =3D "qup11"; - }; - - config { - pins =3D "gpio60", "gpio61"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins =3D "gpio60", "gpio61"; + function =3D "qup11"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c12_default: qup-i2c12-default { - mux { - pins =3D "gpio32", "gpio33"; - function =3D "qup12"; - }; - - config { - pins =3D "gpio32", "gpio33"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins =3D "gpio32", "gpio33"; + function =3D "qup12"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c13_default: qup-i2c13-default { - mux { - pins =3D "gpio36", "gpio37"; - function =3D "qup13"; - }; - - config { - pins =3D "gpio36", "gpio37"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup13"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c14_default: qup-i2c14-default { - mux { - pins =3D "gpio40", "gpio41"; - function =3D "qup14"; - }; - - config { - pins =3D "gpio40", "gpio41"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins =3D "gpio40", "gpio41"; + function =3D "qup14"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c15_default: qup-i2c15-default { - mux { - pins =3D "gpio44", "gpio45"; - function =3D "qup15"; - }; - - config { - pins =3D "gpio44", "gpio45"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins =3D "gpio44", "gpio45"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c16_default: qup-i2c16-default { - mux { - pins =3D "gpio48", "gpio49"; - function =3D "qup16"; - }; - - config { - pins =3D "gpio48", "gpio49"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c16_default: qup-i2c16-default-state { + pins =3D "gpio48", "gpio49"; + function =3D "qup16"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c17_default: qup-i2c17-default { - mux { - pins =3D "gpio52", "gpio53"; - function =3D "qup17"; - }; - - config { - pins =3D "gpio52", "gpio53"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c17_default: qup-i2c17-default-state { + pins =3D "gpio52", "gpio53"; + function =3D "qup17"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c18_default: qup-i2c18-default { - mux { - pins =3D "gpio56", "gpio57"; - function =3D "qup18"; - }; - - config { - pins =3D "gpio56", "gpio57"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c18_default: qup-i2c18-default-state { + pins =3D "gpio56", "gpio57"; + function =3D "qup18"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c19_default: qup-i2c19-default { - mux { - pins =3D "gpio0", "gpio1"; - function =3D "qup19"; - }; - - config { - pins =3D "gpio0", "gpio1"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c19_default: qup-i2c19-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup19"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-state { pins =3D "gpio31"; function =3D "qup0"; }; =20 - qup_spi0_cs_gpio: qup-spi0-cs-gpio { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins =3D "gpio31"; function =3D "gpio"; }; =20 - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins =3D "gpio28", "gpio29", "gpio30"; function =3D "qup0"; }; =20 - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-state { pins =3D "gpio7"; function =3D "qup1"; }; =20 - qup_spi1_cs_gpio: qup-spi1-cs-gpio { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins =3D "gpio7"; function =3D "gpio"; }; =20 - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins =3D "gpio4", "gpio5", "gpio6"; function =3D "qup1"; }; =20 - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-state { pins =3D "gpio118"; function =3D "qup2"; }; =20 - qup_spi2_cs_gpio: qup-spi2-cs-gpio { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins =3D "gpio118"; function =3D "gpio"; }; =20 - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins =3D "gpio115", "gpio116", "gpio117"; function =3D "qup2"; }; =20 - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-state { pins =3D "gpio122"; function =3D "qup3"; }; =20 - qup_spi3_cs_gpio: qup-spi3-cs-gpio { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins =3D "gpio122"; function =3D "gpio"; }; =20 - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins =3D "gpio119", "gpio120", "gpio121"; function =3D "qup3"; }; =20 - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-state { pins =3D "gpio11"; function =3D "qup4"; }; =20 - qup_spi4_cs_gpio: qup-spi4-cs-gpio { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins =3D "gpio11"; function =3D "gpio"; }; =20 - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins =3D "gpio8", "gpio9", "gpio10"; function =3D "qup4"; }; =20 - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-state { pins =3D "gpio15"; function =3D "qup5"; }; =20 - qup_spi5_cs_gpio: qup-spi5-cs-gpio { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins =3D "gpio15"; function =3D "gpio"; }; =20 - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins =3D "gpio12", "gpio13", "gpio14"; function =3D "qup5"; }; =20 - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-state { pins =3D "gpio19"; function =3D "qup6"; }; =20 - qup_spi6_cs_gpio: qup-spi6-cs-gpio { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins =3D "gpio19"; function =3D "gpio"; }; =20 - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins =3D "gpio16", "gpio17", "gpio18"; function =3D "qup6"; }; =20 - qup_spi7_cs: qup-spi7-cs { + qup_spi7_cs: qup-spi7-cs-state { pins =3D "gpio23"; function =3D "qup7"; }; =20 - qup_spi7_cs_gpio: qup-spi7-cs-gpio { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins =3D "gpio23"; function =3D "gpio"; }; =20 - qup_spi7_data_clk: qup-spi7-data-clk { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins =3D "gpio20", "gpio21", "gpio22"; function =3D "qup7"; }; =20 - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-state { pins =3D "gpio27"; function =3D "qup8"; }; =20 - qup_spi8_cs_gpio: qup-spi8-cs-gpio { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins =3D "gpio27"; function =3D "gpio"; }; =20 - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins =3D "gpio24", "gpio25", "gpio26"; function =3D "qup8"; }; =20 - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-state { pins =3D "gpio128"; function =3D "qup9"; }; =20 - qup_spi9_cs_gpio: qup-spi9-cs-gpio { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins =3D "gpio128"; function =3D "gpio"; }; =20 - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins =3D "gpio125", "gpio126", "gpio127"; function =3D "qup9"; }; =20 - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-state { pins =3D "gpio132"; function =3D "qup10"; }; =20 - qup_spi10_cs_gpio: qup-spi10-cs-gpio { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins =3D "gpio132"; function =3D "gpio"; }; =20 - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins =3D "gpio129", "gpio130", "gpio131"; function =3D "qup10"; }; =20 - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-state { pins =3D "gpio63"; function =3D "qup11"; }; =20 - qup_spi11_cs_gpio: qup-spi11-cs-gpio { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins =3D "gpio63"; function =3D "gpio"; }; =20 - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins =3D "gpio60", "gpio61", "gpio62"; function =3D "qup11"; }; =20 - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-state { pins =3D "gpio35"; function =3D "qup12"; }; =20 - qup_spi12_cs_gpio: qup-spi12-cs-gpio { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins =3D "gpio35"; function =3D "gpio"; }; =20 - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins =3D "gpio32", "gpio33", "gpio34"; function =3D "qup12"; }; =20 - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-state { pins =3D "gpio39"; function =3D "qup13"; }; =20 - qup_spi13_cs_gpio: qup-spi13-cs-gpio { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins =3D "gpio39"; function =3D "gpio"; }; =20 - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins =3D "gpio36", "gpio37", "gpio38"; function =3D "qup13"; }; =20 - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-state { pins =3D "gpio43"; function =3D "qup14"; }; =20 - qup_spi14_cs_gpio: qup-spi14-cs-gpio { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins =3D "gpio43"; function =3D "gpio"; }; =20 - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins =3D "gpio40", "gpio41", "gpio42"; function =3D "qup14"; }; =20 - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-state { pins =3D "gpio47"; function =3D "qup15"; }; =20 - qup_spi15_cs_gpio: qup-spi15-cs-gpio { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins =3D "gpio47"; function =3D "gpio"; }; =20 - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins =3D "gpio44", "gpio45", "gpio46"; function =3D "qup15"; }; =20 - qup_spi16_cs: qup-spi16-cs { + qup_spi16_cs: qup-spi16-cs-state { pins =3D "gpio51"; function =3D "qup16"; }; =20 - qup_spi16_cs_gpio: qup-spi16-cs-gpio { + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { pins =3D "gpio51"; function =3D "gpio"; }; =20 - qup_spi16_data_clk: qup-spi16-data-clk { + qup_spi16_data_clk: qup-spi16-data-clk-state { pins =3D "gpio48", "gpio49", "gpio50"; function =3D "qup16"; }; =20 - qup_spi17_cs: qup-spi17-cs { + qup_spi17_cs: qup-spi17-cs-state { pins =3D "gpio55"; function =3D "qup17"; }; =20 - qup_spi17_cs_gpio: qup-spi17-cs-gpio { + qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { pins =3D "gpio55"; function =3D "gpio"; }; =20 - qup_spi17_data_clk: qup-spi17-data-clk { + qup_spi17_data_clk: qup-spi17-data-clk-state { pins =3D "gpio52", "gpio53", "gpio54"; function =3D "qup17"; }; =20 - qup_spi18_cs: qup-spi18-cs { + qup_spi18_cs: qup-spi18-cs-state { pins =3D "gpio59"; function =3D "qup18"; }; =20 - qup_spi18_cs_gpio: qup-spi18-cs-gpio { + qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { pins =3D "gpio59"; function =3D "gpio"; }; =20 - qup_spi18_data_clk: qup-spi18-data-clk { + qup_spi18_data_clk: qup-spi18-data-clk-state { pins =3D "gpio56", "gpio57", "gpio58"; function =3D "qup18"; }; =20 - qup_spi19_cs: qup-spi19-cs { + qup_spi19_cs: qup-spi19-cs-state { pins =3D "gpio3"; function =3D "qup19"; }; =20 - qup_spi19_cs_gpio: qup-spi19-cs-gpio { + qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { pins =3D "gpio3"; function =3D "gpio"; }; =20 - qup_spi19_data_clk: qup-spi19-data-clk { + qup_spi19_data_clk: qup-spi19-data-clk-state { pins =3D "gpio0", "gpio1", "gpio2"; function =3D "qup19"; }; =20 - qup_uart2_default: qup-uart2-default { - mux { - pins =3D "gpio117", "gpio118"; - function =3D "qup2"; - }; + qup_uart2_default: qup-uart2-default-state { + pins =3D "gpio117", "gpio118"; + function =3D "qup2"; }; =20 - qup_uart6_default: qup-uart6-default { - mux { - pins =3D "gpio16", "gpio17", - "gpio18", "gpio19"; - function =3D "qup6"; - }; + qup_uart6_default: qup-uart6-default-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "qup6"; }; =20 - qup_uart12_default: qup-uart12-default { - mux { - pins =3D "gpio34", "gpio35"; - function =3D "qup12"; - }; + qup_uart12_default: qup-uart12-default-state { + pins =3D "gpio34", "gpio35"; + function =3D "qup12"; }; =20 - qup_uart17_default: qup-uart17-default { - mux { - pins =3D "gpio52", "gpio53", - "gpio54", "gpio55"; - function =3D "qup17"; - }; + qup_uart17_default: qup-uart17-default-state { + pins =3D "gpio52", "gpio53", "gpio54", "gpio55"; + function =3D "qup17"; }; =20 - qup_uart18_default: qup-uart18-default { - mux { - pins =3D "gpio58", "gpio59"; - function =3D "qup18"; - }; + qup_uart18_default: qup-uart18-default-state { + pins =3D "gpio58", "gpio59"; + function =3D "qup18"; }; =20 - tert_mi2s_active: tert-mi2s-active { - sck { + tert_mi2s_active: tert-mi2s-active-state { + sck-pins { pins =3D "gpio133"; function =3D "mi2s2_sck"; drive-strength =3D <8>; bias-disable; }; =20 - data0 { + data0-pins { pins =3D "gpio134"; function =3D "mi2s2_data0"; drive-strength =3D <8>; @@ -4542,7 +4410,7 @@ data0 { output-high; }; =20 - ws { + ws-pins { pins =3D "gpio135"; function =3D "mi2s2_ws"; drive-strength =3D <8>; @@ -4550,42 +4418,42 @@ ws { }; }; =20 - sdc2_sleep_state: sdc2-sleep { - clk { + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <2>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <2>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc2_data"; drive-strength =3D <2>; bias-pull-up; }; }; =20 - pcie0_default_state: pcie0-default { - perst { + pcie0_default_state: pcie0-default-state { + perst-pins { pins =3D "gpio79"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio80"; function =3D "pci_e0"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio81"; function =3D "gpio"; drive-strength =3D <2>; @@ -4593,22 +4461,22 @@ wake { }; }; =20 - pcie1_default_state: pcie1-default { - perst { + pcie1_default_state: pcie1-default-state { + perst-pins { pins =3D "gpio82"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio83"; function =3D "pci_e1"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio84"; function =3D "gpio"; drive-strength =3D <2>; @@ -4616,22 +4484,22 @@ wake { }; }; =20 - pcie2_default_state: pcie2-default { - perst { + pcie2_default_state: pcie2-default-state { + perst-pins { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio86"; function =3D "pci_e2"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio87"; function =3D "gpio"; drive-strength =3D <2>; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55F64C43217 for ; Fri, 30 Sep 2022 19:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231172AbiI3Ta2 (ORCPT ); Fri, 30 Sep 2022 15:30:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231706AbiI3TaH (ORCPT ); Fri, 30 Sep 2022 15:30:07 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AB6E2CE07 for ; Fri, 30 Sep 2022 12:30:01 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id q14so1599635lfo.11 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:29:58 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 02/16] arm64: dts: qcom: sm8250-sony-xperia-edo: fix touchscreen bias-disable Date: Fri, 30 Sep 2022 21:29:40 +0200 Message-Id: <20220930192954.242546-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The property to disable bias is "bias-disable". Fixes: e76c7e1f15fe ("arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen= ") Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/ar= m64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 72162852fae7..601a21c381f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -613,7 +613,7 @@ ts_int_default: ts-int-default-state { pins =3D "gpio39"; function =3D "gpio"; drive-strength =3D <2>; - bias-disabled; + bias-disable; input-enable; }; =20 --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C42AC4332F for ; Fri, 30 Sep 2022 19:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231928AbiI3Tac (ORCPT ); Fri, 30 Sep 2022 15:30:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbiI3TaR (ORCPT ); Fri, 30 Sep 2022 15:30:17 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E42BB2C665 for ; Fri, 30 Sep 2022 12:30:02 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id s10so5806122ljp.5 for ; Fri, 30 Sep 2022 12:30:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Lb2yg7Pt4DxTka9+KV6Co4SrBHPOoUuiBCx5duzCR9A=; b=b7FJzs0y0ZOg+uDpLQWkuySxRK/xEdxb73N2jzPsSJuZf+nW58jEMPA3iQJMkW1iNN 0uylutnZEq014/NLKw3YyGeUjVMuvWyWR84AVZOb2FdvjgBy4xF/3apFGKszY5YsKXw6 Aixa9bxwx7SLB9JSBkOpXnIqz5CYq/HuaRC7zsUioNZqdGL3FVQCXcY546L2mglPZS/r 23CaktcHLv/DoLeAcYYYCQKR6b1RlDiw/im2InpHcz4GW11L1wgq8+FN7bYN/ROyVLEL dm6cE0bfVx1N/UsP9vlDq2Bob5m7sx6+Slu8MmfRyJKMXT0VOxV0z4+1P3PGLXl726e0 UTgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Lb2yg7Pt4DxTka9+KV6Co4SrBHPOoUuiBCx5duzCR9A=; b=k+AsvtP1BJqgtprBV2tIG+HkuRpHRpxp6AmBtsD28Lt1AsulZMoOZbCNaevXVvxv08 GyYjC6JaeFzpz2/3KAOF2fYb5Cc0TbCDMxqUTiaywhGHWXzE0pOL/3DOuzzPU2dcEst7 oRKdp8dwxCjf/pKexsfYCFWcOREJ8aQXL0ZWFf7Eh1uSufrJeUlBy6/7w23Q5Ym/whvx X/vwXe7ji6hMjTCW3U9SK2T7iehiUSskRlUs1xH8P9vLkRrqXmAd0yiQDU8uZ7V+q7d3 7TNHg60TdO2nSaSA+VBETS5+G20VpjpyvEELZO27o1QhkM720RKsxGeCSq61Rmf5+XN5 FxBg== X-Gm-Message-State: ACrzQf0aG7CpEEKJlVivCD2aHOdrQnKgHvNVeKv8aUFSmjRkysPncNLb 0WCEPVb62+pF/VvAeLAb7cvBtg== X-Google-Smtp-Source: AMsMyM77CLzXh4xZxRxEciMDgQAB2TqSrV7Ow+HBHesd0WBCQkdu0+TKE7+uxlf/vB5B556MNZ62yg== X-Received: by 2002:a05:651c:239c:b0:26d:94b8:781d with SMTP id bk28-20020a05651c239c00b0026d94b8781dmr3101983ljb.189.1664566200595; Fri, 30 Sep 2022 12:30:00 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:00 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 03/16] arm64: dts: qcom: sc8280xp: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 21:29:41 +0200 Message-Id: <20220930192954.242546-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sc8280xp-crd.dtb: pinctrl@f100000: kybd-default-state: 'oneOf' condi= tional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'disable', 'int-n', 'reset' do not match any of the regexes: 'pinctrl-[= 0-9]+' 'disable', 'int-n', 'reset' do not match any of the regexes: '-pins$', = 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 12 ++++++------ .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index fea7d8273ccd..a2027f1d1d04 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -374,19 +374,19 @@ &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 kybd_default: kybd-default-state { - disable { + disable-pins { pins =3D "gpio102"; function =3D "gpio"; output-low; }; =20 - int-n { + int-n-pins { pins =3D "gpio104"; function =3D "gpio"; bias-disable; }; =20 - reset { + reset-pins { pins =3D "gpio105"; function =3D "gpio"; bias-disable; @@ -410,7 +410,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; =20 tpad_default: tpad-default-state { - int-n { + int-n-pins { pins =3D "gpio182"; function =3D "gpio"; bias-disable; @@ -418,13 +418,13 @@ int-n { }; =20 ts0_default: ts0-default-state { - int-n { + int-n-pins { pins =3D "gpio175"; function =3D "gpio"; bias-disable; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio99"; function =3D "gpio"; output-high; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index b2b744bb8a53..68b61e8d03c0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -350,19 +350,19 @@ &tlmm { gpio-reserved-ranges =3D <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7= >; =20 kybd_default: kybd-default-state { - disable { + disable-pins { pins =3D "gpio102"; function =3D "gpio"; output-low; }; =20 - int-n { + int-n-pins { pins =3D "gpio104"; function =3D "gpio"; bias-disable; }; =20 - reset { + reset-pins { pins =3D "gpio105"; function =3D "gpio"; bias-disable; @@ -384,7 +384,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; =20 tpad_default: tpad-default-state { - int-n { + int-n-pins { pins =3D "gpio182"; function =3D "gpio"; bias-disable; @@ -392,13 +392,13 @@ int-n { }; =20 ts0_default: ts0-default-state { - int-n { + int-n-pins { pins =3D "gpio175"; function =3D "gpio"; bias-disable; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio99"; function =3D "gpio"; output-high; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C654C433F5 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:01 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 04/16] arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema (really) Date: Fri, 30 Sep 2022 21:29:42 +0200 Message-Id: <20220930192954.242546-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. I already tried to do this in commit d801357a0573 ("arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema") and I missed the fact that these nodes were not part of "state" node. Bindings did not catch these errors due to its own issues. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 8 +- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 44 +-- .../arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 8 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 26 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 20 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 316 +++++++++--------- 6 files changed, 211 insertions(+), 211 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/d= ts/qcom/sc7280-crd-r3.dts index dddb505e220b..1185141f348e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -118,25 +118,25 @@ &wcd9385 { }; =20 &tlmm { - tp_int_odl: tp-int-odl { + tp_int_odl: tp-int-odl-state { pins =3D "gpio7"; function =3D "gpio"; bias-disable; }; =20 - ts_int_l: ts-int-l { + ts_int_l: ts-int-l-state { pins =3D "gpio55"; function =3D "gpio"; bias-pull-up; }; =20 - ts_reset_l: ts-reset-l { + ts_reset_l: ts-reset-l-state { pins =3D "gpio54"; function =3D "gpio"; bias-disable; }; =20 - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins =3D "gpio81"; function =3D "gpio"; bias-pull-down; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index c11e37160f34..6a9389c40159 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -744,27 +744,27 @@ &tlmm { pinctrl-names =3D "default"; pinctrl-0 =3D <&bios_flash_wp_od>; =20 - amp_en: amp-en-pins { + amp_en: amp-en-state { pins =3D "gpio63"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins =3D "gpio18"; function =3D "gpio"; bias-pull-up; }; =20 - bios_flash_wp_od: bios-flash-wp-od-pins { + bios_flash_wp_od: bios-flash-wp-od-state { pins =3D "gpio16"; function =3D "gpio"; /* Has external pull */ bias-disable; }; =20 - en_fp_rails: en-fp-rails-pins { + en_fp_rails: en-fp-rails-state { pins =3D "gpio77"; function =3D "gpio"; bias-disable; @@ -772,60 +772,60 @@ en_fp_rails: en-fp-rails-pins { output-high; }; =20 - en_pp3300_codec: en-pp3300-codec-pins { + en_pp3300_codec: en-pp3300-codec-state { pins =3D "gpio105"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - en_pp3300_dx_edp: en-pp3300-dx-edp-pins { + en_pp3300_dx_edp: en-pp3300-dx-edp-state { pins =3D "gpio80"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - fp_rst_l: fp-rst-l-pins { + fp_rst_l: fp-rst-l-state { pins =3D "gpio78"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - fp_to_ap_irq_l: fp-to-ap-irq-l-pins { + fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins =3D "gpio61"; function =3D "gpio"; /* Has external pullup */ bias-disable; }; =20 - fpmcu_boot0: fpmcu-boot0-pins { + fpmcu_boot0: fpmcu-boot0-state { pins =3D "gpio68"; function =3D "gpio"; bias-disable; }; =20 - gsc_ap_int_odl: gsc-ap-int-odl-pins { + gsc_ap_int_odl: gsc-ap-int-odl-state { pins =3D "gpio104"; function =3D "gpio"; bias-pull-up; }; =20 - hp_irq: hp-irq-pins { + hp_irq: hp-irq-state { pins =3D "gpio101"; function =3D "gpio"; bias-pull-up; }; =20 - hub_en: hub-en-pins { + hub_en: hub-en-state { pins =3D "gpio157"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - pe_wake_odl: pe-wake-odl-pins { + pe_wake_odl: pe-wake-odl-state { pins =3D "gpio3"; function =3D "gpio"; /* Has external pull */ @@ -834,45 +834,45 @@ pe_wake_odl: pe-wake-odl-pins { }; =20 /* For ap_spi_fp */ - qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins { + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-state { pins =3D "gpio39"; function =3D "gpio"; output-high; }; =20 /* For ap_ec_spi */ - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; function =3D "gpio"; output-high; }; =20 - sar0_irq_odl: sar0-irq-odl-pins { + sar0_irq_odl: sar0-irq-odl-state { pins =3D "gpio141"; function =3D "gpio"; bias-pull-up; }; =20 - sar1_irq_odl: sar1-irq-odl-pins { + sar1_irq_odl: sar1-irq-odl-state { pins =3D "gpio140"; function =3D "gpio"; bias-pull-up; }; =20 - sd_cd_odl: sd-cd-odl-pins { + sd_cd_odl: sd-cd-odl-state { pins =3D "gpio91"; function =3D "gpio"; bias-pull-up; }; =20 - ssd_en: ssd-en-pins { + ssd_en: ssd-en-state { pins =3D "gpio51"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - ssd_rst_l: ssd-rst-l-pins { + ssd_rst_l: ssd-rst-l-state { pins =3D "gpio2"; function =3D "gpio"; bias-disable; @@ -880,14 +880,14 @@ ssd_rst_l: ssd-rst-l-pins { output-low; }; =20 - tp_int_odl: tp-int-odl-pins { + tp_int_odl: tp-int-odl-state { pins =3D "gpio7"; function =3D "gpio"; /* Has external pullup */ bias-disable; }; =20 - wf_cam_en: wf-cam-en-pins { + wf_cam_en: wf-cam-en-state { pins =3D "gpio119"; function =3D "gpio"; /* Has external pulldown */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index 7f5143e9bb80..b35f3738933c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -79,26 +79,26 @@ cr50: tpm@0 { }; =20 &tlmm { - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins =3D "gpio18"; function =3D "gpio"; input-enable; bias-pull-up; }; =20 - h1_ap_int_odl: h1-ap-int-odl-pins { + h1_ap_int_odl: h1-ap-int-odl-state { pins =3D "gpio104"; function =3D "gpio"; input-enable; bias-pull-up; }; =20 - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; output-high; }; =20 - qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins { + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins =3D "gpio59"; output-high; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index cd432a2856a7..11982c14b704 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -747,24 +747,24 @@ &sdc2_data { }; =20 &tlmm { - amp_en: amp-en { + amp_en: amp-en-state { pins =3D "gpio63"; bias-pull-down; drive-strength =3D <2>; }; =20 - bt_en: bt-en-pins { + bt_en: bt-en-state { pins =3D "gpio85"; function =3D "gpio"; output-low; bias-disable; }; =20 - nvme_pwren: nvme-pwren-pins { + nvme_pwren: nvme-pwren-state { function =3D "gpio"; }; =20 - pcie1_reset_n: pcie1-reset-n-pins { + pcie1_reset_n: pcie1-reset-n-state { pins =3D "gpio2"; function =3D "gpio"; =20 @@ -773,7 +773,7 @@ pcie1_reset_n: pcie1-reset-n-pins { bias-disable; }; =20 - pcie1_wake_n: pcie1-wake-n-pins { + pcie1_wake_n: pcie1-wake-n-state { pins =3D "gpio3"; function =3D "gpio"; =20 @@ -781,7 +781,7 @@ pcie1_wake_n: pcie1-wake-n-pins { bias-pull-up; }; =20 - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins =3D "gpio28"; function =3D "gpio"; /* @@ -794,7 +794,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { bias-bus-hold; }; =20 - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins =3D "gpio29"; function =3D "gpio"; /* @@ -806,7 +806,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { bias-pull-down; }; =20 - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins =3D "gpio30"; function =3D "gpio"; /* @@ -816,7 +816,7 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; =20 - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins =3D "gpio31"; function =3D "gpio"; /* @@ -827,25 +827,25 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { bias-pull-up; }; =20 - sd_cd: sd-cd-pins { + sd_cd: sd-cd-state { pins =3D "gpio91"; function =3D "gpio"; bias-pull-up; }; =20 - sw_ctrl: sw-ctrl-pins { + sw_ctrl: sw-ctrl-state { pins =3D "gpio86"; function =3D "gpio"; bias-pull-down; }; =20 - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; }; =20 - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/d= ts/qcom/sc7280-qcard.dtsi index 4b8c676b0bb1..a42b5878a75f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -595,7 +595,7 @@ pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { }; =20 &tlmm { - mos_bt_en: mos-bt-en-pins { + mos_bt_en: mos-bt-en-state { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; @@ -603,7 +603,7 @@ mos_bt_en: mos-bt-en-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins =3D "gpio28"; function =3D "gpio"; /* @@ -617,7 +617,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins =3D "gpio29"; function =3D "gpio"; /* @@ -630,7 +630,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins =3D "gpio31"; function =3D "gpio"; /* @@ -642,7 +642,7 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins =3D "gpio30"; function =3D "gpio"; /* @@ -652,32 +652,32 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; =20 - ts_int_conn: ts-int-conn-pins { + ts_int_conn: ts-int-conn-state { pins =3D "gpio55"; function =3D "gpio"; bias-pull-up; }; =20 - ts_rst_conn: ts-rst-conn-pins { + ts_rst_conn: ts-rst-conn-state { pins =3D "gpio54"; function =3D "gpio"; drive-strength =3D <2>; }; =20 - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins =3D "gpio81"; function =3D "gpio"; bias-pull-down; drive-strength =3D <2>; }; =20 - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; }; =20 - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 28e3fb9992d9..1a603cf61d8b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4253,791 +4253,791 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 175>; wakeup-parent =3D <&pdc>; =20 - dp_hot_plug_det: dp-hot-plug-det-pins { + dp_hot_plug_det: dp-hot-plug-det-state { pins =3D "gpio47"; function =3D "dp_hot"; }; =20 - edp_hot_plug_det: edp-hot-plug-det-pins { + edp_hot_plug_det: edp-hot-plug-det-state { pins =3D "gpio60"; function =3D "edp_hot"; }; =20 - mi2s0_data0: mi2s0-data0-pins { + mi2s0_data0: mi2s0-data0-state { pins =3D "gpio98"; function =3D "mi2s0_data0"; }; =20 - mi2s0_data1: mi2s0-data1-pins { + mi2s0_data1: mi2s0-data1-state { pins =3D "gpio99"; function =3D "mi2s0_data1"; }; =20 - mi2s0_mclk: mi2s0-mclk-pins { + mi2s0_mclk: mi2s0-mclk-state { pins =3D "gpio96"; function =3D "pri_mi2s"; }; =20 - mi2s0_sclk: mi2s0-sclk-pins { + mi2s0_sclk: mi2s0-sclk-state { pins =3D "gpio97"; function =3D "mi2s0_sck"; }; =20 - mi2s0_ws: mi2s0-ws-pins { + mi2s0_ws: mi2s0-ws-state { pins =3D "gpio100"; function =3D "mi2s0_ws"; }; =20 - mi2s1_data0: mi2s1-data0-pins { + mi2s1_data0: mi2s1-data0-state { pins =3D "gpio107"; function =3D "mi2s1_data0"; }; =20 - mi2s1_sclk: mi2s1-sclk-pins { + mi2s1_sclk: mi2s1-sclk-state { pins =3D "gpio106"; function =3D "mi2s1_sck"; }; =20 - mi2s1_ws: mi2s1-ws-pins { + mi2s1_ws: mi2s1-ws-state { pins =3D "gpio108"; function =3D "mi2s1_ws"; }; =20 - pcie1_clkreq_n: pcie1-clkreq-n-pins { + pcie1_clkreq_n: pcie1-clkreq-n-state { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; }; =20 - qspi_clk: qspi-clk-pins { + qspi_clk: qspi-clk-state { pins =3D "gpio14"; function =3D "qspi_clk"; }; =20 - qspi_cs0: qspi-cs0-pins { + qspi_cs0: qspi-cs0-state { pins =3D "gpio15"; function =3D "qspi_cs"; }; =20 - qspi_cs1: qspi-cs1-pins { + qspi_cs1: qspi-cs1-state { pins =3D "gpio19"; function =3D "qspi_cs"; }; =20 - qspi_data01: qspi-data01-pins { + qspi_data01: qspi-data01-state { pins =3D "gpio12", "gpio13"; function =3D "qspi_data"; }; =20 - qspi_data12: qspi-data12-pins { + qspi_data12: qspi-data12-state { pins =3D "gpio16", "gpio17"; function =3D "qspi_data"; }; =20 - qup_i2c0_data_clk: qup-i2c0-data-clk-pins { + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins =3D "gpio0", "gpio1"; function =3D "qup00"; }; =20 - qup_i2c1_data_clk: qup-i2c1-data-clk-pins { + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins =3D "gpio4", "gpio5"; function =3D "qup01"; }; =20 - qup_i2c2_data_clk: qup-i2c2-data-clk-pins { + qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins =3D "gpio8", "gpio9"; function =3D "qup02"; }; =20 - qup_i2c3_data_clk: qup-i2c3-data-clk-pins { + qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins =3D "gpio12", "gpio13"; function =3D "qup03"; }; =20 - qup_i2c4_data_clk: qup-i2c4-data-clk-pins { + qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins =3D "gpio16", "gpio17"; function =3D "qup04"; }; =20 - qup_i2c5_data_clk: qup-i2c5-data-clk-pins { + qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins =3D "gpio20", "gpio21"; function =3D "qup05"; }; =20 - qup_i2c6_data_clk: qup-i2c6-data-clk-pins { + qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins =3D "gpio24", "gpio25"; function =3D "qup06"; }; =20 - qup_i2c7_data_clk: qup-i2c7-data-clk-pins { + qup_i2c7_data_clk: qup-i2c7-data-clk-state { pins =3D "gpio28", "gpio29"; function =3D "qup07"; }; =20 - qup_i2c8_data_clk: qup-i2c8-data-clk-pins { + qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins =3D "gpio32", "gpio33"; function =3D "qup10"; }; =20 - qup_i2c9_data_clk: qup-i2c9-data-clk-pins { + qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins =3D "gpio36", "gpio37"; function =3D "qup11"; }; =20 - qup_i2c10_data_clk: qup-i2c10-data-clk-pins { + qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins =3D "gpio40", "gpio41"; function =3D "qup12"; }; =20 - qup_i2c11_data_clk: qup-i2c11-data-clk-pins { + qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins =3D "gpio44", "gpio45"; function =3D "qup13"; }; =20 - qup_i2c12_data_clk: qup-i2c12-data-clk-pins { + qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins =3D "gpio48", "gpio49"; function =3D "qup14"; }; =20 - qup_i2c13_data_clk: qup-i2c13-data-clk-pins { + qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins =3D "gpio52", "gpio53"; function =3D "qup15"; }; =20 - qup_i2c14_data_clk: qup-i2c14-data-clk-pins { + qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins =3D "gpio56", "gpio57"; function =3D "qup16"; }; =20 - qup_i2c15_data_clk: qup-i2c15-data-clk-pins { + qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins =3D "gpio60", "gpio61"; function =3D "qup17"; }; =20 - qup_spi0_data_clk: qup-spi0-data-clk-pins { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins =3D "gpio0", "gpio1", "gpio2"; function =3D "qup00"; }; =20 - qup_spi0_cs: qup-spi0-cs-pins { + qup_spi0_cs: qup-spi0-cs-state { pins =3D "gpio3"; function =3D "qup00"; }; =20 - qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins =3D "gpio3"; function =3D "gpio"; }; =20 - qup_spi1_data_clk: qup-spi1-data-clk-pins { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins =3D "gpio4", "gpio5", "gpio6"; function =3D "qup01"; }; =20 - qup_spi1_cs: qup-spi1-cs-pins { + qup_spi1_cs: qup-spi1-cs-state { pins =3D "gpio7"; function =3D "qup01"; }; =20 - qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins =3D "gpio7"; function =3D "gpio"; }; =20 - qup_spi2_data_clk: qup-spi2-data-clk-pins { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins =3D "gpio8", "gpio9", "gpio10"; function =3D "qup02"; }; =20 - qup_spi2_cs: qup-spi2-cs-pins { + qup_spi2_cs: qup-spi2-cs-state { pins =3D "gpio11"; function =3D "qup02"; }; =20 - qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins =3D "gpio11"; function =3D "gpio"; }; =20 - qup_spi3_data_clk: qup-spi3-data-clk-pins { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins =3D "gpio12", "gpio13", "gpio14"; function =3D "qup03"; }; =20 - qup_spi3_cs: qup-spi3-cs-pins { + qup_spi3_cs: qup-spi3-cs-state { pins =3D "gpio15"; function =3D "qup03"; }; =20 - qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins =3D "gpio15"; function =3D "gpio"; }; =20 - qup_spi4_data_clk: qup-spi4-data-clk-pins { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins =3D "gpio16", "gpio17", "gpio18"; function =3D "qup04"; }; =20 - qup_spi4_cs: qup-spi4-cs-pins { + qup_spi4_cs: qup-spi4-cs-state { pins =3D "gpio19"; function =3D "qup04"; }; =20 - qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins =3D "gpio19"; function =3D "gpio"; }; =20 - qup_spi5_data_clk: qup-spi5-data-clk-pins { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins =3D "gpio20", "gpio21", "gpio22"; function =3D "qup05"; }; =20 - qup_spi5_cs: qup-spi5-cs-pins { + qup_spi5_cs: qup-spi5-cs-state { pins =3D "gpio23"; function =3D "qup05"; }; =20 - qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins =3D "gpio23"; function =3D "gpio"; }; =20 - qup_spi6_data_clk: qup-spi6-data-clk-pins { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins =3D "gpio24", "gpio25", "gpio26"; function =3D "qup06"; }; =20 - qup_spi6_cs: qup-spi6-cs-pins { + qup_spi6_cs: qup-spi6-cs-state { pins =3D "gpio27"; function =3D "qup06"; }; =20 - qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins =3D "gpio27"; function =3D "gpio"; }; =20 - qup_spi7_data_clk: qup-spi7-data-clk-pins { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins =3D "gpio28", "gpio29", "gpio30"; function =3D "qup07"; }; =20 - qup_spi7_cs: qup-spi7-cs-pins { + qup_spi7_cs: qup-spi7-cs-state { pins =3D "gpio31"; function =3D "qup07"; }; =20 - qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins =3D "gpio31"; function =3D "gpio"; }; =20 - qup_spi8_data_clk: qup-spi8-data-clk-pins { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins =3D "gpio32", "gpio33", "gpio34"; function =3D "qup10"; }; =20 - qup_spi8_cs: qup-spi8-cs-pins { + qup_spi8_cs: qup-spi8-cs-state { pins =3D "gpio35"; function =3D "qup10"; }; =20 - qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins =3D "gpio35"; function =3D "gpio"; }; =20 - qup_spi9_data_clk: qup-spi9-data-clk-pins { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins =3D "gpio36", "gpio37", "gpio38"; function =3D "qup11"; }; =20 - qup_spi9_cs: qup-spi9-cs-pins { + qup_spi9_cs: qup-spi9-cs-state { pins =3D "gpio39"; function =3D "qup11"; }; =20 - qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins =3D "gpio39"; function =3D "gpio"; }; =20 - qup_spi10_data_clk: qup-spi10-data-clk-pins { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins =3D "gpio40", "gpio41", "gpio42"; function =3D "qup12"; }; =20 - qup_spi10_cs: qup-spi10-cs-pins { + qup_spi10_cs: qup-spi10-cs-state { pins =3D "gpio43"; function =3D "qup12"; }; =20 - qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins =3D "gpio43"; function =3D "gpio"; }; =20 - qup_spi11_data_clk: qup-spi11-data-clk-pins { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins =3D "gpio44", "gpio45", "gpio46"; function =3D "qup13"; }; =20 - qup_spi11_cs: qup-spi11-cs-pins { + qup_spi11_cs: qup-spi11-cs-state { pins =3D "gpio47"; function =3D "qup13"; }; =20 - qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins =3D "gpio47"; function =3D "gpio"; }; =20 - qup_spi12_data_clk: qup-spi12-data-clk-pins { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins =3D "gpio48", "gpio49", "gpio50"; function =3D "qup14"; }; =20 - qup_spi12_cs: qup-spi12-cs-pins { + qup_spi12_cs: qup-spi12-cs-state { pins =3D "gpio51"; function =3D "qup14"; }; =20 - qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins =3D "gpio51"; function =3D "gpio"; }; =20 - qup_spi13_data_clk: qup-spi13-data-clk-pins { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins =3D "gpio52", "gpio53", "gpio54"; function =3D "qup15"; }; =20 - qup_spi13_cs: qup-spi13-cs-pins { + qup_spi13_cs: qup-spi13-cs-state { pins =3D "gpio55"; function =3D "qup15"; }; =20 - qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins =3D "gpio55"; function =3D "gpio"; }; =20 - qup_spi14_data_clk: qup-spi14-data-clk-pins { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins =3D "gpio56", "gpio57", "gpio58"; function =3D "qup16"; }; =20 - qup_spi14_cs: qup-spi14-cs-pins { + qup_spi14_cs: qup-spi14-cs-state { pins =3D "gpio59"; function =3D "qup16"; }; =20 - qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins =3D "gpio59"; function =3D "gpio"; }; =20 - qup_spi15_data_clk: qup-spi15-data-clk-pins { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins =3D "gpio60", "gpio61", "gpio62"; function =3D "qup17"; }; =20 - qup_spi15_cs: qup-spi15-cs-pins { + qup_spi15_cs: qup-spi15-cs-state { pins =3D "gpio63"; function =3D "qup17"; }; =20 - qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins =3D "gpio63"; function =3D "gpio"; }; =20 - qup_uart0_cts: qup-uart0-cts-pins { + qup_uart0_cts: qup-uart0-cts-state { pins =3D "gpio0"; function =3D "qup00"; }; =20 - qup_uart0_rts: qup-uart0-rts-pins { + qup_uart0_rts: qup-uart0-rts-state { pins =3D "gpio1"; function =3D "qup00"; }; =20 - qup_uart0_tx: qup-uart0-tx-pins { + qup_uart0_tx: qup-uart0-tx-state { pins =3D "gpio2"; function =3D "qup00"; }; =20 - qup_uart0_rx: qup-uart0-rx-pins { + qup_uart0_rx: qup-uart0-rx-state { pins =3D "gpio3"; function =3D "qup00"; }; =20 - qup_uart1_cts: qup-uart1-cts-pins { + qup_uart1_cts: qup-uart1-cts-state { pins =3D "gpio4"; function =3D "qup01"; }; =20 - qup_uart1_rts: qup-uart1-rts-pins { + qup_uart1_rts: qup-uart1-rts-state { pins =3D "gpio5"; function =3D "qup01"; }; =20 - qup_uart1_tx: qup-uart1-tx-pins { + qup_uart1_tx: qup-uart1-tx-state { pins =3D "gpio6"; function =3D "qup01"; }; =20 - qup_uart1_rx: qup-uart1-rx-pins { + qup_uart1_rx: qup-uart1-rx-state { pins =3D "gpio7"; function =3D "qup01"; }; =20 - qup_uart2_cts: qup-uart2-cts-pins { + qup_uart2_cts: qup-uart2-cts-state { pins =3D "gpio8"; function =3D "qup02"; }; =20 - qup_uart2_rts: qup-uart2-rts-pins { + qup_uart2_rts: qup-uart2-rts-state { pins =3D "gpio9"; function =3D "qup02"; }; =20 - qup_uart2_tx: qup-uart2-tx-pins { + qup_uart2_tx: qup-uart2-tx-state { pins =3D "gpio10"; function =3D "qup02"; }; =20 - qup_uart2_rx: qup-uart2-rx-pins { + qup_uart2_rx: qup-uart2-rx-state { pins =3D "gpio11"; function =3D "qup02"; }; =20 - qup_uart3_cts: qup-uart3-cts-pins { + qup_uart3_cts: qup-uart3-cts-state { pins =3D "gpio12"; function =3D "qup03"; }; =20 - qup_uart3_rts: qup-uart3-rts-pins { + qup_uart3_rts: qup-uart3-rts-state { pins =3D "gpio13"; function =3D "qup03"; }; =20 - qup_uart3_tx: qup-uart3-tx-pins { + qup_uart3_tx: qup-uart3-tx-state { pins =3D "gpio14"; function =3D "qup03"; }; =20 - qup_uart3_rx: qup-uart3-rx-pins { + qup_uart3_rx: qup-uart3-rx-state { pins =3D "gpio15"; function =3D "qup03"; }; =20 - qup_uart4_cts: qup-uart4-cts-pins { + qup_uart4_cts: qup-uart4-cts-state { pins =3D "gpio16"; function =3D "qup04"; }; =20 - qup_uart4_rts: qup-uart4-rts-pins { + qup_uart4_rts: qup-uart4-rts-state { pins =3D "gpio17"; function =3D "qup04"; }; =20 - qup_uart4_tx: qup-uart4-tx-pins { + qup_uart4_tx: qup-uart4-tx-state { pins =3D "gpio18"; function =3D "qup04"; }; =20 - qup_uart4_rx: qup-uart4-rx-pins { + qup_uart4_rx: qup-uart4-rx-state { pins =3D "gpio19"; function =3D "qup04"; }; =20 - qup_uart5_cts: qup-uart5-cts-pins { + qup_uart5_cts: qup-uart5-cts-state { pins =3D "gpio20"; function =3D "qup05"; }; =20 - qup_uart5_rts: qup-uart5-rts-pins { + qup_uart5_rts: qup-uart5-rts-state { pins =3D "gpio21"; function =3D "qup05"; }; =20 - qup_uart5_tx: qup-uart5-tx-pins { + qup_uart5_tx: qup-uart5-tx-state { pins =3D "gpio22"; function =3D "qup05"; }; =20 - qup_uart5_rx: qup-uart5-rx-pins { + qup_uart5_rx: qup-uart5-rx-state { pins =3D "gpio23"; function =3D "qup05"; }; =20 - qup_uart6_cts: qup-uart6-cts-pins { + qup_uart6_cts: qup-uart6-cts-state { pins =3D "gpio24"; function =3D "qup06"; }; =20 - qup_uart6_rts: qup-uart6-rts-pins { + qup_uart6_rts: qup-uart6-rts-state { pins =3D "gpio25"; function =3D "qup06"; }; =20 - qup_uart6_tx: qup-uart6-tx-pins { + qup_uart6_tx: qup-uart6-tx-state { pins =3D "gpio26"; function =3D "qup06"; }; =20 - qup_uart6_rx: qup-uart6-rx-pins { + qup_uart6_rx: qup-uart6-rx-state { pins =3D "gpio27"; function =3D "qup06"; }; =20 - qup_uart7_cts: qup-uart7-cts-pins { + qup_uart7_cts: qup-uart7-cts-state { pins =3D "gpio28"; function =3D "qup07"; }; =20 - qup_uart7_rts: qup-uart7-rts-pins { + qup_uart7_rts: qup-uart7-rts-state { pins =3D "gpio29"; function =3D "qup07"; }; =20 - qup_uart7_tx: qup-uart7-tx-pins { + qup_uart7_tx: qup-uart7-tx-state { pins =3D "gpio30"; function =3D "qup07"; }; =20 - qup_uart7_rx: qup-uart7-rx-pins { + qup_uart7_rx: qup-uart7-rx-state { pins =3D "gpio31"; function =3D "qup07"; }; =20 - qup_uart8_cts: qup-uart8-cts-pins { + qup_uart8_cts: qup-uart8-cts-state { pins =3D "gpio32"; function =3D "qup10"; }; =20 - qup_uart8_rts: qup-uart8-rts-pins { + qup_uart8_rts: qup-uart8-rts-state { pins =3D "gpio33"; function =3D "qup10"; }; =20 - qup_uart8_tx: qup-uart8-tx-pins { + qup_uart8_tx: qup-uart8-tx-state { pins =3D "gpio34"; function =3D "qup10"; }; =20 - qup_uart8_rx: qup-uart8-rx-pins { + qup_uart8_rx: qup-uart8-rx-state { pins =3D "gpio35"; function =3D "qup10"; }; =20 - qup_uart9_cts: qup-uart9-cts-pins { + qup_uart9_cts: qup-uart9-cts-state { pins =3D "gpio36"; function =3D "qup11"; }; =20 - qup_uart9_rts: qup-uart9-rts-pins { + qup_uart9_rts: qup-uart9-rts-state { pins =3D "gpio37"; function =3D "qup11"; }; =20 - qup_uart9_tx: qup-uart9-tx-pins { + qup_uart9_tx: qup-uart9-tx-state { pins =3D "gpio38"; function =3D "qup11"; }; =20 - qup_uart9_rx: qup-uart9-rx-pins { + qup_uart9_rx: qup-uart9-rx-state { pins =3D "gpio39"; function =3D "qup11"; }; =20 - qup_uart10_cts: qup-uart10-cts-pins { + qup_uart10_cts: qup-uart10-cts-state { pins =3D "gpio40"; function =3D "qup12"; }; =20 - qup_uart10_rts: qup-uart10-rts-pins { + qup_uart10_rts: qup-uart10-rts-state { pins =3D "gpio41"; function =3D "qup12"; }; =20 - qup_uart10_tx: qup-uart10-tx-pins { + qup_uart10_tx: qup-uart10-tx-state { pins =3D "gpio42"; function =3D "qup12"; }; =20 - qup_uart10_rx: qup-uart10-rx-pins { + qup_uart10_rx: qup-uart10-rx-state { pins =3D "gpio43"; function =3D "qup12"; }; =20 - qup_uart11_cts: qup-uart11-cts-pins { + qup_uart11_cts: qup-uart11-cts-state { pins =3D "gpio44"; function =3D "qup13"; }; =20 - qup_uart11_rts: qup-uart11-rts-pins { + qup_uart11_rts: qup-uart11-rts-state { pins =3D "gpio45"; function =3D "qup13"; }; =20 - qup_uart11_tx: qup-uart11-tx-pins { + qup_uart11_tx: qup-uart11-tx-state { pins =3D "gpio46"; function =3D "qup13"; }; =20 - qup_uart11_rx: qup-uart11-rx-pins { + qup_uart11_rx: qup-uart11-rx-state { pins =3D "gpio47"; function =3D "qup13"; }; =20 - qup_uart12_cts: qup-uart12-cts-pins { + qup_uart12_cts: qup-uart12-cts-state { pins =3D "gpio48"; function =3D "qup14"; }; =20 - qup_uart12_rts: qup-uart12-rts-pins { + qup_uart12_rts: qup-uart12-rts-state { pins =3D "gpio49"; function =3D "qup14"; }; =20 - qup_uart12_tx: qup-uart12-tx-pins { + qup_uart12_tx: qup-uart12-tx-state { pins =3D "gpio50"; function =3D "qup14"; }; =20 - qup_uart12_rx: qup-uart12-rx-pins { + qup_uart12_rx: qup-uart12-rx-state { pins =3D "gpio51"; function =3D "qup14"; }; =20 - qup_uart13_cts: qup-uart13-cts-pins { + qup_uart13_cts: qup-uart13-cts-state { pins =3D "gpio52"; function =3D "qup15"; }; =20 - qup_uart13_rts: qup-uart13-rts-pins { + qup_uart13_rts: qup-uart13-rts-state { pins =3D "gpio53"; function =3D "qup15"; }; =20 - qup_uart13_tx: qup-uart13-tx-pins { + qup_uart13_tx: qup-uart13-tx-state { pins =3D "gpio54"; function =3D "qup15"; }; =20 - qup_uart13_rx: qup-uart13-rx-pins { + qup_uart13_rx: qup-uart13-rx-state { pins =3D "gpio55"; function =3D "qup15"; }; =20 - qup_uart14_cts: qup-uart14-cts-pins { + qup_uart14_cts: qup-uart14-cts-state { pins =3D "gpio56"; function =3D "qup16"; }; =20 - qup_uart14_rts: qup-uart14-rts-pins { + qup_uart14_rts: qup-uart14-rts-state { pins =3D "gpio57"; function =3D "qup16"; }; =20 - qup_uart14_tx: qup-uart14-tx-pins { + qup_uart14_tx: qup-uart14-tx-state { pins =3D "gpio58"; function =3D "qup16"; }; =20 - qup_uart14_rx: qup-uart14-rx-pins { + qup_uart14_rx: qup-uart14-rx-state { pins =3D "gpio59"; function =3D "qup16"; }; =20 - qup_uart15_cts: qup-uart15-cts-pins { + qup_uart15_cts: qup-uart15-cts-state { pins =3D "gpio60"; function =3D "qup17"; }; =20 - qup_uart15_rts: qup-uart15-rts-pins { + qup_uart15_rts: qup-uart15-rts-state { pins =3D "gpio61"; function =3D "qup17"; }; =20 - qup_uart15_tx: qup-uart15-tx-pins { + qup_uart15_tx: qup-uart15-tx-state { pins =3D "gpio62"; function =3D "qup17"; }; =20 - qup_uart15_rx: qup-uart15-rx-pins { + qup_uart15_rx: qup-uart15-rx-state { pins =3D "gpio63"; function =3D "qup17"; }; =20 - sdc1_clk: sdc1-clk-pins { + sdc1_clk: sdc1-clk-state { pins =3D "sdc1_clk"; }; =20 - sdc1_cmd: sdc1-cmd-pins { + sdc1_cmd: sdc1-cmd-state { pins =3D "sdc1_cmd"; }; =20 - sdc1_data: sdc1-data-pins { + sdc1_data: sdc1-data-state { pins =3D "sdc1_data"; }; =20 - sdc1_rclk: sdc1-rclk-pins { + sdc1_rclk: sdc1-rclk-state { pins =3D "sdc1_rclk"; }; =20 - sdc1_clk_sleep: sdc1-clk-sleep-pins { + sdc1_clk_sleep: sdc1-clk-sleep-state { pins =3D "sdc1_clk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_cmd_sleep: sdc1-cmd-sleep-pins { + sdc1_cmd_sleep: sdc1-cmd-sleep-state { pins =3D "sdc1_cmd"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_data_sleep: sdc1-data-sleep-pins { + sdc1_data_sleep: sdc1-data-sleep-state { pins =3D "sdc1_data"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_rclk_sleep: sdc1-rclk-sleep-pins { + sdc1_rclk_sleep: sdc1-rclk-sleep-state { pins =3D "sdc1_rclk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_clk: sdc2-clk-pins { + sdc2_clk: sdc2-clk-state { pins =3D "sdc2_clk"; }; =20 - sdc2_cmd: sdc2-cmd-pins { + sdc2_cmd: sdc2-cmd-state { pins =3D "sdc2_cmd"; }; =20 - sdc2_data: sdc2-data-pins { + sdc2_data: sdc2-data-state { pins =3D "sdc2_data"; }; =20 - sdc2_clk_sleep: sdc2-clk-sleep-pins { + sdc2_clk_sleep: sdc2-clk-sleep-state { pins =3D "sdc2_clk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_cmd_sleep: sdc2-cmd-sleep-pins { + sdc2_cmd_sleep: sdc2-cmd-sleep-state { pins =3D "sdc2_cmd"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_data_sleep: sdc2-data-sleep-pins { + sdc2_data_sleep: sdc2-data-sleep-state { pins =3D "sdc2_data"; drive-strength =3D <2>; bias-bus-hold; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1BFCC433FE for ; Fri, 30 Sep 2022 19:30:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbiI3Tah (ORCPT ); Fri, 30 Sep 2022 15:30:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231767AbiI3TaS (ORCPT ); Fri, 30 Sep 2022 15:30:18 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4F952DA94 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:02 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 05/16] arm64: dts: qcom: sc7280-herobrine: correct number of gpio-line-names Date: Fri, 30 Sep 2022 21:29:43 +0200 Message-Id: <20220930192954.242546-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are 175 GPIOs (gpio0-174). Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64= /boot/dts/qcom/sc7280-herobrine-crd.dts index f0f26af1e421..4e0b013e25f4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -372,5 +372,6 @@ &tlmm { "", /* 170 */ "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", + "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch= /arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts index ccbe50b6249a..739e81bd6d68 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts @@ -328,6 +328,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index c1a671968725..c8ff13db30b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -358,6 +358,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch= /arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 4566722bf4dd..3dff610fb946 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -321,6 +321,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD30C433FE for ; Fri, 30 Sep 2022 19:30:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232252AbiI3Tat (ORCPT ); Fri, 30 Sep 2022 15:30:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231852AbiI3TaS (ORCPT ); Fri, 30 Sep 2022 15:30:18 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 130D42DAB4 for ; Fri, 30 Sep 2022 12:30:05 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id bs18so4226516ljb.1 for ; Fri, 30 Sep 2022 12:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=TyDtIBZ/b6jNbw8Fg/X93utCMqZp3mIZumdRr4BC1ys=; b=PxZNFQb6tRWIVB/oh/y+mkO956MqsAvFKZJSaNafXM7ZaAeXdlfLDnVI+Wf8znmuQe baDF0HnsOo5olni9dS6qBQGCulmoAmCiDYZYl+40eMIRq+0pE5PXC4OzWaLzFdI/Y4oM 9UNArVSAd47LkePD5909ajFznKFX78/QQggwYKu5u3DIwHem8zbqlFAcjZZDzeECuSTm 5ESfv8DbJxzgTd0C84KIyN7YpyjThLyyShPz4Qu8bCbzP6ckMRA6YmtOx3oHrNkNeBWv 8tUIMLqXtlDjSu4+MgV/XhzXoPZrpe/b3BDbk8KMJRr+/qXMN0PQOcx9dVYWTts7NIhx /FJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=TyDtIBZ/b6jNbw8Fg/X93utCMqZp3mIZumdRr4BC1ys=; b=oNku8UTCth5Ss1vy7I+tCuz/30X+0e3p6xEFOWF9PChUoNNGIKvFwy9uVydP+z4K8d buhQpEUOM5upkM9dxeKPuULHA6Bi0V8MVNZM/NXXsIesf3XEFjBs0a1qNqfNT9M5ib6G ZoTie7apdU2WEyplZShsRo52abKzZsXHdYZF9ZHZ8b8z5o++lM7ZaHtOtifN/wczHE0S ZQQ2l+dzmgGnYpqIwpdzVaHdr9Qgr/vOzRGgdxN0CyBZJr4kMyLuSi2795ZrvDARAago flKAMpgKehLruL842b7OVO8cyQ6mrtcqbP4oCoj/kMNH4QnR9iIMpY3Kdqu+O7eUOqfT bjgA== X-Gm-Message-State: ACrzQf1GYksMlfocl06jEVgmPXHra+4oPSm2zGUh/6rd3cPr+RUZCLzh AbnGj/Rz16EYijlJfXb9+ya2/Q== X-Google-Smtp-Source: AMsMyM4UxTw00TXiFkFvZOhxBgpeuK2v7ANJB3EVXClVqbCtymSg02pRTD98y0DpEr9uVxMvviZ8YA== X-Received: by 2002:a2e:5d0:0:b0:26a:9a2d:ca90 with SMTP id 199-20020a2e05d0000000b0026a9a2dca90mr3032480ljf.102.1664566203545; Fri, 30 Sep 2022 12:30:03 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:03 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 06/16] arm64: dts: qcom: sc7280-idp-ec-h1: add missing QUP GPIO functions Date: Fri, 30 Sep 2022 21:29:44 +0200 Message-Id: <20220930192954.242546-7-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add default GPIO function to SPI10 and SPI14 chip-select pins on SC7280 IDP, as required by bindings. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index b35f3738933c..3cfeb118d379 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -95,11 +95,13 @@ h1_ap_int_odl: h1-ap-int-odl-state { =20 qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; + function =3D "gpio"; output-high; }; =20 qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins =3D "gpio59"; + function =3D "gpio"; output-high; }; }; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BB26C433FE for ; Fri, 30 Sep 2022 19:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232271AbiI3Taz (ORCPT ); Fri, 30 Sep 2022 15:30:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232001AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0F38ED for ; Fri, 30 Sep 2022 12:30:07 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id l12so5800558ljg.9 for ; Fri, 30 Sep 2022 12:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=1+tNRNTlMKDtrm8kNyG1z3UONnnvb9QDoC8vEjCWfXA=; b=ziX2cDg/+56emJPn3ne2OaAE7ELJINd7gRNkn7Bsp94M4+uBAiYpAygQhy2d6XRIqR kFxihyuAHCi6++EqobihsEPe87AdgcvCelXEVq80gOvKkf4jiL5uuxLXiTb+5QEvsHQo 6JQTorQF9j0PFLVrCuCJlPOe0rk85L2LeUvXYdjMXWsh2IZuww3qG16iSJM+aE41G0Rc JkeX17qsYqWlckDpQtkAInwc3nRARCIiLntk1lGgPHqCc9+o9Cb4QImQqLOnQhOoqsyl gdh1kgWL6RDxzJyluqyhEvdRGB5+yh1E+UnSUlJkb48a4MT+h5wbEs3Mvrpw6iI2o80X TuYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=1+tNRNTlMKDtrm8kNyG1z3UONnnvb9QDoC8vEjCWfXA=; b=DC3diwI1LxWZFE/OSFjxEd96G4wkuJr7R+vMsmSftVjiZZT53hOyhhBol8wx8auwT7 u0ki35Dp05gvSSo9SRP64cjVlGUyQo6699as9smUkwmS3EqDJ158/VdPKdtOW2Z6a908 JGyGNTcII1d4k0Y+BEu3ZtF3sY9WEWAW+usDCAqIJqyF+IDLjNMpiU/453J21mLzMu2p b9tjqJiKteR7DwEEStyQS/wdR9cyNIIPEL0eVY9SjCWqRudOkB/wOq0JDpkxJcemZ/QY 0Wtbo2pNnmV1qGw8Ym5N5m1zY+6VB+3GHEgV5On8fT5/iuuPKZzzFZomBPeND+8hhiVH UZ8w== X-Gm-Message-State: ACrzQf2m3YpWt06W5L7iewksCTYkKXSA6ZoAoq81iV5CSAtspcxx31WE sq55UdUeWkioGfGUCoP5IybuMQ== X-Google-Smtp-Source: AMsMyM5NKxJXIb8pfG8S+e30eY19GJLzCXfrqdI8ooMq/SCtmtqeLvPi4c6Hd5F4DWxwcMmmBzcN/Q== X-Received: by 2002:a05:651c:a08:b0:26c:539d:440a with SMTP id k8-20020a05651c0a0800b0026c539d440amr3144603ljq.264.1664566204648; Fri, 30 Sep 2022 12:30:04 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:04 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 07/16] arm64: dts: qcom: msm8953: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 21:29:45 +0200 Message-Id: <20220930192954.242546-8-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm632-fairphone-fp3.dtb: pinctrl@1000000: 'cd-off-pins', 'cd-on-pin= s', 'gpio-key-default-pins', .... do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 70 +++++++++++++-------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index 6b992a6d56c1..db94e6fd18f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -460,229 +460,229 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells =3D <2>; =20 - uart_console_active: uart-console-active-pins { + uart_console_active: uart-console-active-state { pins =3D "gpio4", "gpio5"; function =3D "blsp_uart2"; drive-strength =3D <2>; bias-disable; }; =20 - uart_console_sleep: uart-console-sleep-pins { + uart_console_sleep: uart-console-sleep-state { pins =3D "gpio4", "gpio5"; function =3D "blsp_uart2"; drive-strength =3D <2>; bias-pull-down; }; =20 - sdc1_clk_on: sdc1-clk-on-pins { + sdc1_clk_on: sdc1-clk-on-state { pins =3D "sdc1_clk"; bias-disable; drive-strength =3D <16>; }; =20 - sdc1_clk_off: sdc1-clk-off-pins { + sdc1_clk_off: sdc1-clk-off-state { pins =3D "sdc1_clk"; bias-disable; drive-strength =3D <2>; }; =20 - sdc1_cmd_on: sdc1-cmd-on-pins { + sdc1_cmd_on: sdc1-cmd-on-state { pins =3D "sdc1_cmd"; bias-disable; drive-strength =3D <10>; }; =20 - sdc1_cmd_off: sdc1-cmd-off-pins { + sdc1_cmd_off: sdc1-cmd-off-state { pins =3D "sdc1_cmd"; bias-disable; drive-strength =3D <2>; }; =20 - sdc1_data_on: sdc1-data-on-pins { + sdc1_data_on: sdc1-data-on-state { pins =3D "sdc1_data"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc1_data_off: sdc1-data-off-pins { + sdc1_data_off: sdc1-data-off-state { pins =3D "sdc1_data"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc1_rclk_on: sdc1-rclk-on-pins { + sdc1_rclk_on: sdc1-rclk-on-state { pins =3D "sdc1_rclk"; bias-pull-down; }; =20 - sdc1_rclk_off: sdc1-rclk-off-pins { + sdc1_rclk_off: sdc1-rclk-off-state { pins =3D "sdc1_rclk"; bias-pull-down; }; =20 - sdc2_clk_on: sdc2-clk-on-pins { + sdc2_clk_on: sdc2-clk-on-state { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - sdc2_clk_off: sdc2-clk-off-pins { + sdc2_clk_off: sdc2-clk-off-state { pins =3D "sdc2_clk"; bias-disable; drive-strength =3D <2>; }; =20 - sdc2_cmd_on: sdc2-cmd-on-pins { + sdc2_cmd_on: sdc2-cmd-on-state { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc2_cmd_off: sdc2-cmd-off-pins { + sdc2_cmd_off: sdc2-cmd-off-state { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc2_data_on: sdc2-data-on-pins { + sdc2_data_on: sdc2-data-on-state { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc2_data_off: sdc2-data-off-pins { + sdc2_data_off: sdc2-data-off-state { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc2_cd_on: cd-on-pins { + sdc2_cd_on: cd-on-state { pins =3D "gpio133"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; =20 - sdc2_cd_off: cd-off-pins { + sdc2_cd_off: cd-off-state { pins =3D "gpio133"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - gpio_key_default: gpio-key-default-pins { + gpio_key_default: gpio-key-default-state { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; =20 - i2c_1_default: i2c-1-default-pins { + i2c_1_default: i2c-1-default-state { pins =3D "gpio2", "gpio3"; function =3D "blsp_i2c1"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_1_sleep: i2c-1-sleep-pins { + i2c_1_sleep: i2c-1-sleep-state { pins =3D "gpio2", "gpio3"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_2_default: i2c-2-default-pins { + i2c_2_default: i2c-2-default-state { pins =3D "gpio6", "gpio7"; function =3D "blsp_i2c2"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_2_sleep: i2c-2-sleep-pins { + i2c_2_sleep: i2c-2-sleep-state { pins =3D "gpio6", "gpio7"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_3_default: i2c-3-default-pins { + i2c_3_default: i2c-3-default-state { pins =3D "gpio10", "gpio11"; function =3D "blsp_i2c3"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_3_sleep: i2c-3-sleep-pins { + i2c_3_sleep: i2c-3-sleep-state { pins =3D "gpio10", "gpio11"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_4_default: i2c-4-default-pins { + i2c_4_default: i2c-4-default-state { pins =3D "gpio14", "gpio15"; function =3D "blsp_i2c4"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_4_sleep: i2c-4-sleep-pins { + i2c_4_sleep: i2c-4-sleep-state { pins =3D "gpio14", "gpio15"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_5_default: i2c-5-default-pins { + i2c_5_default: i2c-5-default-state { pins =3D "gpio18", "gpio19"; function =3D "blsp_i2c5"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_5_sleep: i2c-5-sleep-pins { + i2c_5_sleep: i2c-5-sleep-state { pins =3D "gpio18", "gpio19"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_6_default: i2c-6-default-pins { + i2c_6_default: i2c-6-default-state { pins =3D "gpio22", "gpio23"; function =3D "blsp_i2c6"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_6_sleep: i2c-6-sleep-pins { + i2c_6_sleep: i2c-6-sleep-state { pins =3D "gpio22", "gpio23"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_7_default: i2c-7-default-pins { + i2c_7_default: i2c-7-default-state { pins =3D "gpio135", "gpio136"; function =3D "blsp_i2c7"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_7_sleep: i2c-7-sleep-pins { + i2c_7_sleep: i2c-7-sleep-state { pins =3D "gpio135", "gpio136"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_8_default: i2c-8-default-pins { + i2c_8_default: i2c-8-default-state { pins =3D "gpio98", "gpio99"; function =3D "blsp_i2c8"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_8_sleep: i2c-8-sleep-pins { + i2c_8_sleep: i2c-8-sleep-state { pins =3D "gpio98", "gpio99"; function =3D "gpio"; drive-strength =3D <2>; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E3FAC433FE for ; Fri, 30 Sep 2022 19:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232313AbiI3TbB (ORCPT ); Fri, 30 Sep 2022 15:31:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232041AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C0152EF15 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:05 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 08/16] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 21:29:46 +0200 Message-Id: <20220930192954.242546-9-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm845-lg-judyln.dtb: gpios@c000: 'vol-up-active-pins' does not matc= h any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/bo= ot/dts/qcom/sdm845-lg-common.dtsi index 20f275f8694d..1eb423e4be24 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -604,7 +604,7 @@ pinconf { }; =20 &pm8998_gpio { - vol_up_pin_a: vol-up-active-pins { + vol_up_pin_a: vol-up-active-state { pins =3D "gpio6"; function =3D "normal"; input-enable; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E054C433FE for ; Fri, 30 Sep 2022 19:31:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231917AbiI3Tbd (ORCPT ); Fri, 30 Sep 2022 15:31:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232087AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C09131DDC for ; Fri, 30 Sep 2022 12:30:08 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id p5so5784258ljc.13 for ; Fri, 30 Sep 2022 12:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rQBh9mrZMQXa4Wxb/syFmouoGZGa2l4WN/58xgtqFuw=; b=tdxerNTbi/LoJQJG41IsuEg9ghPRZMjzMrKeqnpnPcy8Th9n0bwZekC1cAsVPgVYnr F2eGILN/Ldn+EaCsK+c0xbgdiIu+53TgSbxeJwCn3pphw+yyuxzC68/++nfFM3s+hqre 9zHhNNjKpJTJ/VqzQ0uE1wsDZc0XbuTO2o9g6MItoWdGyPF766aTXVqUHNr4tguBcymL 2U+OEGTk/bjPcEebKKiypFxlgUOmW7GLMUlTVUJ0m5IU19BRhv9OmxV+K1Hd5j+F63Qn ICD64TlgDZdFwmscXQZevlgjL8PSQrL+gaMHEF56S/Sf8HybNlcnsJTL9pydbXWrXD9h UKRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rQBh9mrZMQXa4Wxb/syFmouoGZGa2l4WN/58xgtqFuw=; b=Iu0UBgw3HYF2pXC4jbLMj31jdX57iSCzersPviUbT9UCGxhsCyFVjRsNc9wtnzdc4S ZdzuqqCeQUdAEy/ILXQSnlBobPY69iaKUbYBM4B4DiXeD3QL70fcjW1OXs8lQaIRPpKC LDenri7DvWSiMQNwdNWjuuOeGxCtEfzsCn4Wh7bEjE/F8531ygSRwtyHl2M5lhIm2E00 TsKiPgimPhCLRHUpauDc6RWsSuiEIX1Qd6dIDJGEVYX4WsGokoMhRTzJNhoV+Ojqb2K7 42UcpwwMQH/HMBC2bjwy+YN+F5hx/O/NfE8OnwDDONruNN3+9RWK3JZtRgdZYPuRjqHs eBig== X-Gm-Message-State: ACrzQf0XR7xVKI40uF4QLrFNd3rv87nbVJ2uEu4+4S7X4Xo+KaQIs9wk Lheyenq/EBmTFFjW27/F13nYFQ== X-Google-Smtp-Source: AMsMyM4ZxoXwchKyNuf0WX40+oHXmtG03nDufsx5D/QesjCFD+EFYs/PaoiXZFlKCaHSRlDCF9kQ/A== X-Received: by 2002:a2e:9d88:0:b0:26a:95c1:218f with SMTP id c8-20020a2e9d88000000b0026a95c1218fmr3266021ljj.223.1664566206637; Fri, 30 Sep 2022 12:30:06 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:06 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 09/16] arm64: dts: qcom: sm6125-sony-xperia: add missing SD CD GPIO functions Date: Fri, 30 Sep 2022 21:29:47 +0200 Message-Id: <20220930192954.242546-10-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add default GPIO function to SD card detect pins on SM6125 Sony Xperia, as required by bindings: qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: sdc2-off-state:= 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'cmd-pins', 'data-pins', 'sd-cd-pins' do not match any of t= he regexes: 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b= /arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 6a8b88cc4385..9af4b76fa6d7 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -89,6 +89,7 @@ &hsusb_phy1 { &sdc2_off_state { sd-cd-pins { pins =3D "gpio98"; + function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; @@ -97,6 +98,7 @@ sd-cd-pins { &sdc2_on_state { sd-cd-pins { pins =3D "gpio98"; + function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B082C4332F for ; Fri, 30 Sep 2022 19:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232354AbiI3Tb1 (ORCPT ); Fri, 30 Sep 2022 15:31:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232083AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 488E833422 for ; Fri, 30 Sep 2022 12:30:09 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id a14so5803337ljj.8 for ; Fri, 30 Sep 2022 12:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=otCIRU4GGd1lvww75mOgK5nY3xGQD+p6iPG3YaT4+2M=; b=XtOAuzmNgm+SzNKEsckn4knlTuEtBRCys11lnJHKgWJhxOWiYr9+g+QQhaBdy30o5Q EAe7hqxdvQL0PTc52lcYzo5HAzEakabfhEhziDKmkzxGDhXCh1SoewcKJRsrUGwgCO/q 1jPQGyKOLUh0JeRm4T8u4yGsV9dgt9B5S+vDZo3eM55m6aAUGJdwqBNWjwkBvQcbidF/ coXWjhtNoTvxZxqT9S9OolhXtt2fb8VqYr9el/Xth2JCY8jEdB3yW1ZBL5h44K9rm4q8 5StCDPABR63YgziV1WeKI2aYcLeP8kRSjqVZ0dhq8qRXsE75DGZxgXIOb/1cVwHD2zHK p96g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=otCIRU4GGd1lvww75mOgK5nY3xGQD+p6iPG3YaT4+2M=; b=TnFtWxHQuDOzGx1E/jyZgl7dW1/9Q2otryScf0wHEKDKbG3mdqWegyGpFaCRwxpFne 0V19by2/XL2XSINbvCVHqeUEOaEuODGdqh2fYo83ElOxF3AFKtX2SUDhKjSZz0n/PGfO 8nvuaVR7vpw8I3sFRWH59WB72Xu7ZwNeejqi8ILMKF3TIOmVTu9SuFiNHFlSRZSKOInW eJMzGzqLMp1uwjisfsqlVjngRZOkh2UbSurWHncbsnCQbzD/EEKdERHwsO+KYAmzPa97 lzRCy/i+xyoq5i/0w4Wbn0uqI221B+gWVzGAGuRgD93KHd9fqK/UntxkUdCHtxS9rDwk 3UrQ== X-Gm-Message-State: ACrzQf3BopsfCZDb4kjoy7HYVmKhaz2Nx73IDcpZTqhuxCHg3Lq1/Xsj +N3zT3XeSB4CCmZimOF0G0NlIA== X-Google-Smtp-Source: AMsMyM4BW7D1iCE6XYv6UXwJa93QmslOjdcD1E8Aki3+X5vx9i+UwRwcUvOk+tdp/ZstMu40K0xa+A== X-Received: by 2002:a2e:7817:0:b0:26c:3e9c:3465 with SMTP id t23-20020a2e7817000000b0026c3e9c3465mr3042669ljc.145.1664566207530; Fri, 30 Sep 2022 12:30:07 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:07 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 10/16] arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema Date: Fri, 30 Sep 2022 21:29:48 +0200 Message-Id: <20220930192954.242546-11-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 1fe3fa3ad877..af49a748e511 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -407,13 +407,13 @@ data-pins { }; =20 sdc2_on_state: sdc2-on-state { - clk { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd-pins-pins { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <10>; bias-pull-up; --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECB0C433FE for ; Fri, 30 Sep 2022 19:31:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232345AbiI3TbW (ORCPT ); Fri, 30 Sep 2022 15:31:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232060AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4864933373 for ; Fri, 30 Sep 2022 12:30:08 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id f21so1392440lfm.9 for ; Fri, 30 Sep 2022 12:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Q7Wt7NmwcU3io2xsT4q8AlyT1mkGLYVHtOHkxPZ8Qsg=; b=fHO+IsFFscYyGA6KsxL/3LYq1dgks7LmCSFGZLKQgEaYwpH13vAbf7dlPPvk0dQpSU s+luPjaTjFSRIP4MkEjbMSz84wvGGCVeudPdTLoC4zt73QFRx72cQzcGSuZPQO1AM2VK pziRQwHb8bwAnHullmH9WyUVknG+N3c9hqI8oLpH2uYMdQxWCR+7k56VHjl1H/ZqTqW4 wt6GOaL/hJX3XCqP5AGMU2xqg93vtQfxXj9v/UX9SaMiA2FKRFRzFVADKVVKBZOHTm9Y JADTWFT10QDgFNyO8vFCiiTT5rbhtgeo+KKChW82g8qH/W57RqFC6MOjVQSuDlXlCJLR hcTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Q7Wt7NmwcU3io2xsT4q8AlyT1mkGLYVHtOHkxPZ8Qsg=; b=eM3E8qk2fGftooI9Bwu73uVVmIYIyHXPj4Z2psJVx6Qqt7lvGcBRG32ZqsKZW1wBcv 1Img7SMWfhjSHoKJNr6wYb/YWPfLsuU8qjsKFxvbMDChUSiAT15NHoNRxvku8PC9MknQ hcKYW9yaTXhDpb2zqEvyHmoNRJQUSbe7yjvzIp9kr5NJagvcht6RrljjzkY6aMoVSi0d tqnwgtnaFACXwXVnMYznubOpNYaxhzdrTsYOgqoCwmVbrkJYdsWTRUL5ubW1KuARFNPW e7mm6M7B7383ugHQF+s3EC/SZAaJOLeiohlcoBhHrNOEIiRS37BvSoIcYU65rOLDGIs7 kqPA== X-Gm-Message-State: ACrzQf1lf50krUikIge5NxX700BcCj0TeZsbrELo7YaEiRuygjs4WdMG SQWIsFFycK0Q1y67ONGZZZVBTA== X-Google-Smtp-Source: AMsMyM5NisDMoIfxYBDmjkTtCz7/i3xeob65iCXd3elLnTRywcAJ7iq2YVvSzdBDjBbkW5zH/aX22w== X-Received: by 2002:a05:6512:4019:b0:4a2:f25:4214 with SMTP id br25-20020a056512401900b004a20f254214mr2214737lfb.94.1664566208412; Fri, 30 Sep 2022 12:30:08 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:08 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 11/16] dt-bindings: pinctrl: qcom,sm8250: add gpio-reserved-ranges and gpio-line-names Date: Fri, 30 Sep 2022 21:29:49 +0200 Message-Id: <20220930192954.242546-12-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document common GPIO properties (gpio-reserved-ranges and gpio-line-names), already used on qrb5165-rb5 board. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Konrad Dybcio Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index c44d02d28bc9..d7d8e5d3b659 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -49,6 +49,13 @@ properties: gpio-ranges: maxItems: 1 =20 + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 180 + wakeup-parent: true =20 #PIN CONFIGURATION NODES --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22AD6C433F5 for ; Fri, 30 Sep 2022 19:31:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232375AbiI3Tbi (ORCPT ); Fri, 30 Sep 2022 15:31:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230521AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 490EE36401 for ; Fri, 30 Sep 2022 12:30:10 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id f21so1392539lfm.9 for ; Fri, 30 Sep 2022 12:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=YcI0G2tvJ2eeBoXCl3/KWqeV9ihL9n5QFt8TDOVyV84=; b=MOuf7S1DiBaiESHsFZqhnaVlBQ9PCDhjzQFbeDmC4qvDCrVD0VW1BAVTPOiL6AQw3X qU/IeNa4425XAiBNAcBcQaHmHSXiC2JhIQjldwhT5adWqZFaskSEpYepoceSrDpgEw4S g5YxoUMqhHH1qPRkyQoSt/tgNg6eteICMUkTaidUoZxMa5bkALbtF+ZMkihMWciex+dh PPGsgeO++r39YLjrjuz7rYRCcTpey0C/LF3LFDLkiNAPcvNi9Sj0rRg7aKsUuYFd4DPN bZ+LV0eyGRK9aIqF9rAqMhlvwgXBG0t5l9jzXwRh9f6qQCRKi9Qv1AOWVVyvO3/0z2vD 4BRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=YcI0G2tvJ2eeBoXCl3/KWqeV9ihL9n5QFt8TDOVyV84=; b=SP10GjZrt0tCjhmg3u1JDqTYNznfSHAz/rtBcW28gisJoqVgF3Ua4RH4zmsy6xBxsg ambYGtiBB/QPJhp/DkUG+H9yDYO+kUoql+4y23BOKfaFfrRLV4yJC3U8PWxtBXwXkjKN 9fZ6byoh6/PiaAEOyXftLn83uAnDpBwWyvdCsnP/QfcYGeSLYko6INNT9eMpKBY6mkXl 2cNOAJglqJjuLxYcXIwnCTKEOIHzgYEtlRia7Hjq7ATldTe2sUxNypE2EKb736zdMOX6 ezyawz4h+KubQViNQtMkl83Ec+P7QmMqn3AcfGngKXyYcQkMhyzQgpQXDOnRB5SByCP9 1wOQ== X-Gm-Message-State: ACrzQf3BEklp3V8rq9WlK4T7IUVSPwUtmx9sUEDQcZopwhfxO0Qxf4JG jC4o8aTCqRGLRni7zxr6sVFIYSYWRvCsIA== X-Google-Smtp-Source: AMsMyM6JWXNaKmo9ITi8GfvgKGi5qyyVtQiC813vh+ypLgkIaOyuzoK/K2V2eZk1/Pbf7Ml+sk1zCw== X-Received: by 2002:a05:6512:239c:b0:497:938e:2c99 with SMTP id c28-20020a056512239c00b00497938e2c99mr3676715lfv.416.1664566209605; Fri, 30 Sep 2022 12:30:09 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:09 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 12/16] dt-bindings: pinctrl: qcom,sm8250: drop checks used in common TLMM Date: Fri, 30 Sep 2022 21:29:50 +0200 Message-Id: <20220930192954.242546-13-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The common Qualcomm TLMM pin controller schema brings already requirement of function for gpio pins. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index d7d8e5d3b659..021592b32904 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -64,6 +64,7 @@ patternProperties: if: type: object then: + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state properties: pins: description: @@ -118,16 +119,6 @@ patternProperties: required: - pins =20 - allOf: - - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - - if: - properties: - pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" - then: - required: - - function - additionalProperties: false =20 allOf: --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B3CC4321E for ; Fri, 30 Sep 2022 19:31:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232002AbiI3TbO (ORCPT ); Fri, 30 Sep 2022 15:31:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbiI3TaV (ORCPT ); Fri, 30 Sep 2022 15:30:21 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C9EA41D23 for ; Fri, 30 Sep 2022 12:30:11 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id q14so1600361lfo.11 for ; Fri, 30 Sep 2022 12:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=QQuJTHBAF+LytlsG9mBEaNV8uzLklN/f5fClzGBdurk=; b=vT3g3+MoY2XVkwcmZMfyPg1UrzUeyqL9YcqekiXZ2Fb4qYVEAlIDCk43K1qMe+oqz1 UhilEvqWkNcpN9l3Wf+gGwFpBZzSQt53iSWOk8yCxgOcQDF7dM/4S9bLqIhl6zVI5zsu /PbGls80vSFhVadRygCwtqVx2hN9i5rKbG++PHY20Me3lJOnPXjZ+QT0X+X8YwsmW252 YlN2T0ws9jzCAx96/Xot4nC4fr9y0p9GVaRTagJCwV2GV/XMysR0W3sXadQoDK8JH75k WrOJpamuoxAi6sZZQsR04lVvdAaBI72Pv7qHDV119p68xg2NqdUfp4bot844dctMe2S7 69Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=QQuJTHBAF+LytlsG9mBEaNV8uzLklN/f5fClzGBdurk=; b=oRs677wZYdyvno3CD8wUD84jVP5adeiU2PLdPwZVjOV6wn63grSH7RUdvfeHDOO/he 81vZx4g2bNrOgsxq2a7+slEJWQAnHt3mcaoY0z5mEJZcZaWewBJj0purI6oVb9YkKmES ka36e42VMdDzvDbWDopKOZFZ60WMs3KeZ5UlTO1K3nQDVn0wcLfWvLyiqEhvtKidHXHb JfEAaTJ0IXUyZp6SDwigt91hgeReeGNrIykyJOPBi2SiWV+JKe+uasxHPibAoenZvYLx zT7OLC5MyDBnoM34GPbGQ4Zo5w6EgzUTyRBgyu6Vx4kbVPuTLCJ9SjotlCLK/hP3eMw5 O+lA== X-Gm-Message-State: ACrzQf2IuIyHbArEHeTdQFoa3OByMPbINUjsyMTN7GzFyoGybBfNI+Y+ pIQbnNODPpFjUE8J/4YFfJTt/g== X-Google-Smtp-Source: AMsMyM6j8dUtqk8kFm4xOTV/VvdfWfMCzWtr5zTjONbotnJYi7EMTUBQPxho+ZO7BH+GLkpB6Ycedw== X-Received: by 2002:ac2:4f03:0:b0:496:e4:4d16 with SMTP id k3-20020ac24f03000000b0049600e44d16mr3601706lfr.250.1664566210530; Fri, 30 Sep 2022 12:30:10 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:10 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 13/16] dt-bindings: pinctrl: qcom,sm8250: fix matching pin config Date: Fri, 30 Sep 2022 21:29:51 +0200 Message-Id: <20220930192954.242546-14-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. The change causes indentation decrement, so the diff-hunk looks big, but there are no functional changes in the subnode "properties" section. The only difference there is removal of blank lines between common GPIO pinconf properties. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 128 +++++++++--------- 1 file changed, 67 insertions(+), 61 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 021592b32904..131eb8c981f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -58,68 +58,74 @@ properties: =20 wakeup-parent: true =20 -#PIN CONFIGURATION NODES patternProperties: - '^.*$': - if: - type: object - then: - $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state - properties: - pins: - description: - List of gpio pins affected by the properties specified in this - subnode. - items: - oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" - - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] - minItems: 1 - maxItems: 36 - - function: - description: - Specify the alternative function to be configured for the spec= ified - pins. - - enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_time= r4, cri_trng, - cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_p= xi1, - ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gc= c_gp3, gpio, - ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsyn= c0, - mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_d= ata1, - mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck= , mi2s1_ws, - mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, p= ci_e1, - pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll= _reset, - pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, = qspi2, qspi3, - qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup1= 3, qup14, - qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup= 5, qup6, - qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc4= 0, sdc41, - sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_= ch0, tgu_ch1, - tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, t= sif0_data, - tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data= , tsif1_en, - tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_tri= gger ] - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - required: - - pins - - additionalProperties: false + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8250-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8250-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8250-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4= , cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi= 1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_= gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_dat= a1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, = mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci= _e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_r= eset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qs= pi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13,= qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5,= qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40,= sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch= 0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsi= f0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, = tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigg= er ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false =20 allOf: - $ref: "pinctrl.yaml#" --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9FB0C433F5 for ; Fri, 30 Sep 2022 19:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232201AbiI3Tbk (ORCPT ); Fri, 30 Sep 2022 15:31:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232034AbiI3TaX (ORCPT ); Fri, 30 Sep 2022 15:30:23 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B5CC43E46 for ; Fri, 30 Sep 2022 12:30:12 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id j16so8350520lfg.1 for ; Fri, 30 Sep 2022 12:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=751HwE4ANyqWjgioMZDa/VolLenfO2h9E4PUsKTqmtg=; b=awR/urScDETz3u4YGsD0uUg68eGVaCmc6FPn96ThB0WgQvJ7xb90q7rev7rrC9b7az fvDuVfJPk/Rm5sIxlIgDRcIaJxCSY/CY90AIpQlS50YB71BYEYNPzL4kyYuuIiUAKfCv Qjl8t4F9IFCj6AfyLuia8aVBMH/Ed2O2m+n9gSrqqj0DqtZwnDZ3/hKTbTJWQfcIrxc3 hg3pDGHCATZMImDRLF/SknEDa7YajJYLhSbpZxnyk9bC6997wqe530hIMO5otmGpWcu/ AgP4fdcsUbOWzPA9joNuQrWfWr5C+TIxGbScoE8v+8pj0nhju/9jkCDSNVHCwPgWDAEq xaBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=751HwE4ANyqWjgioMZDa/VolLenfO2h9E4PUsKTqmtg=; b=YEZNFI6obL0ZHnkC8KTa8UY7Vp/1tuf3f33t6V76MkGZd52C5GKXb0Cogz4wJQgIBR 2OHceUKxaK4yaBjekAgy1Kyvgn7ZJXcncJHZGkvqz7sD0MVXBvjXo2W1Ozr6QVE+XloF 5aDj/JN1W0/X+w4ELMtN2HaMiBtzDCXVxyaB7OcUR9c/LraD4ATLBj83n5WB10/csSaw pW/cm8Ge5lX3IoVtzABZXMh2mdskFYhhiYPKFnRQ+Nh9D326xaI6h3LtoJRsDpMuQ6AU 3yXQnTHGCCeuABYSpIlwkcCQKMZSVhSF1yR9fWfsPvVv9+baOsxbN+HPYBwLq/9AolM6 BR2g== X-Gm-Message-State: ACrzQf3sOsfuYlxdbszsWmYUwJNu65zDZ2qZt9kYmDVdBJCGpVgl1OcC 7VYSL2ycdR/XxtbfsTzvgZAEAA== X-Google-Smtp-Source: AMsMyM4QdTw8Odc4fHUhM/j5GmrND335cYcD42VOQtqDPMCsgYBazwrdXR8mGAl7MBTzEWYGpb3FMQ== X-Received: by 2002:a05:6512:3d1a:b0:499:c00f:d95f with SMTP id d26-20020a0565123d1a00b00499c00fd95fmr3825857lfv.575.1664566211515; Fri, 30 Sep 2022 12:30:11 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:11 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 14/16] dt-bindings: pinctrl: qcom,sm8250: add input-enable Date: Fri, 30 Sep 2022 21:29:52 +0200 Message-Id: <20220930192954.242546-15-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SM8250 pinctrl driver supports input-enable and DTS already use it (sm8250-sony-xperia-edo-pdx203). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 131eb8c981f8..fb753fd8bbee 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -119,6 +119,7 @@ $defs: bias-pull-down: true bias-pull-up: true bias-disable: true + input-enable: true output-high: true output-low: true =20 --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A1BFC433FE for ; Fri, 30 Sep 2022 19:31:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232399AbiI3Tbp (ORCPT ); Fri, 30 Sep 2022 15:31:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbiI3TaX (ORCPT ); Fri, 30 Sep 2022 15:30:23 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B4614E855 for ; Fri, 30 Sep 2022 12:30:12 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 10so8353868lfy.5 for ; Fri, 30 Sep 2022 12:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=GJ8jipC4Qtr73OxvWkLL0z7JLAO3XeJVdGRbttk7Bns=; b=G4BUUDRW+DSCw6H3Wn4oPeCUI0IBwg2gOwF4G3pf7fa7wWlajEXipyqEfB9FDzrkQO jlOQUZcFTeyY2cp9FX8ecxsTVv9/VBcDy58YVi8xfULWls+tEau3jUGxm1FmoZg7y/fN The6u3iJKU+89Vdeo1UusPT2Lz87Vv1C0CktDVm/xXRmiYOIaNW2vW1VOcszM+NcnZTF eT6P8qxUd4MJAFDwy9vKRbBPxAnwuuHiaYhZmFu9TnvyP/359YxEEmKbv0RbIESIqRio JXmZqSAEP7UAJEY99D8ANlvVQI2JNc+ff3U8GSjNivFnsjYkBX/5eAsuvN78zrz7l86/ 36EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=GJ8jipC4Qtr73OxvWkLL0z7JLAO3XeJVdGRbttk7Bns=; b=4sEO7mwW/s3BuLf5STPzykjsZuuFbXCQK/I0YhuMRS1/+EzlsAuCaPBljtZsu/DyBr mHUULnW5kdD043gRge77vuNj2epo+30TQrSPgSu4fEy5Qcpjo71+opS75CYoaASDLnEa 71EqBZsriuyaWM0GVN6TrqoYfaKFMxX9EAW/sz6vDmUrKUFdtByYmp1XS+154JGmEDCW 1iIcYqgy0LYH08Xk6t8+7CTiuN+fGC/OCSGwB59/BqP7ypp19Utyau3zrlf6d9pXIouI 3H8xIzgYw3bHUHl6lqej2Jp9nm3sgSsCby4lt5i1zoDqwKn8/87vH7eE5cTVpwwB2OvD qsGg== X-Gm-Message-State: ACrzQf1hIaBcz5/5ziGiZbwzQJatB9LQaUWR4JnkP97UiDY9V8aNUXud 6flm/e9JtNhxaxZt1QNFH2+4Qw== X-Google-Smtp-Source: AMsMyM4R7zOCDF9Xyc9OFoEtSBu4ycGu636OKlKczAfxwUVAxT3xW89MZCOiTtzc9DgYRkhv6eaC4w== X-Received: by 2002:a05:6512:3d94:b0:49d:144c:9667 with SMTP id k20-20020a0565123d9400b0049d144c9667mr3839392lfv.50.1664566212429; Fri, 30 Sep 2022 12:30:12 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:12 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 15/16] dt-bindings: pinctrl: qcom,sc7280: add bias-bus-hold and input-enable Date: Fri, 30 Sep 2022 21:29:53 +0200 Message-Id: <20220930192954.242546-16-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SC7280 pinctrl driver supports bias-bus-hold and input-enable, and DTS already use it (sc7280-idp). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 4606ca980dc4..1db05c43d58c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -117,13 +117,11 @@ $defs: Selects the drive strength for the specified pins, in mA. =20 bias-pull-down: true - bias-pull-up: true - + bias-bus-hold: true bias-disable: true - + input-enable: true output-high: true - output-low: true =20 required: --=20 2.34.1 From nobody Sun May 5 16:26:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6254C433F5 for ; Fri, 30 Sep 2022 19:31:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbiI3Tbt (ORCPT ); Fri, 30 Sep 2022 15:31:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232183AbiI3TaZ (ORCPT ); Fri, 30 Sep 2022 15:30:25 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2A735050F for ; Fri, 30 Sep 2022 12:30:13 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id bs18so4226885ljb.1 for ; Fri, 30 Sep 2022 12:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=D4UikLTplWsHhZaUVls61V0/b6sUXu3Z8bQRTT/fioM=; b=DlDOTLmE/3K9A1fyyNvzhl65kiZ3T7Ie6Bil8zmwXlww+YoeawtfDqe4h1+lsSqJj0 FEvBVI5MQc0XGN480GaRmhbhBRMmX2O7WLGCSSKtct/PUc7DVIU+T7e69jFGKWG7IUB5 PfiPd919QmwqSTLoIq+fuHzINwZv+D1KEavJLUpsaqzrcAz0N+ETYyjB5wP8zjzYaYZq g9asxPEiXppHKFRp0uobCF5IhS8EV4qOA11XN/OGb2cKZd/OL4Bx8ToWbdWbrJtuC8OV hAovSOkPfp5WsOy1mM399GcELKeABSAGEzWijn0Jwc6MCkSSRWYM5vl85JXApmMSpYzw tRmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=D4UikLTplWsHhZaUVls61V0/b6sUXu3Z8bQRTT/fioM=; b=NODdVGGaDZPa3Avyex4nNAdGk+8BlO2lRdpR5LPmnFwq7lY6G2YzIEnAkUyhOdcTac w6Is4oCYDMD/+uAdUZ9iDxjA4sY0L0apmKxOD1YwS+DJYDuudXx42d4ukHeE94NdnwM+ osPE3q3LB9pko5L2ygWCpeo7QPO1cGzqulJ66O3+82YPl+QWtpNdcIym+QK3kV1x6WeQ IwmAtiNVZily6S7BJ9GbGWKkdq5E9zXNVo7hgI+p7wlyCxo2bPVn5fF6XNLSZhTalsid sRZRnXwQMFcJaY92uXaV7MJeGT+0Yu6BCdTrnzh15U/6HfLN3K9T/mbKFV9K1HqX5fZ+ Ka6Q== X-Gm-Message-State: ACrzQf1V8zAD+q8RrfWgeWnI5bSpWPQ6dj/sCg9YBp4ipxV2EyCzhkQk 7+6TdyGquIKPsdti/+NxZmdMiA== X-Google-Smtp-Source: AMsMyM57Ib5akcpmzoy0N5pqvXa9scToASPNmSaFb5mBPkLhQOljFXK5PJPbJIyANZcTWwPDHeLq5Q== X-Received: by 2002:a2e:8e8d:0:b0:26c:5d95:b31b with SMTP id z13-20020a2e8e8d000000b0026c5d95b31bmr3158920ljk.465.1664566213340; Fri, 30 Sep 2022 12:30:13 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id br32-20020a056512402000b0049f9799d349sm393603lfb.187.2022.09.30.12.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 12:30:13 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 16/16] dt-bindings: pinctrl: qcom,sc7280: correct number of GPIOs Date: Fri, 30 Sep 2022 21:29:54 +0200 Message-Id: <20220930192954.242546-17-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> References: <20220930192954.242546-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SC7280 has 175 GPIOs (gpio0-174), so correct size of gpio-line-names and narrow the pattern for matching pin names. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 1db05c43d58c..2a6b5a719d18 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -43,7 +43,7 @@ properties: maxItems: 1 =20 gpio-line-names: - maxItems: 174 + maxItems: 175 =20 wakeup-parent: true =20 @@ -70,7 +70,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] minItems: 1 @@ -132,7 +132,7 @@ $defs: - if: properties: pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" then: required: - function --=20 2.34.1