From nobody Tue Feb 10 04:02:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC5C2C433FE for ; Fri, 30 Sep 2022 16:07:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231924AbiI3QHL (ORCPT ); Fri, 30 Sep 2022 12:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231816AbiI3QGx (ORCPT ); Fri, 30 Sep 2022 12:06:53 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB9E01C2FB0 for ; Fri, 30 Sep 2022 09:06:50 -0700 (PDT) X-UUID: 30105a7576c3467ca5b9b827c83bca0c-20221001 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Yjl+Bzl2sRx8O3JnLZlmYNW0isbqNQocd4L3f9Rikao=; b=sSuU7RQMZdcwC22xUxMCOanqLbnIxdSfZ4RXhABLhj3cHDcV77xWtUFuXppKD47hgtlEddPxOt2A6v7HTOMRD+vYz3lrLbuSrv+s6YuLJ0+QnyyjEXpT6hcwfrm8I+sh7SdT4ZR7H+NsQXRKwhs35jbGSsC64zkWc/dMWK+vHCo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:f6b56217-985e-423a-8d3f-0ddbb119fe58,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.11,REQID:f6b56217-985e-423a-8d3f-0ddbb119fe58,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:39a5ff1,CLOUDID:d869a7a3-dc04-435c-b19b-71e131a5fc35,B ulkID:221001000644F3ISY5OD,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 30105a7576c3467ca5b9b827c83bca0c-20221001 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 76173501; Sat, 01 Oct 2022 00:06:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 1 Oct 2022 00:06:41 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 1 Oct 2022 00:06:40 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data Date: Sat, 1 Oct 2022 00:06:35 +0800 Message-ID: <20220930160638.7588-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930160638.7588-1-yongqiang.niu@mediatek.com> References: <20220930160638.7588-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. Signed-off-by: Yongqiang Niu --- drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 9465f9081515..88db6b4642db 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -38,6 +38,8 @@ #define CMDQ_THR_PRIORITY 0x40 =20 #define GCE_GCTL_VALUE 0x48 +#define GCE_CTRL_BY_SW GENMASK(2, 0) +#define GCE_DDR_EN GENMASK(18, 16) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -80,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -87,6 +90,7 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq) WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) writel(0x7, cmdq->base + GCE_GCTL_VALUE); + + if (cmdq->sw_ddr_en) + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr =3D plat_data->thread_nr; cmdq->shift_pa =3D plat_data->shift; cmdq->control_by_sw =3D plat_data->control_by_sw; + cmdq->sw_ddr_en =3D plat_data->sw_ddr_en; cmdq->gce_num =3D plat_data->gce_num; cmdq->irq_mask =3D GENMASK(cmdq->thread_nr - 1, 0); err =3D devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, --=20 2.25.1