From nobody Mon Feb 9 21:18:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38948C433F5 for ; Fri, 30 Sep 2022 14:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229566AbiI3OsX (ORCPT ); Fri, 30 Sep 2022 10:48:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231475AbiI3OsP (ORCPT ); Fri, 30 Sep 2022 10:48:15 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ECB512B5F0 for ; Fri, 30 Sep 2022 07:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664549291; x=1696085291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q72u8o9NplBRndRYgPTxCNaKqaPHER7MLnoX2dvImDc=; b=oG0O0rgiFJhRRDi+zl0ZYYInh+GH96gFtiBZNr2QZOPbdx2hZSfw8MMk nRsA/tf/8M1W8f79kvlbQkHPhzYmoZZHUir0+WQnAShqweVfwLpkJHa0V +a4tfdHD/SgiKTbr4cp2Z0h2m8fUWrNkCxRRBPCRgq4fAuu9vQS6DiiO7 U2+Sh+XCeZUnUYiU2nFUmjnHvrW6xzAZBE5NPF16ExKkF2Tkue6igI+7U JUNFiboUBXZAVEwKiyedTQHQN6FToe2LPf4oPrdI1a0iC4YE+OAK1zWE8 F+kAzC/uwiqydHNPQ4aVZahBu3MeDk9Jksq//4caMcaF8KX5oZKhQgyCD A==; X-IronPort-AV: E=McAfee;i="6500,9779,10486"; a="303116978" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="303116978" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 07:48:09 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10486"; a="691271767" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="691271767" Received: from herrerop-mobl1.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.38.128]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 07:48:04 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 33168104BD7; Fri, 30 Sep 2022 17:48:02 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv9 01/14] x86/mm: Fix CR3_ADDR_MASK Date: Fri, 30 Sep 2022 17:47:45 +0300 Message-Id: <20220930144758.30232-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930144758.30232-1-kirill.shutemov@linux.intel.com> References: <20220930144758.30232-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mask must not include bits above physical address mask. These bits are reserved and can be used for other things. Bits 61 and 62 are used for Linear Address Masking. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor-flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/= processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) =20 --=20 2.35.1