From nobody Sun May 5 09:32:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3658EC433F5 for ; Fri, 30 Sep 2022 13:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230042AbiI3NVD (ORCPT ); Fri, 30 Sep 2022 09:21:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230382AbiI3NUz (ORCPT ); Fri, 30 Sep 2022 09:20:55 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68ABE107599; Fri, 30 Sep 2022 06:20:53 -0700 (PDT) Received: (Authenticated sender: foss@0leil.net) by mail.gandi.net (Postfix) with ESMTPSA id 44FCC2000C; Fri, 30 Sep 2022 13:20:49 +0000 (UTC) From: Quentin Schulz Cc: linus.walleij@linaro.org, brgl@bgdev.pl, heiko@sntech.de, jay.xu@rock-chips.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, foss+kernel@0leil.net, Quentin Schulz , stable@vger.kernel.org Subject: [PATCH v2 1/2] pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback Date: Fri, 30 Sep 2022 15:20:32 +0200 Message-Id: <20220930132033.4003377-2-foss+kernel@0leil.net> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220930132033.4003377-1-foss+kernel@0leil.net> References: <20220930132033.4003377-1-foss+kernel@0leil.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Quentin Schulz Before the split of gpio and pinctrl sections in their own driver, rockchip_set_mux was called in pinmux_ops.gpio_set_direction for configuring a pin in its GPIO function. This is essential for cases where pinctrl is "bypassed" by gpio consumers otherwise the GPIO function is not configured for the pin and it does not work. Such was the case for the sysfs/libgpiod userspace GPIO handling. Let's re-implement the pinmux_ops.gpio_set_direction callback so that the gpio subsystem can request from the pinctrl driver to put the pin in its GPIO function. Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner Signed-off-by: Quentin Schulz --- v2: - added Reviewed-by, drivers/pinctrl/pinctrl-rockchip.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index 32e41395fc768..c84bd0e1ce5a6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2393,11 +2393,24 @@ static int rockchip_pmx_set(struct pinctrl_dev *pct= ldev, unsigned selector, return 0; } =20 +static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, + bool input) +{ + struct rockchip_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank; + + bank =3D pin_to_bank(info, offset); + return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); +} + static const struct pinmux_ops rockchip_pmx_ops =3D { .get_functions_count =3D rockchip_pmx_get_funcs_count, .get_function_name =3D rockchip_pmx_get_func_name, .get_function_groups =3D rockchip_pmx_get_groups, .set_mux =3D rockchip_pmx_set, + .gpio_set_direction =3D rockchip_pmx_gpio_set_direction, }; =20 /* --=20 2.37.3 From nobody Sun May 5 09:32:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13FC2C433FE for ; Fri, 30 Sep 2022 13:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231460AbiI3NVJ (ORCPT ); Fri, 30 Sep 2022 09:21:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230092AbiI3NU6 (ORCPT ); Fri, 30 Sep 2022 09:20:58 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49BA5A4B2E; Fri, 30 Sep 2022 06:20:56 -0700 (PDT) Received: (Authenticated sender: foss@0leil.net) by mail.gandi.net (Postfix) with ESMTPSA id 2CB0020005; Fri, 30 Sep 2022 13:20:51 +0000 (UTC) From: Quentin Schulz Cc: linus.walleij@linaro.org, brgl@bgdev.pl, heiko@sntech.de, jay.xu@rock-chips.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, foss+kernel@0leil.net, Quentin Schulz , stable@vger.kernel.org Subject: [PATCH v2 2/2] gpio: rockchip: request GPIO mux to pinctrl when setting direction Date: Fri, 30 Sep 2022 15:20:33 +0200 Message-Id: <20220930132033.4003377-3-foss+kernel@0leil.net> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220930132033.4003377-1-foss+kernel@0leil.net> References: <20220930132033.4003377-1-foss+kernel@0leil.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Quentin Schulz Before the split of gpio and pinctrl sections in their own driver, rockchip_set_mux was called in pinmux_ops.gpio_set_direction for configuring a pin in its GPIO function. This is essential for cases where pinctrl is "bypassed" by gpio consumers otherwise the GPIO function is not configured for the pin and it does not work. Such was the case for the sysfs/libgpiod userspace GPIO handling. Let's call pinctrl_gpio_direction_input/output when setting the direction of a GPIO so that the pinctrl core requests from the rockchip pinctrl driver to put the pin in its GPIO function. Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") Fixes: 936ee2675eee ("gpio/rockchip: add driver for rockchip gpio") Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner Signed-off-by: Quentin Schulz --- v2: - added Reviewed-by, - added missing linux/pinctrl/consumer.h header, drivers/gpio/gpio-rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index bb50335239ac8..9c976ad7208ef 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -156,6 +157,12 @@ static int rockchip_gpio_set_direction(struct gpio_chi= p *chip, unsigned long flags; u32 data =3D input ? 0 : 1; =20 + + if (input) + pinctrl_gpio_direction_input(bank->pin_base + offset); + else + pinctrl_gpio_direction_output(bank->pin_base + offset); + raw_spin_lock_irqsave(&bank->slock, flags); rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); raw_spin_unlock_irqrestore(&bank->slock, flags); --=20 2.37.3