From nobody Thu Mar 28 14:52:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1991C43219 for ; Fri, 30 Sep 2022 11:32:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231190AbiI3Lcb (ORCPT ); Fri, 30 Sep 2022 07:32:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231192AbiI3Lb7 (ORCPT ); Fri, 30 Sep 2022 07:31:59 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2172410052; Fri, 30 Sep 2022 04:22:44 -0700 (PDT) X-UUID: a3c8c5a75b834a91bae00170cbd3cee0-20220930 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yKadKMqPNiVt1qdvNK0BcoSiCFwoSH7wgM4CC5LxkZo=; b=B5cQmTwuj9QDCH6o16lHJjqYvi+aXq2x8vWQ1efQUQAOhsqF3eEPT+VojlwCcV7f8hQsz0yKmdaftsBd64GsAcjkpXMSEB62v0V7IgDppIpJPYKM5L7Rp5eWsgvqLr+Ya3sD5k06Lm6+hAU/E5UVfS8PCzgnxXHc3fZcMWlceGk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:16ff82c0-00cb-468e-8341-9ca48d2ec37a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:4bc4a2a3-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: a3c8c5a75b834a91bae00170cbd3cee0-20220930 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1905449710; Fri, 30 Sep 2022 19:22:43 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 30 Sep 2022 19:22:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 30 Sep 2022 19:22:41 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH v4 1/2] media: dt-bindings: mediatek: Rename child node names for decoder Date: Fri, 30 Sep 2022 19:22:36 +0800 Message-ID: <20220930112237.14411-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220930112237.14411-1-allen-kh.cheng@mediatek.com> References: <20220930112237.14411-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to make the names of the child nodes more generic, we rename "vcodec" to "video-codec" for decoder in patternProperties and example. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index c4f20acdc1f8..67fde48f991c 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -91,7 +91,7 @@ properties: =20 # Required child node: patternProperties: - '^vcodec-lat@[0-9a-f]+$': + '^video-codec-lat@[0-9a-f]+$': type: object =20 properties: @@ -145,7 +145,7 @@ patternProperties: =20 additionalProperties: false =20 - '^vcodec-core@[0-9a-f]+$': + '^video-codec-core@[0-9a-f]+$': type: object =20 properties: @@ -241,7 +241,7 @@ examples: #size-cells =3D <2>; ranges =3D <0 0 0 0x16000000 0 0x40000>; reg =3D <0 0x16000000 0 0x1000>; /* VDEC_SYS */ - vcodec-lat@10000 { + video-codec-lat@10000 { compatible =3D "mediatek,mtk-vcodec-lat"; reg =3D <0 0x10000 0 0x800>; interrupts =3D ; @@ -264,7 +264,7 @@ examples: power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; }; =20 - vcodec-core@25000 { + video-codec-core@25000 { compatible =3D "mediatek,mtk-vcodec-core"; reg =3D <0 0x25000 0 0x1000>; interrupts =3D ; --=20 2.18.0 From nobody Thu Mar 28 14:52:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F7A7C433F5 for ; Fri, 30 Sep 2022 11:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231604AbiI3Lcj (ORCPT ); Fri, 30 Sep 2022 07:32:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230156AbiI3Lb7 (ORCPT ); Fri, 30 Sep 2022 07:31:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D3B64B983; Fri, 30 Sep 2022 04:22:48 -0700 (PDT) X-UUID: 5ac2acc32b3a4c6f8c76e999caed4b03-20220930 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cfFnCcfi9XACmXya1wwpAWLUPh+LkXp5sDgaFWNvkHc=; b=BOBZ2AI9qhn8z83uaP7JIg0rJxr6XatTApeI92NLbkQHIj/0GplaVU+JnvNlvO6HH7sxxzGZffyeQQTe06tUvxSxL3emJyzPq9Kz5yH/HPaOebiib1EsnX7vyFT/uPMwiq/8cA7OP6/FZ2/nhxgZy+4zhkhDFfdR3T2fCxp51oo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:d0db3600-0666-4985-9445-cc75542b8221,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:869dc9e4-87f9-4bb0-97b6-34957dc0fbbe,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5ac2acc32b3a4c6f8c76e999caed4b03-20220930 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1784707299; Fri, 30 Sep 2022 19:22:44 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 30 Sep 2022 19:22:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 30 Sep 2022 19:22:42 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , Allen-KH Cheng Subject: [PATCH v4 2/2] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Fri, 30 Sep 2022 19:22:37 +0800 Message-ID: <20220930112237.14411-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220930112237.14411-1-allen-kh.cheng@mediatek.com> References: <20220930112237.14411-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 6b20376191a7..92a20f87468b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1449,6 +1449,66 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: video-codec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x16000000 0 0x26000>; + + video-codec-lat@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0x0 0x10000 0 0x800>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + video-codec-core@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0