From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA6A1C433FE for ; Fri, 30 Sep 2022 05:13:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230503AbiI3FN1 (ORCPT ); Fri, 30 Sep 2022 01:13:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230290AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AC7F154448; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=EpyJR1O+18IlesRb1sVxkR2L/tT+4AYzN+FinO47AbI=; b=ZdNxBDaGzRZRVvevF+crC2ukEH JM3+800dHLclZWsuDVo+v05NhK9QguDiTLB59afD19PT7dMm1T0wPHIx/mfIp5z+kPMm3may05vS8 9p0UJzWQLa+4tTejAMUeujLxydrvZDP/4yY7PxqEZZfAIwI8kuZxRGSEZ6zdXhPsqUN76ckGDZBBv vp32aSJGPRC9wjzkgcRtv5OzSH+1OsQQFrIBTvmVa/KcaYh1S+FlpAGhBU7qyF9xBiaxrURfiPjql tmM9ejBVWCXmLnOklaQnxnsITGvfpurDnxjNwjuvTBWS+NGdkthWnxvNVmUPIUjI3rOgFAD6BveZX qXoAEvNA==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kc-00Dje4-0V; Fri, 30 Sep 2022 07:13:02 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kb-001duJ-1d; Fri, 30 Sep 2022 07:13:01 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Krzysztof Kozlowski , Dan Johansen Subject: [PATCH v3 01/13] dt-bindings: rockchip: Add Hardkernel ODROID-M1 board Date: Fri, 30 Sep 2022 07:12:34 +0200 Message-Id: <20220930051246.391614-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dongjin Kim Add device tree binding for Hardkernel ODROID-M1 board based on RK3568 SoC. Signed-off-by: Dongjin Kim Signed-off-by: Aurelien Jarno Acked-by: Krzysztof Kozlowski Tested-by: Dan Johansen --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 7811ba64149c..a704d5389a82 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -432,6 +432,11 @@ properties: - const: hardkernel,rk3326-odroid-go2 - const: rockchip,rk3326 =20 + - description: Hardkernel Odroid M1 + items: + - const: rockchip,rk3568-odroid-m1 + - const: rockchip,rk3568 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6DD2C433F5 for ; Fri, 30 Sep 2022 05:13:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbiI3FNp (ORCPT ); Fri, 30 Sep 2022 01:13:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230344AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E0D8166487; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=tiqGXDT4YVEt8t1s8LR3Dy8OJjr3SkehHwupZs09YE4=; b=MgILfmSdmDH4jHxJMZPSPhhfCm /MwpHhdgHzzQiIMETqn0pz94IFFkUxfynJqwY3h23CsAMe9jEoM2Jlzhn4gc5YDCvlde8nGCMVkZR ILCAtnI0IrsP75c0RBkklm8xv3Xssti++s+Jn+0vhuPWd65oXQ62Hr9kEFm9Y1G1LJxgMXU7kmhua RMzF1ju+R1vYexNPgLhBf/If032zndpyVU7CBAD2WmEiCu02CvddYT8fLpReZHWT0FRFRpw3mCFiX stO3GAH0R6E7rqiTKbDqa/FxfUOgSt4kXesTthM6A0dcRdHH1FkFg9hgJ/aKeudx+dIVBs7f/pHVy a9vCzkZg==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kc-00Dje7-Lz; Fri, 30 Sep 2022 07:13:02 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kc-001duT-0Y; Fri, 30 Sep 2022 07:13:02 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 02/13] arm64: dts: rockchip: Add Hardkernel ODROID-M1 board Date: Fri, 30 Sep 2022 07:12:35 +0200 Message-Id: <20220930051246.391614-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dongjin Kim This patch is to add a device tree for new board Hardkernel ODROID-M1 based on Rockchip RK3568, includes basic peripherals - uart/eMMC/uSD/i2c and on-board ethernet. Signed-off-by: Dongjin Kim [aurelien@aurel32.net: addressed issues from initial review] Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 414 ++++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index ef79a672804a..c06fe8406c5b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -65,4 +65,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts new file mode 100644 index 000000000000..b3016437640b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model =3D "Hardkernel ODROID-M1"; + compatible =3D "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; + + aliases { + ethernet0 =3D &gmac0; + i2c0 =3D &i2c3; + i2c3 =3D &i2c0; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc0; + serial0 =3D &uart1; + serial1 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + leds { + compatible =3D "gpio-leds"; + + led_power: led-0 { + gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_POWER; + color =3D ; + default-state =3D "keep"; + linux,default-trigger =3D "default-on"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_power_pin>; + }; + led_work: led-1 { + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_HEARTBEAT; + color =3D ; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_work_pin>; + }; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks =3D <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents =3D <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + phy-mode =3D "rgmii"; + phy-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status =3D "okay"; + + tx_delay =3D <0x4f>; + rx_delay =3D <0x2d>; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int_l>; + rockchip,system-power-controller; + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + leds { + led_power_pin: led-power-pin { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_work_pin: led-work-pin { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstn= out>; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8D8FC43219 for ; Fri, 30 Sep 2022 05:13:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230080AbiI3FNO (ORCPT ); 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Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kc-00DjeO-VY; Fri, 30 Sep 2022 07:13:02 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kc-001dub-1T; Fri, 30 Sep 2022 07:13:02 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 03/13] arm64: dts: rockchip: add thermal support to ODROID-M1 Date: Fri, 30 Sep 2022 07:12:36 +0200 Message-Id: <20220930051246.391614-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the thermal nodes for the ODROID-M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index b3016437640b..112c65af3f55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -409,6 +409,12 @@ &sdmmc0 { status =3D "okay"; }; =20 +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + &uart2 { status =3D "okay"; }; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADC03C433FE for ; Fri, 30 Sep 2022 05:14:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230508AbiI3FOO (ORCPT ); Fri, 30 Sep 2022 01:14:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77E861664A9; Thu, 29 Sep 2022 22:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=CzlWQu3A1mClcSu8Q/+U0oU9SfnYjCXu1cD9OxHY0xA=; b=Pr99J+e7Xmh2eC7NtAyWjs9UyS V5p1C8QM9DSIzKalgw6gibz3OB97t3La6sxPtS4A6eMiJHN0gtxV2z23KWFVW2+dwUR0sqAgqCOo6 Dpu38kFowhi8NakcfbrxMcaGnKh+dbV39ZDRvzjn8N/4+KODMSQhUQfKAD6iEjzjd+EhmxRWEFoOD 2+c4eTc7AL+LniqUASXtlMSlNhUc04Uhuap3e5xUXBWZ0u2pSn9bRL85ln5KVxlXRv1R/qC70Blj/ lX8jOUvrRLOuBQ84G4adcmadHOddVUVes1ykokV5SFFrxyrY0MlDnQ8mA5NIT1F1PzjYliWQ9E/6f XQOXpZgQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kd-00DjeY-9F; Fri, 30 Sep 2022 07:13:03 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kc-001duk-2S; Fri, 30 Sep 2022 07:13:02 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v3 04/13] arm64: dts: rockchip: Add NOR flash to ODROID-M1 Date: Fri, 30 Sep 2022 07:12:37 +0200 Message-Id: <20220930051246.391614-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Rockchip Serial Flash Controller for the ODROID-M1 and add the corresponding SPI NOR flash entry. The SFC is used in dual I/O mode and not quad I/O mode, as the FSPI_D2 pin is shared with the EMMC_RSTn pin. The partitions addresses and sizes are taken from the ODROID-M1 Partition Table page on the ODROID wiki. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 112c65af3f55..94e839c9afab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -351,6 +351,20 @@ rgmii_phy0: ethernet-phy@0 { }; =20 &pinctrl { + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins =3D + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + leds { led_power_pin: led-power-pin { rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -409,6 +423,50 @@ &sdmmc0 { status =3D "okay"; }; =20 +&sfc { + /* Dual I/O mode as the D2 pin conflicts with the eMMC */ + pinctrl-0 =3D <&fspi_dual_io_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "SPL"; + reg =3D <0x0 0xe0000>; + }; + partition@e0000 { + label =3D "U-Boot Env"; + reg =3D <0xe0000 0x20000>; + }; + partition@100000 { + label =3D "U-Boot"; + reg =3D <0x100000 0x200000>; + }; + partition@300000 { + label =3D "splash"; + reg =3D <0x300000 0x100000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x400000 0xc00000>; + }; + }; + }; +}; + &tsadc { rockchip,hw-tshut-mode =3D <1>; rockchip,hw-tshut-polarity =3D <0>; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD0B4C433F5 for ; Fri, 30 Sep 2022 05:13:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230423AbiI3FNP (ORCPT ); Fri, 30 Sep 2022 01:13:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229663AbiI3FNL (ORCPT ); Fri, 30 Sep 2022 01:13:11 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AB7F153EFE; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=Gy+bXpplweq1n04UVQcDAT6V76lDFkLqQu4m9KSxUyU=; b=lbsi7XcqtSI0vDTttFZnZBgi5e 3AkjXTDn802NkWAvgDRT7eNAIMECmm/3HQDdvopXgHiwO4tocc3iGjV4AUDaNCxcONcuJaDjPJpQj JoZ2mrxqsLSZAkWu/bDDHnEjfo1H8ll3XgpBGDPYscY44eSpvRQ6YWkuy0qQNug24Hy+WuIp6kn2n 1J5gAFa1zz0F5xzyzoVGvF2Uai1ocgH0hRgd2j4qvpq2aL3LKFaNHyQ9bXg+KC2nyoAEO8aMu/ic5 PxGsI0HuFfUqDX2b9s0+Og4VNMjxh0GeAx/UYJReelMb+QAUm5Fkjm4pXG6FqK96YYuGuesZPurNN REUOieDw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kd-00Djei-Kn; Fri, 30 Sep 2022 07:13:03 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kd-001dut-0Q; Fri, 30 Sep 2022 07:13:03 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 05/13] arm64: dts: rockchip: Add analog audio on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:38 +0200 Message-Id: <20220930051246.391614-6-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the ODROID-M1, the I2S1 TDM controller is connected to the rk809 codec in I2S mode. It is used to provide a stereo headphones output and a mono speaker output. A GPIO with an external pullup is used as an headphone detection input. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 43 ++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 94e839c9afab..634c1bd80b4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -59,6 +59,31 @@ led_work: led-1 { }; }; =20 + rk809-sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_det_pin>; + simple-audio-card,name =3D "Analog RK817"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,hp-det-gpio =3D <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,widgets =3D + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing =3D + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai =3D <&rk809>; + }; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_sys"; @@ -131,10 +156,15 @@ rk809: pmic@20 { reg =3D <0x20>; interrupt-parent =3D <&gpio0>; interrupts =3D ; + assigned-clocks =3D <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents =3D <&cru CLK_I2S1_8CH_TX>; #clock-cells =3D <1>; + clock-names =3D "mclk"; + clocks =3D <&cru I2S1_MCLKOUT_TX>; pinctrl-names =3D "default"; - pinctrl-0 =3D <&pmic_int_l>; + pinctrl-0 =3D <&pmic_int_l>, <&i2s1m0_mclk>; rockchip,system-power-controller; + #sound-dai-cells =3D <0>; vcc1-supply =3D <&vcc3v3_sys>; vcc2-supply =3D <&vcc3v3_sys>; vcc3-supply =3D <&vcc3v3_sys>; @@ -340,6 +370,11 @@ regulator-state-mem { }; }; =20 +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status =3D "okay"; +}; + &mdio0 { rgmii_phy0: ethernet-phy@0 { compatible =3D "ethernet-phy-ieee802.3-c22"; @@ -379,6 +414,12 @@ pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + rk809 { + hp_det_pin: hp-det-pin { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pmu_io_domains { --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFC0AC433FE for ; Fri, 30 Sep 2022 05:13:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230519AbiI3FNd (ORCPT ); Fri, 30 Sep 2022 01:13:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230323AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C66081664A5; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=mY3EDY/vx2Uownaii2/cI7b2LqzoukIIBmBHq6JBVYo=; b=vI7ufF45c2ZujmarwO4fpkI6J2 zpap5xxdpN2CfStNw3GQuwwLUMY7+frxpSNCvZNT5Qohrdp0v7cBWBW3BC58l3T/LTiiCEZq8+vnS dpcdzs4zdlpAqtijXKAbgSeF9L5FTMMB1eTq/hrGQkHDi9p2paxiA5z9YtlgBihCSv3gM6r564kAM KAlWZwIM9iL46vpgr6WaGJ3yj8AsV5J6F810n1zwlLfjrfwiCzqT0+E+ONHbk1oPCAgd0pK8CJY42 mVrdLb2AywwY5LtrVenjdPtcx5l3/CKscryDf+HhVjz9Wf14RrGOCV+enQGDsydjk61WXWCjERCAK qIvNMIDQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Ke-00Djew-2p; Fri, 30 Sep 2022 07:13:04 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kd-001dv6-1V; Fri, 30 Sep 2022 07:13:03 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 06/13] arm64: dts: rockchip: Enable vop2 and hdmi tx on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:39 +0200 Message-Id: <20220930051246.391614-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the RK356x Video Output Processor (VOP) 2 on ODROID M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 634c1bd80b4e..126b893048fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "rk3568.dtsi" =20 / { @@ -37,6 +38,17 @@ dc_12v: dc-12v-regulator { regulator-max-microvolt =3D <12000000>; }; =20 + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -131,6 +143,24 @@ &gmac0_rgmii_clk rx_delay =3D <0x2d>; }; =20 +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + &i2c0 { status =3D "okay"; =20 @@ -517,3 +547,20 @@ &tsadc { &uart2 { status =3D "okay"; }; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A3BDC433F5 for ; Fri, 30 Sep 2022 05:14:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229574AbiI3FOV (ORCPT ); Fri, 30 Sep 2022 01:14:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230372AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A63001664AB; Thu, 29 Sep 2022 22:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=ZB+wIhFYn9b6/VRhzZ02j0AeAFBVE/fffN0ePcGyD8A=; b=Vq4+kP7Hzc0C8jkycwxk0T9iyy CqAUTr+XUD1KvusdMUuiZgIXb1R5hTjN23z8KgNrTl9/nDiVeau9Ah4IhpILxAbZU0odj9TPBSk8G 9Ng/fk9kIplcYwqbPqMxLKDd9HmKPkLHIw/pRneunPS04p61odF3frCcLPi3lhlsY3k1OOOHGTRW8 oy0UfSZsOQ1rmGYg0vnNzg1Y0RU6X1XEVMvzPdsiMuErR1Cwm+IhALhbf5MzPvCy6L3QU0gbRvY/T rIEa2rpBeoumwvxbhEjqv2a3cmSSWIyE0zjnihCPxe5l73RO6HGO8EpVjvi4hhEBef/tU2p7CAUCN whTtPa4g==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Ke-00Djf7-F0; Fri, 30 Sep 2022 07:13:04 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kd-001dvJ-2d; Fri, 30 Sep 2022 07:13:03 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 07/13] arm64: dts: rockchip: Enable HDMI audio on ODROID-M1. Date: Fri, 30 Sep 2022 07:12:40 +0200 Message-Id: <20220930051246.391614-8-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This enables the i2s0 controller and the hdmi-sound node on the ODROID-M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 126b893048fe..ac4e94d18feb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -161,6 +161,10 @@ hdmi_out_con: endpoint { }; }; =20 +&hdmi_sound { + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -400,6 +404,10 @@ regulator-state-mem { }; }; =20 +&i2s0_8ch { + status =3D "okay"; +}; + &i2s1_8ch { rockchip,trcm-sync-tx-only; status =3D "okay"; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F7AC433FE for ; Fri, 30 Sep 2022 05:14:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229696AbiI3FOC (ORCPT ); Fri, 30 Sep 2022 01:14:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B77FA1664AD; Thu, 29 Sep 2022 22:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=ypMQ4XgbvXncnzJhuzBdDiqc5hueXXs/1IVnLmGV/8s=; b=zpNRVEQ2qmJO+eNV5+iRggNZuQ d1g7XN4s68x4sknMpBrv2H2AJUCYs1Ln9juEkb5LKfiJEHl34Mg/7N6Uj7rrPsKN3q6t7hp3FYEZ5 RMHqrG8vBLB1w2nocS+8Yd5pkT2s5dWcIXuz12JOZyWrmo/tIe7F9pQOSMLh4vbSjflsFS0cGva0O k38kIqrTNPA+hcefUKVpD0DB3gBF9ZiJ0mxb+Uq0VAxuyirG8rsppmyLp/YWJRvwCEdBrixXPwSvw EOiM3IRLCLm+NzrFL6QcfjlpQ/ZOqzfAwiug+U5Cqm0mPSjMldwNDKYRV3yusQNQVik2Zo0yjGjPN i66sn+7Q==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Ke-00DjfL-Qc; Fri, 30 Sep 2022 07:13:04 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Ke-001dvY-0g; Fri, 30 Sep 2022 07:13:04 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 08/13] arm64: dts: rockchip: Enable the GPU on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:41 +0200 Message-Id: <20220930051246.391614-9-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the GPU core on the Rockchip RK3568 ODROID-M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index ac4e94d18feb..e4b7699d3eea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -143,6 +143,11 @@ &gmac0_rgmii_clk rx_delay =3D <0x2d>; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + &hdmi { avdd-0v9-supply =3D <&vdda0v9_image>; avdd-1v8-supply =3D <&vcca1v8_image>; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4363DC433F5 for ; Fri, 30 Sep 2022 05:13:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229606AbiI3FNX (ORCPT ); Fri, 30 Sep 2022 01:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6A421664A4; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=2Z0orixVMMmZ5VqVIk55pq3AUKfU1o1MRrPIzz8sIPw=; b=r9trFQ13Eo0msZk2ZZW67dl+qc Gd+Qt3yjWP3LlS4vDQvnPJ8y0rjDTDjvMEjCw7uTKKG9h/Ea0xwSSgbPIc1l9Em2rbmMRq2B1o/v1 o1r4KIceemcBGnTXVb4julHAiKKk+6DEdQcSuL1H9JXHOrs2+YZIsllMwndIyu1oekmU/PA+9YVbY 1/RwuOcPclnh6ExcYeK+AcF8o0PjK0o5CzvWEWbKP7m9FsTtQurteUIYIYB+Fn018KjeRfdpPgOdB XHetpb0JnoDPbiknDAWq8HyjkmxGZwEjzyWCHOqtbSk8hrDu/U79R8mWyTikXjsLZkc1jsoaVK3qZ vIllVRIQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kf-00DjfX-An; Fri, 30 Sep 2022 07:13:05 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Ke-001dvk-1x; Fri, 30 Sep 2022 07:13:04 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 09/13] arm64: dts: rockchip: Enable the USB 2.0 ports on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:42 +0200 Message-Id: <20220930051246.391614-10-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Rockchip RK3568 has two USB OHCI/EHCI controllers connected to a PHY providing one host-only port and one OTG port. On the ODROID-M1, they are both used in host mode. The USB ports are powered by a DC/DC converter providing 5V and named VCC5V0_SYS on the schematics, followed by a power switch. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index e4b7699d3eea..2e4cc20bd676 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -105,6 +105,28 @@ vcc3v3_sys: vcc3v3-sys-regulator { regulator-max-microvolt =3D <3300000>; vin-supply =3D <&dc_12v>; }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_host_en_pin>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; }; =20 &cpu0 { @@ -463,6 +485,15 @@ hp_det_pin: hp-det-pin { rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pmu_io_domains { @@ -561,6 +592,36 @@ &uart2 { status =3D "okay"; }; =20 +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + &vop { assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 503CBC433FE for ; Fri, 30 Sep 2022 05:13:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229998AbiI3FN4 (ORCPT ); Fri, 30 Sep 2022 01:13:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230330AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C669C1664A6; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; 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Fri, 30 Sep 2022 07:13:04 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 10/13] arm64: dts: rockchip: Enable the USB 3.0 ports on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:43 +0200 Message-Id: <20220930051246.391614-11-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Rockchip RK3568 has two USB XHCI controllers. The USB 2.0 signals are connected to a PHY providing one host-only port and one OTG port. The USB 3.0 signals are connected to two USB3.0/PCIE/SATA combo PHY. The ODROID M1 has 2 type A USB 3.0 connectors, with the USB 3.0 signals connected to the two combo PHYs. For the USB 2.0 signals, one connector is connected to the host-only PHY and uses the same power switch as the USB 2.0 ports. The other connector has its own power switch and is connected to the OTG PHY, which is also connected to a device only micro-USB connector. The purpose of this micro-USB connector is for firmware update using the Rockusb vendor specific USB class. Therefore it does not make sense to enable this port on Linux, and the PHY is forced to host mode. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 49 ++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 2e4cc20bd676..9a84a7e76d7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -127,6 +127,30 @@ vcc5v0_usb_host: vcc5v0-usb-host-regulator { regulator-max-microvolt =3D <5000000>; vin-supply =3D <&vcc5v0_sys>; }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_pin>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0 { + /* Used for USB3 */ + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&combphy1 { + /* Used for USB3 */ + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; }; =20 &cpu0 { @@ -490,7 +514,7 @@ usb { vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { + vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -600,6 +624,11 @@ &usb_host0_ohci { status =3D "okay"; }; =20 +&usb_host0_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + &usb_host1_ehci { status =3D "okay"; }; @@ -608,6 +637,24 @@ &usb_host1_ohci { status =3D "okay"; }; =20 +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + &usb2phy1 { status =3D "okay"; }; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52575C433F5 for ; Fri, 30 Sep 2022 05:13:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231124AbiI3FNg (ORCPT ); Fri, 30 Sep 2022 01:13:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230327AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6CAF1664A7; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=1SQ7lNpSiCQMCl0mv1Tz12guO+YBNRrBVs+sLNxQgeY=; b=VzHRPby4+VJ/9bxGJKzTGeMo74 usqo6VSSv+D9Vy5IwNK0g4nt0Yhsv2mSqaFDW9arfPdQ5RWtnx3ZMrLaLM/GEoFEjMcpxu1Kt3jU2 rJoljoeMqvsITqDHjdttU+7dFBoNPknCyQ36u5/9dA7JXgkILt6wabFwRKNw7y68Q+qe8RpwhYLD0 QmgRS2ZdlxNbY3r9ewNl8ada+rnzJ+2lCOx285oMGmtQby0Vbf7BAU7Iviljhd8CICFBc+1EVbFNJ OLwn/MNq4f584Kj8CzkdSDkVD68JXpXnAgEEF5xM6l/ktCMfQX5NIs0Yf3CiusZu2X84Zh+TxNEmQ s9JqVyGQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kg-00Djfm-0h; Fri, 30 Sep 2022 07:13:06 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kf-001dw5-0y; Fri, 30 Sep 2022 07:13:05 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 11/13] arm64: dts: rockchip: Add SATA support to ODROID-M1 Date: Fri, 30 Sep 2022 07:12:44 +0200 Message-Id: <20220930051246.391614-12-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Combo PHY and SATA nodes in ODROID-M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 9a84a7e76d7a..bd24ccf94e76 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -153,6 +153,11 @@ &combphy1 { status =3D "okay"; }; =20 +&combphy2 { + /* used for SATA */ + status =3D "okay"; +}; + &cpu0 { cpu-supply =3D <&vdd_cpu>; }; @@ -538,6 +543,10 @@ &saradc { status =3D "okay"; }; =20 +&sata2 { + status =3D "okay"; +}; + &sdhci { bus-width =3D <8>; max-frequency =3D <200000000>; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5E53C433FE for ; Fri, 30 Sep 2022 05:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231193AbiI3FOJ (ORCPT ); Fri, 30 Sep 2022 01:14:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230386AbiI3FNN (ORCPT ); Fri, 30 Sep 2022 01:13:13 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 971D9142E04; Thu, 29 Sep 2022 22:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=DDAhsfiRYbh3/+MkjL9NfNU/4tzDdoR0tDFSXdyD3TA=; b=E07JNPks7+cdyR5S/HjUEMQalp 8dujHPsKnIJGQ33116zFm+44j+nJCm/fxVt89mqg8K70BPLijnVuWVUEmPf37FdLNL+MQZ9NJd73l U1LiahMinRAzf09bxedNJe9svtoDpl4UjQOqAoC8uxZ9ysgmjnjFy0eJy8FGJmK4kB3DUkxJed243 jqhpDo3nOaeIirrjlNNHh7tU7SK6jdhG8+/8ZMDBP+ulKjYyCcFdI9jFPm7bIIRferQZYZaHuHU/v 5CTxsU/2eIr5JdQsVJ11JdDcOB4/2hSp5AY3orvKzMnvZ1Q3BU4H2dVW3lM9XnDj6455wB21WH+q5 PILNY7xA==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kg-00Djfx-9C; Fri, 30 Sep 2022 07:13:06 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kf-001dwH-22; Fri, 30 Sep 2022 07:13:05 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 12/13] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1 Date: Fri, 30 Sep 2022 07:12:45 +0200 Message-Id: <20220930051246.391614-13-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index bd24ccf94e76..2f685c606bb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -96,6 +96,19 @@ simple-audio-card,codec { }; }; =20 + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie"; + enable-active-high; + gpio =3D <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc3v3_sys>; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_sys"; @@ -479,6 +492,18 @@ rgmii_phy0: ethernet-phy@0 { }; }; =20 +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_pin>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + &pinctrl { fspi { fspi_dual_io_pins: fspi-dual-io-pins { @@ -503,6 +528,15 @@ led_work_pin: led-work-pin { }; }; =20 + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins =3D <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins =3D <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.35.1 From nobody Wed May 8 22:34:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EB58C433FE for ; Fri, 30 Sep 2022 05:13:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbiI3FNj (ORCPT ); Fri, 30 Sep 2022 01:13:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E2631664A8; Thu, 29 Sep 2022 22:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=G/DCuas0MLgTm0P57BFgZrTVZlNe0W+v2z9cQz8Xx8I=; b=Gzu1RgYPzscghwaBKykzNVbZI/ dU5cBOzRq9yZJ4ddEHK3Gw9V9NNGw9N37xtJOFPeilJjeMRCtxA89cpqr9dS2ccoFqeOnW8xjYmWq G+uuCKstAHHjLFGWGU/3Sh+6ILyuZLa0gAVCHY5+cEyLKR8uQOtmx8nNCjorGkpairbObyjBaDc7e cYoZDn5FA8loUNV7EDmr8FyuV6UwkQ/G+LqbeGRAxJaD1lIUK1Z8Ok2gMqU9asf2yGvnkA/SfkUr1 1m39FfssCjIk7U8c9J3NaTegHR9z/qrWPPctUQUgbtm+Oghi2jbEvj5yZw+ofLll5gmtV3I7eOcvo GJZw9tlA==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Kg-00Djg8-LL; Fri, 30 Sep 2022 07:13:06 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kf-001dwS-34; Fri, 30 Sep 2022 07:13:05 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 13/13] arm64: dts: rockchip: Add IR receiver node to ODROID-M1 Date: Fri, 30 Sep 2022 07:12:46 +0200 Message-Id: <20220930051246.391614-14-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the infrared receiver and its associated pinctrl entry. Note that there is an external pullup to VCC3V3_SYS. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 2f685c606bb9..59ecf868dbd0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -49,6 +49,13 @@ hdmi_con_in: endpoint { }; }; =20 + ir-receiver { + compatible =3D "gpio-ir-receiver"; + gpios =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_receiver_pin>; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -519,6 +526,13 @@ fspi_dual_io_pins: fspi-dual-io-pins { }; }; =20 + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + /* external pullup to VCC3V3_SYS */ + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { led_power_pin: led-power-pin { rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; --=20 2.35.1