From nobody Sat Sep 21 14:57:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 059BEC433F5 for ; Thu, 29 Sep 2022 11:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235495AbiI2Lqw (ORCPT ); Thu, 29 Sep 2022 07:46:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235424AbiI2Lqn (ORCPT ); Thu, 29 Sep 2022 07:46:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F50912AC6; Thu, 29 Sep 2022 04:46:39 -0700 (PDT) X-UUID: 2fc89144367b483780cf2eef36ba554c-20220929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dEREXDrcvhelkOICfcyA9Xxt4SjBwZLsSdOAbzmW7k8=; b=u0lb5p4Mc22uPckHdH4+zEXfB+tkjCgFoYN2cYnnu9pyNNqTrIdPM9emykPMy5SkvyWHJ5oFmIwtXWegw6XuxyWyfmN9D0YeqKE+H4mGosWHbqDfFGG5zDPshVUoKyvCaYWx1rplyDzzWnM+ivyL7Q3/06DWlxVOaPZf1JD/Jh0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:f36c2b3e-72c0-4034-b5bf-573560c09393,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:f36c2b3e-72c0-4034-b5bf-573560c09393,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:b72a7307-1cee-4c38-b21b-a45f9682fdc0,B ulkID:220929194634RJEI7S7V,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: 2fc89144367b483780cf2eef36ba554c-20220929 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2013719714; Thu, 29 Sep 2022 19:46:31 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 29 Sep 2022 19:46:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 29 Sep 2022 19:46:29 +0800 From: Johnson Wang To: , , , CC: , , , , , , , , Johnson Wang , Edward-JW Yang Subject: [PATCH v3 4/4] clk: mediatek: Change PLL register API for MT8186 Date: Thu, 29 Sep 2022 19:46:24 +0800 Message-ID: <20220929114624.16809-5-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220929114624.16809-1-johnson.wang@mediatek.com> References: <20220929114624.16809-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use mtk_clk_register_pllfhs() to enhance frequency hopping and spread spectrum clocking control for MT8186. Co-developed-by: Edward-JW Yang Signed-off-by: Edward-JW Yang Signed-off-by: Johnson Wang --- drivers/clk/mediatek/Kconfig | 1 + drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 66 +++++++++++++++++++- 2 files changed, 64 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 65b25082daf2..2de905aa6132 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -523,6 +523,7 @@ config COMMON_CLK_MT8186 bool "Clock driver for MediaTek MT8186" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL default ARCH_MEDIATEK help This driver supports MediaTek MT8186 clocks. diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index e692a2a67ce1..1d673c6278a9 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -9,6 +9,7 @@ =20 #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #define MT8186_PLL_FMAX (3800UL * MHZ) #define MT8186_PLL_FMIN (1500UL * MHZ) @@ -76,6 +77,59 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350), }; =20 +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL, + FH_CCIPLL, + FH_MAINPLL, + FH_MMPLL, + FH_TVDPLL, + FH_RESERVE6, + FH_ADSPPLL, + FH_MFGPLL, + FH_NNAPLL, + FH_NNA2PLL, + FH_MSDCPLL, + FH_RESERVE12, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C), + FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050), + FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8), + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC), + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0), + FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118), +}; + static const struct of_device_id of_match_clk_mt8186_apmixed[] =3D { { .compatible =3D "mediatek,mt8186-apmixedsys", }, {} @@ -85,13 +139,17 @@ static int clk_mt8186_apmixed_probe(struct platform_de= vice *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8186-fhctl"; int r; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; =20 @@ -104,7 +162,8 @@ static int clk_mt8186_apmixed_probe(struct platform_dev= ice *pdev) return r; =20 unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; @@ -116,7 +175,8 @@ static int clk_mt8186_apmixed_remove(struct platform_de= vice *pdev) struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); =20 of_clk_del_provider(node); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.18.0