From nobody Sat Sep 21 14:07:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 747D0C433F5 for ; Thu, 29 Sep 2022 11:47:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235514AbiI2LrA (ORCPT ); Thu, 29 Sep 2022 07:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235464AbiI2Lqo (ORCPT ); Thu, 29 Sep 2022 07:46:44 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86844A5701; Thu, 29 Sep 2022 04:46:40 -0700 (PDT) X-UUID: e1d45dd197b94fa8b866071d95a8b496-20220929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=39ebN8yN46vkEhOfN7WVyLWWk/+c6irLgIToD0MrqLc=; b=gzxAwSytLivThdhMuyKZxr0U8GHXHz/a/rVbFvYjEK50qdqEQXsamkDnwZW3LgsZbfojCeGuccXPhlxS+BnejLhbwYdntyumI/BHstY1DldTnDGIscBbzaHHU9J6U+BFmaII0BhWOhRlp1pPWwurRLf62HAsXw5phpwUtlLZf5g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:316c79e8-5941-4920-bd13-4a0e5d4dda59,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:316c79e8-5941-4920-bd13-4a0e5d4dda59,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:73d180a3-dc04-435c-b19b-71e131a5fc35,B ulkID:220929194634FH4VEPHZ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: e1d45dd197b94fa8b866071d95a8b496-20220929 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1807388709; Thu, 29 Sep 2022 19:46:31 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 29 Sep 2022 19:46:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 29 Sep 2022 19:46:29 +0800 From: Johnson Wang To: , , , CC: , , , , , , , , Johnson Wang , Edward-JW Yang Subject: [PATCH v3 1/4] clk: mediatek: Export PLL operations symbols Date: Thu, 29 Sep 2022 19:46:21 +0800 Message-ID: <20220929114624.16809-2-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220929114624.16809-1-johnson.wang@mediatek.com> References: <20220929114624.16809-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Export PLL operations and register functions for different type of clock driver used. Co-developed-by: Edward-JW Yang Signed-off-by: Edward-JW Yang Signed-off-by: Johnson Wang --- drivers/clk/mediatek/clk-pll.c | 84 ++++++++++++++-------------------- drivers/clk/mediatek/clk-pll.h | 56 +++++++++++++++++++++++ 2 files changed, 90 insertions(+), 50 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 54e6cfd29dfc..a4eca5fd539c 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -27,37 +27,10 @@ =20 #define AUDPLL_TUNER_EN BIT(31) =20 -#define POSTDIV_MASK 0x7 - /* default 7 bits integer, can be overridden with pcwibits. */ #define INTEGER_BITS 7 =20 -/* - * MediaTek PLLs are configured through their pcw value. The pcw value des= cribes - * a divider in the PLL feedback loop which consists of 7 bits for the int= eger - * part and the remaining bits (if present) for the fractional part. Also = they - * have a 3 bit power-of-two post divider. - */ - -struct mtk_clk_pll { - struct clk_hw hw; - void __iomem *base_addr; - void __iomem *pd_addr; - void __iomem *pwr_addr; - void __iomem *tuner_addr; - void __iomem *tuner_en_addr; - void __iomem *pcw_addr; - void __iomem *pcw_chg_addr; - void __iomem *en_addr; - const struct mtk_pll_data *data; -}; - -static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) -{ - return container_of(hw, struct mtk_clk_pll, hw); -} - -static int mtk_pll_is_prepared(struct clk_hw *hw) +int mtk_pll_is_prepared(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); =20 @@ -161,8 +134,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *p= ll, u32 pcw, * @fin: The input frequency * */ -static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *po= stdiv, - u32 freq, u32 fin) +void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, + u32 freq, u32 fin) { unsigned long fmin =3D pll->data->fmin ? pll->data->fmin : (1000 * MHZ); const struct mtk_pll_div_table *div_table =3D pll->data->div_table; @@ -198,8 +171,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll= , u32 *pcw, u32 *postdiv, *pcw =3D (u32)_pcw; } =20 -static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) +int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 pcw =3D 0; @@ -211,8 +184,7 @@ static int mtk_pll_set_rate(struct clk_hw *hw, unsigned= long rate, return 0; } =20 -static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_= rate) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 postdiv; @@ -227,8 +199,8 @@ static unsigned long mtk_pll_recalc_rate(struct clk_hw = *hw, return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); } =20 -static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 pcw =3D 0; @@ -239,7 +211,7 @@ static long mtk_pll_round_rate(struct clk_hw *hw, unsig= ned long rate, return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); } =20 -static int mtk_pll_prepare(struct clk_hw *hw) +int mtk_pll_prepare(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 r; @@ -273,7 +245,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) return 0; } =20 -static void mtk_pll_unprepare(struct clk_hw *hw) +void mtk_pll_unprepare(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 r; @@ -301,7 +273,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) writel(r, pll->pwr_addr); } =20 -static const struct clk_ops mtk_pll_ops =3D { +const struct clk_ops mtk_pll_ops =3D { .is_prepared =3D mtk_pll_is_prepared, .prepare =3D mtk_pll_prepare, .unprepare =3D mtk_pll_unprepare, @@ -310,18 +282,15 @@ static const struct clk_ops mtk_pll_ops =3D { .set_rate =3D mtk_pll_set_rate, }; =20 -static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, - void __iomem *base) +struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, + const struct mtk_pll_data *data, + void __iomem *base, + const struct clk_ops *pll_ops) { - struct mtk_clk_pll *pll; struct clk_init_data init =3D {}; int ret; const char *parent_name =3D "clk26m"; =20 - pll =3D kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - pll->base_addr =3D base + data->reg; pll->pwr_addr =3D base + data->pwr_reg; pll->pd_addr =3D base + data->pd_reg; @@ -343,7 +312,7 @@ static struct clk_hw *mtk_clk_register_pll(const struct= mtk_pll_data *data, =20 init.name =3D data->name; init.flags =3D (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; - init.ops =3D &mtk_pll_ops; + init.ops =3D pll_ops; if (data->parent_name) init.parent_names =3D &data->parent_name; else @@ -360,7 +329,22 @@ static struct clk_hw *mtk_clk_register_pll(const struc= t mtk_pll_data *data, return &pll->hw; } =20 -static void mtk_clk_unregister_pll(struct clk_hw *hw) +struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, + void __iomem *base) +{ + struct mtk_clk_pll *pll; + struct clk_hw *hw; + + pll =3D kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + hw =3D mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops); + + return hw; +} + +void mtk_clk_unregister_pll(struct clk_hw *hw) { struct mtk_clk_pll *pll; =20 @@ -423,8 +407,8 @@ int mtk_clk_register_plls(struct device_node *node, } EXPORT_SYMBOL_GPL(mtk_clk_register_plls); =20 -static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, - const struct mtk_pll_data *data) +__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, + const struct mtk_pll_data *data) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); =20 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index fe3199715688..e87ab08eea9b 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -7,6 +7,7 @@ #ifndef __DRV_CLK_MTK_PLL_H #define __DRV_CLK_MTK_PLL_H =20 +#include #include =20 struct clk_ops; @@ -20,6 +21,7 @@ struct mtk_pll_div_table { =20 #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) +#define POSTDIV_MASK 0x7 =20 struct mtk_pll_data { int id; @@ -48,10 +50,64 @@ struct mtk_pll_data { u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ }; =20 +/* + * MediaTek PLLs are configured through their pcw value. The pcw value des= cribes + * a divider in the PLL feedback loop which consists of 7 bits for the int= eger + * part and the remaining bits (if present) for the fractional part. Also = they + * have a 3 bit power-of-two post divider. + */ + +struct mtk_clk_pll { + struct clk_hw hw; + void __iomem *base_addr; + void __iomem *pd_addr; + void __iomem *pwr_addr; + void __iomem *tuner_addr; + void __iomem *tuner_en_addr; + void __iomem *pcw_addr; + void __iomem *pcw_chg_addr; + void __iomem *en_addr; + const struct mtk_pll_data *data; +}; + + int mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data); void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data); =20 +extern const struct clk_ops mtk_pll_ops; + +static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) +{ + return container_of(hw, struct mtk_clk_pll, hw); +} + +int mtk_pll_is_prepared(struct clk_hw *hw); + +int mtk_pll_prepare(struct clk_hw *hw); + +void mtk_pll_unprepare(struct clk_hw *hw); + +unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_= rate); + +void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, + u32 freq, u32 fin); +int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate); + +struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, + const struct mtk_pll_data *data, + void __iomem *base, + const struct clk_ops *pll_ops); +struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, + void __iomem *base); +void mtk_clk_unregister_pll(struct clk_hw *hw); + +__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, + const struct mtk_pll_data *data); + #endif /* __DRV_CLK_MTK_PLL_H */ --=20 2.18.0