From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCDDFC32771 for ; Wed, 28 Sep 2022 17:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233656AbiI1RxH (ORCPT ); Wed, 28 Sep 2022 13:53:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234299AbiI1Rww (ORCPT ); Wed, 28 Sep 2022 13:52:52 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F1B5F8C37; Wed, 28 Sep 2022 10:52:50 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqQ29068346; Wed, 28 Sep 2022 12:52:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664387546; bh=ZDGY++hbiatkPuL2SZZuzL6ocLLtEggP+NKxDZhpR/E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ga+wlokM4nyk6F6ng4aTswYwxlEskIVfy/EzVirDhA4llIk6Mu5bFfTGswZdyYVAy Da+BhGfnBKO11kISOmP2I7+xlv2EC7efhSzbX6JQ3c5ADrTQxZ/DSGbisWhtOeahWJ QfdVzMH/SpQ32QfTYp0dTHoiBMuQHP3rTlXzJkF0= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28SHqQfd115146 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Sep 2022 12:52:26 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:26 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:26 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqPdp001048; Wed, 28 Sep 2022 12:52:26 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 1/6] dt-bindings: display: ti,am65x-dss: Add am625 dss compatible Date: Wed, 28 Sep 2022 23:22:18 +0530 Message-ID: <20220928175223.15225-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ti,am625-dss compatible string. The DSS IP on TI's AM625 SoC is an update from the DSS on TI's AM65X SoC. The former has an additional OLDI TX to enable a 2K resolution on OLDI displays or enable 2 duplicated displays with a smaller resolution. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..6bbce921479d 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -19,7 +19,9 @@ description: | =20 properties: compatible: - const: ti,am65x-dss + enum: + - ti,am625-dss + - ti,am65x-dss =20 reg: description: --=20 2.37.0 From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BDB8C32771 for ; Wed, 28 Sep 2022 17:53:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234290AbiI1RxF (ORCPT ); Wed, 28 Sep 2022 13:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234093AbiI1Rww (ORCPT ); Wed, 28 Sep 2022 13:52:52 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBAACF85AC; Wed, 28 Sep 2022 10:52:49 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqSeE068355; Wed, 28 Sep 2022 12:52:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664387548; bh=U/A5bFOTrvS5PJd2SiMxUroXJjiGvivMeuXikcg9+n0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pU2/IBjr9EfNnKFxbu8dFyG85vxYJnTgj3RPtkXruA2Pt54RkT9N5m1isHXmCLFuX ZT5DgB+/uqJbzOm8U0t6BjmoYTAtfO1jTYqWJniLgbqi0mXgcPmpu/cx/v1neg8TNn Xwlb1wsPMnXm53YSmfm4ae2zVP6mDCoyjWPU41uU= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28SHqSfL115162 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Sep 2022 12:52:28 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:27 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:27 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqQ3W001066; Wed, 28 Sep 2022 12:52:27 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 2/6] dt-bindings: display: ti: am65x-dss: Add new port for am625-dss Date: Wed, 28 Sep 2022 23:22:19 +0530 Message-ID: <20220928175223.15225-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add 3rd "port" property for am625-dss. This port represents the output from the 2nd OLDI TX (OLDI TX 1) latched onto the first video port (VP0) from the DSS controller on AM625 SOC. Signed-off-by: Aradhya Bhatia Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/ti/ti,am65x-dss.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 6bbce921479d..99576c6ec108 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -82,13 +82,18 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + The DSS OLDI output port node form video port 1 (OLDI TX 0). =20 port@1: $ref: /schemas/graph.yaml#/properties/port description: The DSS DPI output port node from video port 2 =20 + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + The DSS OLDI output port node form video port 1 (OLDI TX 1). + ti,am65x-oldi-io-ctrl: $ref: "/schemas/types.yaml#/definitions/phandle" description: @@ -104,6 +109,17 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second =20 +if: + properties: + compatible: + contains: + const: ti,am65x-dss +then: + properties: + ports: + properties: + port@2: false + required: - compatible - reg --=20 2.37.0 From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B04EC32771 for ; Wed, 28 Sep 2022 17:53:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234652AbiI1RxV (ORCPT ); Wed, 28 Sep 2022 13:53:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234723AbiI1RxJ (ORCPT ); Wed, 28 Sep 2022 13:53:09 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51184F8594; Wed, 28 Sep 2022 10:52:59 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqTdm077451; Wed, 28 Sep 2022 12:52:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664387549; bh=wOdTIH04zCG32VSdCu2/2EFESBmHau0thJrO8QBimxo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DOqQmbbrFAeZ+KlatytGC9cE8NIhKbyZycV+/I0RfI7I6ztP0cjOyDwZU0M5+AVbc wVMAzMR/kayQv2u5ThbE/MVMo08v27W/tV/bMrZYJIQLN4XD/Z0p54mglC4ey0oTdo lUBYa07VkSFTgsOlO9wdQmSBBcJtQQa/AzeGokm4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28SHqT7S029184 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Sep 2022 12:52:29 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:29 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqS19001228; Wed, 28 Sep 2022 12:52:28 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 3/6] drm/tidss: Add support for AM625 DSS Date: Wed, 28 Sep 2022 23:22:20 +0530 Message-ID: <20220928175223.15225-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the DSS controller on TI's new AM625 SoC in the tidss driver. The first video port (VP0) in am625-dss can output OLDI signals through 2 OLDI TXes. A 3rd port has been added with "DISPC_VP_OLDI" bus type. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 61 ++++++++++++++++++++++++++++- drivers/gpu/drm/tidss/tidss_dispc.h | 3 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index dd3c6a606ae2..34f0da4bb3e3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -93,6 +93,7 @@ const struct dispc_features dispc_k2g_feats =3D { .common_regs =3D tidss_k2g_common_regs, =20 .num_vps =3D 1, + .num_max_ports =3D 1, .vp_name =3D { "vp1" }, .ovr_name =3D { "ovr1" }, .vpclk_name =3D { "vp1" }, @@ -168,6 +169,7 @@ const struct dispc_features dispc_am65x_feats =3D { .common_regs =3D tidss_am65x_common_regs, =20 .num_vps =3D 2, + .num_max_ports =3D 2, .vp_name =3D { "vp1", "vp2" }, .ovr_name =3D { "ovr1", "ovr2" }, .vpclk_name =3D { "vp1", "vp2" }, @@ -257,6 +259,7 @@ const struct dispc_features dispc_j721e_feats =3D { .common_regs =3D tidss_j721e_common_regs, =20 .num_vps =3D 4, + .num_max_ports =3D 4, .vp_name =3D { "vp1", "vp2", "vp3", "vp4" }, .ovr_name =3D { "ovr1", "ovr2", "ovr3", "ovr4" }, .vpclk_name =3D { "vp1", "vp2", "vp3", "vp4" }, @@ -275,6 +278,57 @@ const struct dispc_features dispc_j721e_feats =3D { .vid_order =3D { 1, 3, 0, 2 }, }; =20 +const struct dispc_features dispc_am625_feats =3D { + .max_pclk_khz =3D { + [DISPC_VP_DPI] =3D 165000, + [DISPC_VP_OLDI] =3D 165000, + }, + + .scaling =3D { + .in_width_max_5tap_rgb =3D 1280, + .in_width_max_3tap_rgb =3D 2560, + .in_width_max_5tap_yuv =3D 2560, + .in_width_max_3tap_yuv =3D 4096, + .upscale_limit =3D 16, + .downscale_limit_5tap =3D 4, + .downscale_limit_3tap =3D 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max =3D 32, + }, + + .subrev =3D DISPC_AM625, + + .common =3D "common", + .common_regs =3D tidss_am65x_common_regs, + + .num_vps =3D 2, + /* note: the 3rd port is not representative of a 3rd pipeline */ + .num_max_ports =3D 3, + .vp_name =3D { "vp1", "vp2" }, + .ovr_name =3D { "ovr1", "ovr2" }, + .vpclk_name =3D { "vp1", "vp2" }, + .vp_bus_type =3D { DISPC_VP_OLDI, DISPC_VP_DPI, DISPC_VP_OLDI }, + + .vp_feat =3D { .color =3D { + .has_ctm =3D true, + .gamma_size =3D 256, + .gamma_type =3D TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes =3D 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name =3D { "vid", "vidl1" }, + .vid_lite =3D { false, true, }, + .vid_order =3D { 1, 0 }, +}; + static const u16 *dispc_common_regmap; =20 struct dss_vp_data { @@ -778,6 +832,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc= _device *dispc) return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: return dispc_k3_read_and_clear_irqstatus(dispc); default: WARN_ON(1); @@ -793,6 +848,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, di= spc_irq_t mask) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_set_irqenable(dispc, mask); break; default: @@ -1282,6 +1338,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, = u32 hw_plane, x, y, layer); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; @@ -2205,6 +2262,7 @@ static void dispc_plane_init(struct dispc_device *dis= pc) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_plane_init(dispc); break; default: @@ -2310,6 +2368,7 @@ static void dispc_vp_write_gamma_table(struct dispc_d= evice *dispc, dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_J721E: @@ -2583,7 +2642,7 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, 2, 2), REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); =20 - if (dispc->feat->subrev =3D=3D DISPC_AM65X) + if (dispc->feat->subrev =3D=3D DISPC_AM65X || dispc->feat->subrev =3D=3D = DISPC_AM625) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", REG_GET(dispc, DSS_SYSSTATUS, 5, 5), REG_GET(dispc, DSS_SYSSTATUS, 6, 6), diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index e49432f0abf5..b66418e583ee 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -61,6 +61,7 @@ enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM65X, DISPC_J721E, + DISPC_AM625, }; =20 struct dispc_features { @@ -74,6 +75,7 @@ struct dispc_features { const char *common; const u16 *common_regs; u32 num_vps; + u32 num_max_ports; const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ @@ -88,6 +90,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; +extern const struct dispc_features dispc_am625_feats; =20 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index 04cfff89ee51..326059e99696 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -235,6 +235,7 @@ static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,k2g-dss", .data =3D &dispc_k2g_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, + { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, { } }; =20 --=20 2.37.0 From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79499C54EE9 for ; Wed, 28 Sep 2022 17:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234748AbiI1RxR (ORCPT ); Wed, 28 Sep 2022 13:53:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234225AbiI1Rwz (ORCPT ); Wed, 28 Sep 2022 13:52:55 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 470ECF8F91; Wed, 28 Sep 2022 10:52:52 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqVQW068362; Wed, 28 Sep 2022 12:52:31 -0500 DKIM-Signature: v=1; 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Wed, 28 Sep 2022 12:52:30 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqTuc001260; Wed, 28 Sep 2022 12:52:30 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 4/6] drm/tidss: Add support to configure OLDI mode for am625-dss. Date: Wed, 28 Sep 2022 23:22:21 +0530 Message-ID: <20220928175223.15225-5-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal. These can be configured to support the following modes: 1. OLDI_SINGLE_LINK_SINGLE_MODE Single Output over OLDI 0. +------+ +---------+ +-------+ | | | | | | | CRTC +------->+ ENCODER +----->| PANEL | | | | | | | +------+ +---------+ +-------+ 2. OLDI_SINGLE_LINK_CLONE_MODE Duplicate Output over OLDI 0 and 1. +------+ +---------+ +-------+ | | | | | | | CRTC +---+--->| ENCODER +----->| PANEL | | | | | | | | +------+ | +---------+ +-------+ | | +---------+ +-------+ | | | | | +--->| ENCODER +----->| PANEL | | | | | +---------+ +-------+ 3. OLDI_DUAL_LINK_MODE Combined Output over OLDI 0 and 1. +------+ +---------+ +-------+ | | | +----->| | | CRTC +------->+ ENCODER | | PANEL | | | | +----->| | +------+ +---------+ +-------+ Following the above pathways for different modes, 2 encoder/panel-bridge pipes get created for clone mode, and 1 pipe in cases of single link and dual link mode. Add support for confgure the OLDI modes using of and lvds DRM helper functions. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 11 +++ drivers/gpu/drm/tidss/tidss_dispc.h | 8 ++ drivers/gpu/drm/tidss/tidss_drv.h | 3 + drivers/gpu/drm/tidss/tidss_kms.c | 146 +++++++++++++++++++++++----- 4 files changed, 145 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 34f0da4bb3e3..88008ad39b55 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -354,6 +354,8 @@ struct dispc_device { =20 bool is_enabled; =20 + enum dispc_oldi_modes oldi_mode; + struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; =20 u32 *fourccs; @@ -1958,6 +1960,15 @@ const u32 *dispc_plane_formats(struct dispc_device *= dispc, unsigned int *len) return dispc->fourccs; } =20 +int dispc_configure_oldi_mode(struct dispc_device *dispc, + enum dispc_oldi_modes oldi_mode) +{ + WARN_ON(!dispc); + + dispc->oldi_mode =3D oldi_mode; + return 0; +} + static s32 pixinc(int pixels, u8 ps) { if (pixels =3D=3D 1) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index b66418e583ee..45cce1054832 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -64,6 +64,13 @@ enum dispc_dss_subrevision { DISPC_AM625, }; =20 +enum dispc_oldi_modes { + OLDI_MODE_OFF, /* OLDI turned off / tied off in IP. */ + OLDI_SINGLE_LINK_SINGLE_MODE, /* Single Output over OLDI 0. */ + OLDI_SINGLE_LINK_CLONE_MODE, /* Duplicate Output over OLDI 0 and 1. */ + OLDI_DUAL_LINK_MODE, /* Combined Output over OLDI 0 and 1. */ +}; + struct dispc_features { int min_pclk_khz; int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; @@ -131,6 +138,7 @@ int dispc_plane_setup(struct dispc_device *dispc, u32 h= w_plane, u32 hw_videoport); int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enab= le); const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *l= en); +int dispc_configure_oldi_mode(struct dispc_device *dispc, enum dispc_oldi_= modes oldi_mode); =20 int dispc_init(struct tidss_device *tidss); void dispc_remove(struct tidss_device *tidss); diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tids= s_drv.h index d7f27b0b0315..2252ba0222ca 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -12,6 +12,9 @@ #define TIDSS_MAX_PORTS 4 #define TIDSS_MAX_PLANES 4 =20 +/* For AM625-DSS with 2 OLDI TXes */ +#define TIDSS_MAX_BRIDGE_PER_PIPE 2 + typedef u32 dispc_irq_t; =20 struct tidss_device { diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tids= s_kms.c index 666e527a0acf..73afe390f36d 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -107,32 +107,84 @@ static const struct drm_mode_config_funcs mode_config= _funcs =3D { .atomic_commit =3D drm_atomic_helper_commit, }; =20 +static int tidss_get_oldi_mode(struct tidss_device *tidss) +{ + int pixel_order; + struct device_node *dss_ports, *oldi0_port, *oldi1_port; + + dss_ports =3D of_get_next_child(tidss->dev->of_node, NULL); + oldi0_port =3D of_graph_get_port_by_id(dss_ports, 0); + oldi1_port =3D of_graph_get_port_by_id(dss_ports, 2); + + if (!(oldi0_port && oldi1_port)) + return OLDI_SINGLE_LINK_SINGLE_MODE; + + /* + * OLDI Ports found for both the OLDI TXes. The DSS is to be configured + * in either Dual Link or Clone Mode. + */ + pixel_order =3D drm_of_lvds_get_dual_link_pixel_order(oldi0_port, + oldi1_port); + switch (pixel_order) { + case -EINVAL: + /* + * The dual link properties were not found in at least one of + * the sink nodes. Since 2 OLDI ports are present in the DT, it + * can be safely assumed that the required configuration is + * Clone Mode. + */ + return OLDI_SINGLE_LINK_CLONE_MODE; + + case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: + case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: + /* + * Note that the OLDI TX 0 transmits the odd set of pixels while + * the OLDI TX 1 transmits the even set. This is a fixed + * configuration in the IP and an cannot be change vis SW. These + * properties have been used to merely identify if a Dual Link + * configuration is required. Swapping this property in the panel + * port DT nodes will not make any difference. + */ + return OLDI_DUAL_LINK_MODE; + + default: + return OLDI_MODE_OFF; + } +} + static int tidss_dispc_modeset_init(struct tidss_device *tidss) { struct device *dev =3D tidss->dev; unsigned int fourccs_len; const u32 *fourccs =3D dispc_plane_formats(tidss->dispc, &fourccs_len); - unsigned int i; + unsigned int i, j; =20 struct pipe { u32 hw_videoport; - struct drm_bridge *bridge; + struct drm_bridge *bridge[TIDSS_MAX_BRIDGE_PER_PIPE]; u32 enc_type; + u32 num_bridges; }; =20 const struct dispc_features *feat =3D tidss->feat; - u32 max_vps =3D feat->num_vps; + u32 max_ports =3D feat->num_max_ports; u32 max_planes =3D feat->num_planes; =20 struct pipe pipes[TIDSS_MAX_PORTS]; u32 num_pipes =3D 0; + u32 pipe_number =3D 0; u32 crtc_mask; + u32 num_oldi =3D 0; + u32 oldi0_port =3D 0; + u32 hw_vp =3D 0; + enum dispc_oldi_modes oldi_mode; =20 /* first find all the connected panels & bridges */ =20 - for (i =3D 0; i < max_vps; i++) { + for (i =3D 0; i < max_ports; i++) { struct drm_panel *panel; struct drm_bridge *bridge; + bool bridge_req =3D true; u32 enc_type =3D DRM_MODE_ENCODER_NONE; int ret; =20 @@ -146,6 +198,11 @@ static int tidss_dispc_modeset_init(struct tidss_devic= e *tidss) return ret; } =20 + /* default number of bridges required for a panel/bridge*/ + pipe_number =3D num_pipes; + pipes[pipe_number].num_bridges =3D 1; + hw_vp =3D i; + if (panel) { u32 conn_type; =20 @@ -155,7 +212,43 @@ static int tidss_dispc_modeset_init(struct tidss_devic= e *tidss) case DISPC_VP_OLDI: enc_type =3D DRM_MODE_ENCODER_LVDS; conn_type =3D DRM_MODE_CONNECTOR_LVDS; + + /* + * A single DSS controller cannot support 2 + * independent displays. If 2nd node is detected, + * it is for Dual Link Mode or Clone Mode. + * + * A new pipe instance is not required. + */ + if (++num_oldi =3D=3D 2) { + pipe_number =3D oldi0_port; + hw_vp =3D i; + + /* 2nd OLDI DT node detected. Get its mode */ + oldi_mode =3D tidss_get_oldi_mode(tidss); + bridge_req =3D false; + + /* + * A separate panel bridge will only be + * required if 2 panels are connected for + * the OLDI Clone Mode. + */ + if (oldi_mode =3D=3D OLDI_SINGLE_LINK_CLONE_MODE) { + bridge_req =3D true; + (pipes[pipe_number].num_bridges)++; + } + } else { + /* + * First OLDI DT node detected. Save it + * in case there is another node for Dual + * Link Mode or Clone Mode. + */ + oldi0_port =3D i; + oldi_mode =3D OLDI_SINGLE_LINK_SINGLE_MODE; + } + dispc_configure_oldi_mode(tidss->dispc, oldi_mode); break; + case DISPC_VP_DPI: enc_type =3D DRM_MODE_ENCODER_DPI; conn_type =3D DRM_MODE_CONNECTOR_DPI; @@ -173,19 +266,23 @@ static int tidss_dispc_modeset_init(struct tidss_devi= ce *tidss) return -EINVAL; } =20 - bridge =3D devm_drm_panel_bridge_add(dev, panel); - if (IS_ERR(bridge)) { - dev_err(dev, - "failed to set up panel bridge for port %d\n", - i); - return PTR_ERR(bridge); + if (bridge_req) { + bridge =3D devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR(bridge)) { + dev_err(dev, + "failed to set up panel bridge for port %d\n", + i); + return PTR_ERR(bridge); + } } } =20 - pipes[num_pipes].hw_videoport =3D i; - pipes[num_pipes].bridge =3D bridge; - pipes[num_pipes].enc_type =3D enc_type; - num_pipes++; + if (bridge_req) { + pipes[pipe_number].hw_videoport =3D hw_vp; + pipes[pipe_number].bridge[pipes[pipe_number].num_bridges - 1] =3D bridg= e; + pipes[pipe_number].enc_type =3D enc_type; + num_pipes++; + } } =20 /* all planes can be on any crtc */ @@ -200,6 +297,7 @@ static int tidss_dispc_modeset_init(struct tidss_device= *tidss) u32 hw_plane_id =3D feat->vid_order[tidss->num_planes]; int ret; =20 + /* Creating planes and CRTCs only for real pipes */ tplane =3D tidss_plane_create(tidss, hw_plane_id, DRM_PLANE_TYPE_PRIMARY, crtc_mask, fourccs, fourccs_len); @@ -219,16 +317,18 @@ static int tidss_dispc_modeset_init(struct tidss_devi= ce *tidss) =20 tidss->crtcs[tidss->num_crtcs++] =3D &tcrtc->crtc; =20 - enc =3D tidss_encoder_create(tidss, pipes[i].enc_type, - 1 << tcrtc->crtc.index); - if (IS_ERR(enc)) { - dev_err(tidss->dev, "encoder create failed\n"); - return PTR_ERR(enc); - } + for (j =3D 0; j < pipes[i].num_bridges; j++) { + enc =3D tidss_encoder_create(tidss, pipes[i].enc_type, + 1 << tcrtc->crtc.index); + if (IS_ERR(enc)) { + dev_err(tidss->dev, "encoder create failed\n"); + return PTR_ERR(enc); + } =20 - ret =3D drm_bridge_attach(enc, pipes[i].bridge, NULL, 0); - if (ret) - return ret; + ret =3D drm_bridge_attach(enc, pipes[i].bridge[j], NULL, 0); + if (ret) + return ret; + } } =20 /* create overlay planes of the leftover planes */ --=20 2.37.0 From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 603C7C32771 for ; Wed, 28 Sep 2022 17:53:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbiI1Rw6 (ORCPT ); Wed, 28 Sep 2022 13:52:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233967AbiI1Rwv (ORCPT ); Wed, 28 Sep 2022 13:52:51 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDD2BF8C13; Wed, 28 Sep 2022 10:52:48 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqWVu076976; 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Wed, 28 Sep 2022 12:52:32 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqU7v101937; Wed, 28 Sep 2022 12:52:31 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 5/6] drm/tidss: Add IO CTRL and Power support for OLDI TX in am625 Date: Wed, 28 Sep 2022 23:22:22 +0530 Message-ID: <20220928175223.15225-6-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ctrl mmr module of the AM625 is different from the AM65X SoC. Thus the ctrl mmr registers that supported the OLDI TX power have become different in AM625 SoC. Add IO CTRL support and control the OLDI TX power for AM625. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 55 ++++++++++++++++++------ drivers/gpu/drm/tidss/tidss_dispc_regs.h | 6 +++ 2 files changed, 49 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 88008ad39b55..68444e0cd8d7 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -921,21 +921,52 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u3= 2 hw_videoport, =20 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) { - u32 val =3D power ? 0 : OLDI_PWRDN_TX; + u32 val; =20 if (WARN_ON(!dispc->oldi_io_ctrl)) return; =20 - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, - OLDI_PWRDN_TX, val); + if (dispc->feat->subrev =3D=3D DISPC_AM65X) { + val =3D power ? 0 : OLDI_PWRDN_TX; + + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, + OLDI_PWRDN_TX, val); + + } else if (dispc->feat->subrev =3D=3D DISPC_AM625) { + if (power) { + switch (dispc->oldi_mode) { + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* Power down OLDI TX 1 */ + val =3D OLDI1_PWRDN_TX; + break; + + case OLDI_SINGLE_LINK_CLONE_MODE: + case OLDI_DUAL_LINK_MODE: + /* No Power down */ + val =3D 0; + break; + + default: + /* Power down both the OLDI TXes */ + val =3D OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + break; + } + } else { + /* Power down both the OLDI TXes */ + val =3D OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + } + + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_PD_CTRL, + OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); + } } =20 static void dispc_set_num_datalines(struct dispc_device *dispc, @@ -2831,7 +2862,7 @@ int dispc_init(struct tidss_device *tidss) dispc->vp_data[i].gamma_table =3D gamma_table; } =20 - if (feat->subrev =3D=3D DISPC_AM65X) { + if (feat->subrev =3D=3D DISPC_AM65X || feat->subrev =3D=3D DISPC_AM625) { r =3D dispc_init_am65x_oldi_io_ctrl(dev, dispc); if (r) return r; diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tid= ss/tidss_dispc_regs.h index 13feedfe5d6d..510bee70b3b8 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -238,6 +238,12 @@ enum dispc_common_regs { #define OLDI_DAT3_IO_CTRL 0x0C #define OLDI_CLK_IO_CTRL 0x10 =20 +/* Only for AM625 OLDI TX */ +#define OLDI_PD_CTRL 0x100 +#define OLDI_LB_CTRL 0x104 + #define OLDI_PWRDN_TX BIT(8) +#define OLDI0_PWRDN_TX BIT(0) +#define OLDI1_PWRDN_TX BIT(1) =20 #endif /* __TIDSS_DISPC_REGS_H */ --=20 2.37.0 From nobody Sun May 19 01:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB4CFC04A95 for ; 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Wed, 28 Sep 2022 12:52:33 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:33 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:33 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqWQA001317; Wed, 28 Sep 2022 12:52:33 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 6/6] drm/tidss: Enable Dual and Duplicate Modes for OLDI Date: Wed, 28 Sep 2022 23:22:23 +0530 Message-ID: <20220928175223.15225-7-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The AM625 DSS IP contains 2 OLDI TXes which can work to enable 2 duplicated displays of smaller resolutions or enable a single Dual Link display with a higher resolution (1920x1200). Configure the necessary register to enable and disable the OLDI TXes with necessary modes configurations. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 68444e0cd8d7..fd7f49535f0c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1003,8 +1003,8 @@ static void dispc_enable_oldi(struct dispc_device *di= spc, u32 hw_videoport, int count =3D 0; =20 /* - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are + * set statically to 0. */ =20 if (fmt->data_width =3D=3D 24) @@ -1021,6 +1021,30 @@ static void dispc_enable_oldi(struct dispc_device *d= ispc, u32 hw_videoport, =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 + switch (dispc->oldi_mode) { + case OLDI_MODE_OFF: + oldi_cfg &=3D ~BIT(0); /* DISABLE */ + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* All configuration is done for this mode. */ + break; + + case OLDI_SINGLE_LINK_CLONE_MODE: + oldi_cfg |=3D BIT(5); /* CLONE MODE */ + break; + + case OLDI_DUAL_LINK_MODE: + oldi_cfg |=3D BIT(11); /* DUALMODESYNC */ + oldi_cfg |=3D BIT(3); /* data-mapping field also indicates dual-link mod= e */ + break; + + default: + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); =20 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && --=20 2.37.0