From nobody Sat Sep 21 14:03:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FF8BC32771 for ; Wed, 28 Sep 2022 09:34:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233321AbiI1Jeh (ORCPT ); Wed, 28 Sep 2022 05:34:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233397AbiI1JdV (ORCPT ); Wed, 28 Sep 2022 05:33:21 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C0F73308; Wed, 28 Sep 2022 02:33:18 -0700 (PDT) X-UUID: eb58ce93e25d469c8e0bd0e1562c5936-20220928 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=plO6ko6UxqNOxenMbAi+M8EMiHcKIxgK6VMUFebTRgs=; b=D4TQPYZHFtNlrLRPTlccG+l2HhR6D5KrsPkpXIWdJI5yYyq6Q5erftjNRFovAehum3OPguOCHPeK5owQN2U7sqD5V4cXnu7iLqSXKTrEd/0ZrtzJoX7stC7L75UEUygg9pwWx7Ukk9ZzD+Za027+j7JLSw0fTsXzjuve/PC5GGk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:51b9a95b-ecce-46b7-97e0-95a12c910d5e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:51b9a95b-ecce-46b7-97e0-95a12c910d5e,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:6eeb82e4-87f9-4bb0-97b6-34957dc0fbbe,B ulkID:220928173313H4WTPSNV,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:n il,COL:0 X-UUID: eb58ce93e25d469c8e0bd0e1562c5936-20220928 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2009509457; Wed, 28 Sep 2022 17:33:12 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 28 Sep 2022 17:33:11 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 28 Sep 2022 17:33:09 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , "Tzung-Bi Shih" , , , , kyrie wu CC: , , , , , , Tomasz Figa , , , irui wang , kernel test robot Subject: [V16,03/15] mtk-jpegenc: support jpegenc multi-hardware Date: Wed, 28 Sep 2022 17:32:46 +0800 Message-ID: <20220928093258.32384-4-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220928093258.32384-1-irui.wang@mediatek.com> References: <20220928093258.32384-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: kyrie wu support jpeg encode multi-hardware includes HW0 and HW1. Signed-off-by: kyrie wu Signed-off-by: irui wang Reported-by: kernel test robot --- drivers/media/platform/mediatek/jpeg/Makefile | 11 +- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 69 ++++---- .../platform/mediatek/jpeg/mtk_jpeg_core.h | 42 +++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 161 ++++++++++++++++++ 4 files changed, 249 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/Makefile b/drivers/media/= platform/mediatek/jpeg/Makefile index 76c33aad0f3f..69703db4b0a5 100644 --- a/drivers/media/platform/mediatek/jpeg/Makefile +++ b/drivers/media/platform/mediatek/jpeg/Makefile @@ -1,6 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -mtk_jpeg-objs :=3D mtk_jpeg_core.o \ +obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) +=3D mtk_jpeg.o \ + mtk-jpeg-enc-hw.o + +mtk_jpeg-y :=3D mtk_jpeg_core.o \ mtk_jpeg_dec_hw.o \ - mtk_jpeg_dec_parse.o \ - mtk_jpeg_enc_hw.o -obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) +=3D mtk_jpeg.o + mtk_jpeg_dec_parse.o + +mtk-jpeg-enc-hw-y :=3D mtk_jpeg_enc_hw.o diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 724fb7aeb0ee..2de2e3846b5b 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -680,7 +680,7 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb) { struct mtk_jpeg_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); struct mtk_jpeg_q_data *q_data =3D NULL; - struct v4l2_plane_pix_format plane_fmt; + struct v4l2_plane_pix_format plane_fmt =3D {}; int i; =20 q_data =3D mtk_jpeg_get_q_data(ctx, vb->vb2_queue->type); @@ -1312,38 +1312,51 @@ static int mtk_jpeg_probe(struct platform_device *p= dev) spin_lock_init(&jpeg->hw_lock); jpeg->dev =3D &pdev->dev; jpeg->variant =3D of_device_get_match_data(jpeg->dev); - INIT_DELAYED_WORK(&jpeg->job_timeout_work, mtk_jpeg_job_timeout_work); =20 - jpeg->reg_base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(jpeg->reg_base)) { - ret =3D PTR_ERR(jpeg->reg_base); - return ret; + ret =3D devm_of_platform_populate(&pdev->dev); + if (ret) { + v4l2_err(&jpeg->v4l2_dev, "Master of platform populate failed."); + return -EINVAL; } =20 - jpeg_irq =3D platform_get_irq(pdev, 0); - if (jpeg_irq < 0) - return jpeg_irq; + if (list_empty(&pdev->dev.devres_head)) { + INIT_DELAYED_WORK(&jpeg->job_timeout_work, + mtk_jpeg_job_timeout_work); =20 - ret =3D devm_request_irq(&pdev->dev, jpeg_irq, - jpeg->variant->irq_handler, 0, pdev->name, jpeg); - if (ret) { - dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n", - jpeg_irq, ret); - goto err_req_irq; - } + jpeg->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(jpeg->reg_base)) { + ret =3D PTR_ERR(jpeg->reg_base); + return ret; + } =20 - ret =3D devm_clk_bulk_get(jpeg->dev, jpeg->variant->num_clks, - jpeg->variant->clks); - if (ret) { - dev_err(&pdev->dev, "Failed to init clk, err %d\n", ret); - goto err_clk_init; + jpeg_irq =3D platform_get_irq(pdev, 0); + if (jpeg_irq < 0) + return jpeg_irq; + + ret =3D devm_request_irq(&pdev->dev, + jpeg_irq, + jpeg->variant->irq_handler, + 0, + pdev->name, jpeg); + if (ret) { + dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n", + jpeg_irq, ret); + return ret; + } + + ret =3D devm_clk_bulk_get(jpeg->dev, + jpeg->variant->num_clks, + jpeg->variant->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } } =20 ret =3D v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev); if (ret) { dev_err(&pdev->dev, "Failed to register v4l2 device\n"); - ret =3D -EINVAL; - goto err_dev_register; + return -EINVAL; } =20 jpeg->m2m_dev =3D v4l2_m2m_init(jpeg->variant->m2m_ops); @@ -1401,12 +1414,6 @@ static int mtk_jpeg_probe(struct platform_device *pd= ev) err_m2m_init: v4l2_device_unregister(&jpeg->v4l2_dev); =20 -err_dev_register: - -err_clk_init: - -err_req_irq: - return ret; } =20 @@ -1497,6 +1504,7 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata= =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, }; =20 +#if defined(CONFIG_OF) static const struct of_device_id mtk_jpeg_match[] =3D { { .compatible =3D "mediatek,mt8173-jpgdec", @@ -1514,13 +1522,14 @@ static const struct of_device_id mtk_jpeg_match[] = =3D { }; =20 MODULE_DEVICE_TABLE(of, mtk_jpeg_match); +#endif =20 static struct platform_driver mtk_jpeg_driver =3D { .probe =3D mtk_jpeg_probe, .remove =3D mtk_jpeg_remove, .driver =3D { .name =3D MTK_JPEG_NAME, - .of_match_table =3D mtk_jpeg_match, + .of_match_table =3D of_match_ptr(mtk_jpeg_match), .pm =3D &mtk_jpeg_pm_ops, }, }; diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.h index 3e4811a41ba2..1e0ba466303b 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -9,6 +9,7 @@ #ifndef _MTK_JPEG_CORE_H #define _MTK_JPEG_CORE_H =20 +#include #include #include #include @@ -74,6 +75,40 @@ struct mtk_jpeg_variant { u32 cap_q_default_fourcc; }; =20 +enum mtk_jpegenc_hw_id { + MTK_JPEGENC_HW0, + MTK_JPEGENC_HW1, + MTK_JPEGENC_HW_MAX, +}; + +/** + * struct mtk_jpegenc_clk - Structure used to store vcodec clock informati= on + * @clks: JPEG encode clock + * @clk_num: JPEG encode clock numbers + */ +struct mtk_jpegenc_clk { + struct clk_bulk_data *clks; + int clk_num; +}; + +/** + * struct mtk_jpegenc_comp_dev - JPEG COREX abstraction + * @dev: JPEG device + * @plat_dev: platform device data + * @reg_base: JPEG registers mapping + * @master_dev: mtk_jpeg_dev device + * @venc_clk: jpeg encode clock + * @jpegenc_irq: jpeg encode irq num + */ +struct mtk_jpegenc_comp_dev { + struct device *dev; + struct platform_device *plat_dev; + void __iomem *reg_base; + struct mtk_jpeg_dev *master_dev; + struct mtk_jpegenc_clk venc_clk; + int jpegenc_irq; +}; + /** * struct mtk_jpeg_dev - JPEG IP abstraction * @lock: the mutex protecting this structure @@ -87,6 +122,9 @@ struct mtk_jpeg_variant { * @reg_base: JPEG registers mapping * @job_timeout_work: IRQ timeout structure * @variant: driver variant to be used + * @reg_encbase: jpg encode register base addr + * @enc_hw_dev: jpg encode hardware device + * @is_jpgenc_multihw: the flag of multi-hw core */ struct mtk_jpeg_dev { struct mutex lock; @@ -100,6 +138,10 @@ struct mtk_jpeg_dev { void __iomem *reg_base; struct delayed_work job_timeout_work; const struct mtk_jpeg_variant *variant; + + void __iomem *reg_encbase[MTK_JPEGENC_HW_MAX]; + struct mtk_jpegenc_comp_dev *enc_hw_dev[MTK_JPEGENC_HW_MAX]; + bool is_jpgenc_multihw; }; =20 /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 368f512ea86e..3dcf83d6d95e 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -5,11 +5,27 @@ * */ =20 +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include =20 +#include "mtk_jpeg_core.h" #include "mtk_jpeg_enc_hw.h" =20 static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] =3D { @@ -30,6 +46,16 @@ static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_qualit= y[] =3D { {.quality_param =3D 97, .hardware_value =3D JPEG_ENC_QUALITY_Q97}, }; =20 +#if defined(CONFIG_OF) +static const struct of_device_id mtk_jpegenc_drv_ids[] =3D { + { + .compatible =3D "mediatek,mt8195-jpgenc-hw", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids); +#endif + void mtk_jpeg_enc_reset(void __iomem *base) { writel(0, base + JPEG_ENC_RSTB); @@ -158,3 +184,138 @@ void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx= , void __iomem *base) writel(ctx->restart_interval, base + JPEG_ENC_RST_MCU_NUM); } EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_params); + +static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) +{ + struct vb2_v4l2_buffer *src_buf, *dst_buf; + enum vb2_buffer_state buf_state; + struct mtk_jpeg_ctx *ctx; + u32 result_size; + u32 irq_status; + + struct mtk_jpegenc_comp_dev *jpeg =3D priv; + struct mtk_jpeg_dev *master_jpeg =3D jpeg->master_dev; + + irq_status =3D readl(jpeg->reg_base + JPEG_ENC_INT_STS) & + JPEG_ENC_INT_STATUS_MASK_ALLIRQ; + if (irq_status) + writel(0, jpeg->reg_base + JPEG_ENC_INT_STS); + if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) + return IRQ_NONE; + + ctx =3D v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev); + if (!ctx) { + v4l2_err(&master_jpeg->v4l2_dev, "Context is NULL\n"); + return IRQ_HANDLED; + } + + src_buf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst_buf =3D v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + + result_size =3D mtk_jpeg_enc_get_file_size(jpeg->reg_base); + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); + buf_state =3D VB2_BUF_STATE_DONE; + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); + v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx); + pm_runtime_put(ctx->jpeg->dev); + + return IRQ_HANDLED; +} + +static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev) +{ + struct platform_device *pdev =3D dev->plat_dev; + int ret; + + dev->jpegenc_irq =3D platform_get_irq(pdev, 0); + if (dev->jpegenc_irq < 0) + return dev->jpegenc_irq; + + ret =3D devm_request_irq(&pdev->dev, + dev->jpegenc_irq, + mtk_jpegenc_hw_irq_handler, + 0, + pdev->name, dev); + if (ret) { + dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)", + dev->jpegenc_irq, ret); + return ret; + } + + return 0; +} + +static int mtk_jpegenc_hw_probe(struct platform_device *pdev) +{ + struct mtk_jpegenc_clk *jpegenc_clk; + struct mtk_jpeg_dev *master_dev; + struct mtk_jpegenc_comp_dev *dev; + int ret, i; + + struct device *decs =3D &pdev->dev; + + if (!decs->parent) + return -EPROBE_DEFER; + + master_dev =3D dev_get_drvdata(decs->parent); + if (!master_dev) + return -EPROBE_DEFER; + + dev =3D devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->plat_dev =3D pdev; + dev->dev =3D &pdev->dev; + + if (!master_dev->is_jpgenc_multihw) { + master_dev->is_jpgenc_multihw =3D true; + for (i =3D 0; i < MTK_JPEGENC_HW_MAX; i++) + master_dev->enc_hw_dev[i] =3D NULL; + } + + jpegenc_clk =3D &dev->venc_clk; + + jpegenc_clk->clk_num =3D devm_clk_bulk_get_all(&pdev->dev, + &jpegenc_clk->clks); + if (jpegenc_clk->clk_num < 0) + return dev_err_probe(&pdev->dev, jpegenc_clk->clk_num, + "Failed to get jpegenc clock count\n"); + + dev->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dev->reg_base)) + return PTR_ERR(dev->reg_base); + + ret =3D mtk_jpegenc_hw_init_irq(dev); + if (ret) + return ret; + + for (i =3D 0; i < MTK_JPEGENC_HW_MAX; i++) { + if (master_dev->enc_hw_dev[i]) + continue; + + master_dev->enc_hw_dev[i] =3D dev; + master_dev->reg_encbase[i] =3D dev->reg_base; + dev->master_dev =3D master_dev; + } + + platform_set_drvdata(pdev, dev); + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static struct platform_driver mtk_jpegenc_hw_driver =3D { + .probe =3D mtk_jpegenc_hw_probe, + .driver =3D { + .name =3D "mtk-jpegenc-hw", + .of_match_table =3D of_match_ptr(mtk_jpegenc_drv_ids), + }, +}; + +module_platform_driver(mtk_jpegenc_hw_driver); + +MODULE_DESCRIPTION("MediaTek JPEG encode HW driver"); +MODULE_LICENSE("GPL"); --=20 2.18.0