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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id o18-20020a2e7312000000b00268bc2c1ed0sm191592ljc.22.2022.09.27.08.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 08:34:39 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 02/12] arm64: dts: qcom: sc7280: align LPASS pin configuration with DT schema Date: Tue, 27 Sep 2022 17:34:19 +0200 Message-Id: <20220927153429.55365-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927153429.55365-1-krzysztof.kozlowski@linaro.org> References: <20220927153429.55365-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects LPASS pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 8823b75a6f1b..28e3fb9992d9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2432,82 +2432,82 @@ lpass_tlmm: pinctrl@33c0000 { #gpio-cells =3D <2>; gpio-ranges =3D <&lpass_tlmm 0 0 15>; =20 - lpass_dmic01_clk: dmic01-clk { + lpass_dmic01_clk: dmic01-clk-state { pins =3D "gpio6"; function =3D "dmic1_clk"; }; =20 - lpass_dmic01_clk_sleep: dmic01-clk-sleep { + lpass_dmic01_clk_sleep: dmic01-clk-sleep-state { pins =3D "gpio6"; function =3D "dmic1_clk"; }; =20 - lpass_dmic01_data: dmic01-data { + lpass_dmic01_data: dmic01-data-state { pins =3D "gpio7"; function =3D "dmic1_data"; }; =20 - lpass_dmic01_data_sleep: dmic01-data-sleep { + lpass_dmic01_data_sleep: dmic01-data-sleep-state { pins =3D "gpio7"; function =3D "dmic1_data"; }; =20 - lpass_dmic23_clk: dmic23-clk { + lpass_dmic23_clk: dmic23-clk-state { pins =3D "gpio8"; function =3D "dmic2_clk"; }; =20 - lpass_dmic23_clk_sleep: dmic23-clk-sleep { + lpass_dmic23_clk_sleep: dmic23-clk-sleep-state { pins =3D "gpio8"; function =3D "dmic2_clk"; }; =20 - lpass_dmic23_data: dmic23-data { + lpass_dmic23_data: dmic23-data-state { pins =3D "gpio9"; function =3D "dmic2_data"; }; =20 - lpass_dmic23_data_sleep: dmic23-data-sleep { + lpass_dmic23_data_sleep: dmic23-data-sleep-state { pins =3D "gpio9"; function =3D "dmic2_data"; }; =20 - lpass_rx_swr_clk: rx-swr-clk { + lpass_rx_swr_clk: rx-swr-clk-state { pins =3D "gpio3"; function =3D "swr_rx_clk"; }; =20 - lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep-state { pins =3D "gpio3"; function =3D "swr_rx_clk"; }; =20 - lpass_rx_swr_data: rx-swr-data { + lpass_rx_swr_data: rx-swr-data-state { pins =3D "gpio4", "gpio5"; function =3D "swr_rx_data"; }; =20 - lpass_rx_swr_data_sleep: rx-swr-data-sleep { + lpass_rx_swr_data_sleep: rx-swr-data-sleep-state { pins =3D "gpio4", "gpio5"; function =3D "swr_rx_data"; }; =20 - lpass_tx_swr_clk: tx-swr-clk { + lpass_tx_swr_clk: tx-swr-clk-state { pins =3D "gpio0"; function =3D "swr_tx_clk"; }; =20 - lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep-state { pins =3D "gpio0"; function =3D "swr_tx_clk"; }; =20 - lpass_tx_swr_data: tx-swr-data { + lpass_tx_swr_data: tx-swr-data-state { pins =3D "gpio1", "gpio2", "gpio14"; function =3D "swr_tx_data"; }; =20 - lpass_tx_swr_data_sleep: tx-swr-data-sleep { + lpass_tx_swr_data_sleep: tx-swr-data-sleep-state { pins =3D "gpio1", "gpio2", "gpio14"; function =3D "swr_tx_data"; }; --=20 2.34.1