From nobody Tue Dec 16 19:42:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19C71C6FA8E for ; Tue, 27 Sep 2022 11:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231871AbiI0LVV (ORCPT ); Tue, 27 Sep 2022 07:21:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231292AbiI0LUZ (ORCPT ); Tue, 27 Sep 2022 07:20:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27A34F6AE; Tue, 27 Sep 2022 04:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277623; x=1695813623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lT0bVFe59r0LZtVlbhkUSjAZd0dwPCr+Kqah6r2WiU8=; b=Rkf630tSzgnH3UiXWkqMiopnFWtGAuPghs15K1W7xIKannd/KTKBDzbD 0l1x/2ExQCBA/9t26ZwL28S8lRJVmnZ0X7NurHdehJ1JOUnK5rCtDpcek ndLVoTzDo7i8ySzrOszn8bTltPFrRn1tri8XPGakDHh9WZCWLOAO1ZzJ2 NNpU/nc+OtJENQl2rMou1MGgEdmjbAwAHCVJqyoR3CbkY4znfwua+4hbc cwAAb0M15jc5j3gjI6gfuiRhYgNyIMvtljvku5k3CWpdCVdJFrL3o6P+9 cxerS+3BhLlTGU+58wPsG1oO7/Fxhd8vRYLhcF5U5nIf6DkK6W9V9oLiA w==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094369" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:11 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties Date: Tue, 27 Sep 2022 12:19:18 +0100 Message-ID: <20220927111922.3602838-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 688ef0fc5a64..9ca2ac4ad8e2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -38,13 +38,13 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; =20 - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; #interrupt-cells =3D <0x1>; #size-cells =3D <0x2>; device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg =3D <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names =3D "cfg", "apb"; bus-range =3D <0x0 0x7f>; interrupt-parent =3D <&plic>; @@ -54,9 +54,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks =3D <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent =3D <&pcie>; msi-controller; --=20 2.37.3