From nobody Tue Dec 16 19:43:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F988C6FA92 for ; Tue, 27 Sep 2022 11:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbiI0LVS (ORCPT ); Tue, 27 Sep 2022 07:21:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbiI0LUX (ORCPT ); Tue, 27 Sep 2022 07:20:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C0BFB6023; Tue, 27 Sep 2022 04:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277622; x=1695813622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jGJip5ceUu4A8yJeV6ZmwmmFZ9D61ZjQ1AOYwFa+oXk=; b=07VgAKWacXhY62Xr2soybFfxMekSJQCcbLNb5TQmKKw+wYC5liRqROQ8 3c1ZaHLultvFYHlyTAeKPvCMXVrbzy3Jmj38oUEOCPhemZbSwW3qnHgM5 WWSK6z9UvTTFzVT5R6oKvz0cMschHDAh+GbNHsDKpeTslsOj5UFTp9MI/ ip+2rAZqbjn+wS9MXqyi/C1ZAR+ns/YnArcIF40FF7eOX0tvfSvOjrkNw IHpnm4+U/jIGKihqPjeVA2b0dvBlgCguXRn2ldzeDmMxxcd0iEm7jXGaO QRAFS2w94rVx9xfljLDN3NMJH70Wpr8i4/Ek49v2bR3ifjWogPiqhn7g8 g==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094355" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:06 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Tue, 27 Sep 2022 12:19:16 +0100 Message-ID: <20220927111922.3602838-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Since this change is not backwards compatible, update the compatible to denote this, jumping over v2022.09 directly to v2022.10. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..eec5aba43436 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; }; + +&pcie { + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 044982a11df5..42d350fe6c6b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 aliases { ethernet0 =3D &mac1; --=20 2.37.3