From nobody Sat Sep 21 17:18:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 948C6C6FA83 for ; Tue, 27 Sep 2022 10:12:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231935AbiI0KMY (ORCPT ); Tue, 27 Sep 2022 06:12:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231903AbiI0KLs (ORCPT ); Tue, 27 Sep 2022 06:11:48 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81435A3D45; Tue, 27 Sep 2022 03:11:44 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 012F7660226D; Tue, 27 Sep 2022 11:11:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1664273503; bh=j10EM1licQi3mwiHxVGMv2C3ETIprP9h+07XKCWj8yU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SeEHD7Dy/8p+JvKSviqAASCFXO0+8JJpOmthAYvFDZuj/qSeJ/VxtDlxlR5kolctd vcjE0ynnqL3l9mT9iyILH703RrbpLXQcjrju3bVuylMGf2RiM88wNI7F7jl2x0m+ww IBWxTIbOJQhGHhTbaVPsV6Ti9zppp4LVX03LAZKaJmRBYoyM8lKF4G213GQdsaqBs3 +xUjJWBdbv84gMtZfAt/DhP9bi8J+Lb8+E/KJK1PRJQzmTn443/FBDV3F3zuuaIivi /F2+xuxMANS7LvR65PRV2Kuw3rMg3ManSkjp4UN6QDTsN/Yn/4SZypmg03ProLVSKC sme0M/AzV8ASg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH v3 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents Date: Tue, 27 Sep 2022 12:11:26 +0200 Message-Id: <20220927101128.44758-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com> References: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 4dde23bece66..8cbab5ca2e58 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -298,11 +298,14 @@ static const char * const ipu_if_parents[] =3D { "mmpll_d4" }; =20 +/* + * MFG can be also parented to "univpll_d6" and "univpll_d7": + * these have been removed from the parents list to let us + * achieve GPU DVFS without any special clock handlers. + */ static const char * const mfg_parents[] =3D { "clk26m", - "mainpll_d5_d2", - "univpll_d6", - "univpll_d7" + "mainpll_d5_d2" }; =20 static const char * const camtg_parents[] =3D { --=20 2.37.2