From nobody Sat Sep 21 16:55:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C751AC54EE9 for ; Tue, 27 Sep 2022 10:12:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231983AbiI0KMT (ORCPT ); Tue, 27 Sep 2022 06:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231905AbiI0KLs (ORCPT ); Tue, 27 Sep 2022 06:11:48 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8494B07C9; Tue, 27 Sep 2022 03:11:46 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 551EA660226E; Tue, 27 Sep 2022 11:11:44 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1664273505; bh=5IWI64htpEUd32LavmbW5vcTEzgbRV3GoZjikO26riQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=avjHok5TrFI3/972JFn0CVpzlKvuEqyFdFWvlvd7I+U9ARrLUoA/uhao8tEgHNM0E SwfUKz4UcLFxm4XcH9L4zAheamC218jaUOER+Ixa/5demwgbQN1YOvgtDW5dL2Pmu5 Phz3pBPw1Fpj+q6msB0S80OE8PFfg2nSyvGtT0KJbX/Qq2zyhJPjrUD6puh7yOHqFY w46u7ZW+QrIvwUyKEUPc485MWr48eby8CBc/aRS6mqqoQxnsrCsvX2iqhUl783JTzg sEBY1R5p4V7e2uu7T5lCJmBllWttBGqVjGZXLBuFB0W5WJSMFGBHiMi99zLAsydqYb 0B9hvheXY2J4g== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH v3 10/10] clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel Date: Tue, 27 Sep 2022 12:11:28 +0200 Message-Id: <20220927101128.44758-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com> References: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8192.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index ebbd2798d9a3..187dbffeb987 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1224,6 +1224,28 @@ static void clk_mt8192_top_init_early(struct device_= node *node) CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", clk_mt8192_top_init_early); =20 +/* Register mux notifier for MFG mux */ +static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + int i; + + mfg_mux_nb =3D devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(top_mtk_muxes); i++) + if (top_mtk_muxes[i].id =3D=3D CLK_TOP_MFG_PLL_SEL) + break; + if (i =3D=3D ARRAY_SIZE(top_mtk_muxes)) + return -EINVAL; + + mfg_mux_nb->ops =3D top_mtk_muxes[i].ops; + mfg_mux_nb->bypass_index =3D 0; /* Bypass to 26M crystal */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + static int clk_mt8192_top_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -1247,6 +1269,12 @@ static int clk_mt8192_top_probe(struct platform_devi= ce *pdev) if (r) return r; =20 + r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, + top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); + if (r) + return r; + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); } --=20 2.37.2