From nobody Sat Sep 21 14:17:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27D33C54EE9 for ; Tue, 27 Sep 2022 08:39:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229977AbiI0Ijr (ORCPT ); Tue, 27 Sep 2022 04:39:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230445AbiI0Ijl (ORCPT ); Tue, 27 Sep 2022 04:39:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9C7418B33 for ; Tue, 27 Sep 2022 01:39:34 -0700 (PDT) X-UUID: c636732f6011483792102331b92e0b00-20220927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=ybSkKRjrYUZT0xTirHZg3dFqDX4pBEgxXhWL0FLGGsU=; b=KJfNFGi861MLCNpReUan6RwVutYXPbd4zLuFEdMs3LGaSQcXVbQCA73X7F++St/6PDrB6IhaPPb0/x2dUnYHJWdydnRVqhQvY89b5plt9zQHFjAuUCC3osp167fPqra2pQbpb5ieOXxDjsoAJzk+YEm1IWLdQocTeENlqwI9ebA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:58c6c8e8-7cc6-42db-9e83-efd88c2ba052,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:523537a3-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c636732f6011483792102331b92e0b00-20220927 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1881899188; Tue, 27 Sep 2022 16:39:29 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 27 Sep 2022 16:39:27 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 16:39:27 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v5] mailbox: mtk-cmdq: fix gce timeout issue Date: Tue, 27 Sep 2022 16:39:25 +0800 Message-ID: <20220927083925.28433-1-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. enable gce ddr enable(gce reigster offset 0x48, bit 16 to 18) when gce w= ork, and disable gce ddr enable when gce work job done 2. add cmdq ddr enable/disable api, and control gce ddr enable/disable to make sure it could protect when cmdq is multiple used by display and mdp this is only for some SOC which has flag "gce_ddr_en". for this kind of gce, there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. ddr problem is a special case. when test suspend/resume case, gce sometimes will pull ddr, and ddr can not go to suspend. if we set gce register 0x48 to 0x7, will fix this gce pull ddr issue, as you have referred [1] and [2] (8192 and 8195) but for mt8186, the gce is more special, except setting of [1] and [2], we need add more setting set gce register 0x48 to (0x7 << 16 | 0x7) when gce working to make sure gce could process all instructions ok. this case just need normal bootup, if we not set this, display cmdq task will timeout, and chrome homescreen will always black screen. and with this patch, we have done these test on mt8186: 1.suspend/resume 2.boot up to home screen 3.playback video with youtube. suspend issue is special gce hardware issue, gce client driver command already process done, but gce still pull ddr. Signed-off-by: Yongqiang Niu --- change since v4: 1. remove spin lock control flow 2. move ddr control into suspend/resume/remove function --- --- drivers/mailbox/mtk-cmdq-mailbox.c | 44 +++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 9465f9081515..e9ead72b9bd3 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -38,6 +38,8 @@ #define CMDQ_THR_PRIORITY 0x40 =20 #define GCE_GCTL_VALUE 0x48 +#define GCE_CTRL_BY_SW GENMASK(18, 16) +#define GCE_DDR_EN GENMASK(2, 0) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -80,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -87,9 +90,25 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) +{ + if (!cmdq->sw_ddr_en) + return; + + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); + + if (enable) + writel(GCE_DDR_EN + GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + else + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); +} + u8 cmdq_get_shift_pa(struct mbox_chan *chan) { struct cmdq *cmdq =3D container_of(chan->mbox, struct cmdq, mbox); @@ -129,7 +148,11 @@ static void cmdq_init(struct cmdq *cmdq) =20 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(0x7, cmdq->base + GCE_GCTL_VALUE); + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + + if (cmdq->sw_ddr_en) + writel(GCE_DDR_EN + GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -266,6 +289,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, =20 if (list_empty(&thread->task_busy_list)) { cmdq_thread_disable(cmdq, thread); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); } } @@ -311,6 +335,8 @@ static int cmdq_suspend(struct device *dev) if (task_running) dev_warn(dev, "exist running task(s) in suspend\n"); =20 + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); =20 return 0; @@ -322,6 +348,9 @@ static int cmdq_resume(struct device *dev) =20 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); cmdq->suspended =3D false; + + cmdq_sw_ddr_enable(cmdq, true); + return 0; } =20 @@ -329,6 +358,8 @@ static int cmdq_remove(struct platform_device *pdev) { struct cmdq *cmdq =3D platform_get_drvdata(pdev); =20 + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); return 0; } @@ -468,6 +499,7 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsi= gned long timeout) =20 cmdq_thread_resume(thread); cmdq_thread_disable(cmdq, thread); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); =20 out: @@ -543,6 +575,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr =3D plat_data->thread_nr; cmdq->shift_pa =3D plat_data->shift; cmdq->control_by_sw =3D plat_data->control_by_sw; + cmdq->sw_ddr_en =3D plat_data->sw_ddr_en; cmdq->gce_num =3D plat_data->gce_num; cmdq->irq_mask =3D GENMASK(cmdq->thread_nr - 1, 0); err =3D devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, @@ -660,9 +693,18 @@ static const struct gce_plat gce_plat_v6 =3D { .gce_num =3D 2 }; =20 +static const struct gce_plat gce_plat_v7 =3D { + .thread_nr =3D 24, + .shift =3D 3, + .control_by_sw =3D true, + .sw_ddr_en =3D true, + .gce_num =3D 1 +}; + static const struct of_device_id cmdq_of_ids[] =3D { {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_v2}, {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_v3}, + {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_v7}, {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_v4}, {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_v5}, {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_v6}, --=20 2.25.1