From nobody Mon Apr 6 13:30:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6668CC6FA82 for ; Mon, 26 Sep 2022 18:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiIZSiR (ORCPT ); Mon, 26 Sep 2022 14:38:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229957AbiIZShp (ORCPT ); Mon, 26 Sep 2022 14:37:45 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C573E67445; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=guTQUyIY3Ak74CaPrHeNLBZ+hPVciKbJ6JW4ThPI6EE=; b=wkF7ieiwQQIoTHYfp0GEjpgjiE VAIHPVje++9TPaVC0Lr2L6bxjJiWTnml8+sFg8S9gyG1sv/6mtkhD/apAEJM9tKyRsMa4fLMwGGan /e5rCkBEfBrjK5xqERdTXvzJXKZgeBGECPZ6A3+NCrhHBBdhP4s1SDyBKPGO6rr+YqQD44KzfQOwA CIc8CNNrY5ITkeuu59c4AA8v7hLTDTAEYsNFyzF/H0GaNFGtKnBomImXQJzoFwmw4IynQK5CVtCtx NGftOMUA8mS897MgSK9LP65LqWybl4leNuG8nKlUpDu76CC4MDs+MOUZ7QafVj7QFekotp+cF2KF/ uagx2tCw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz4-00B9Pd-Eb; Mon, 26 Sep 2022 20:37:38 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcX-2E; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 12/13] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:26 +0200 Message-Id: <20220926183727.1893566-13-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index a595014942aa..a9092c663a6e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -96,6 +96,19 @@ simple-audio-card,codec { }; }; =20 + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie"; + enable-active-high; + gpio =3D <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc3v3_sys>; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_sys"; @@ -479,6 +492,18 @@ rgmii_phy0: ethernet-phy@0 { }; }; =20 +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_pin>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + &pinctrl { leds { led_power_pin: led-power-pin { @@ -489,6 +514,15 @@ led_work_pin: led-work-pin { }; }; =20 + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins =3D <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins =3D <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.35.1