From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E07A8C6FA8E for ; Mon, 26 Sep 2022 18:37:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230074AbiIZShu (ORCPT ); Mon, 26 Sep 2022 14:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229877AbiIZShl (ORCPT ); Mon, 26 Sep 2022 14:37:41 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B5326580D; Mon, 26 Sep 2022 11:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=wn2dlv+AAhjXeFbTWc4zcB3btHAdOPL9MKl20QyJBys=; b=MoWc2PAYvN8ybarCHs3475q4tz eRELGyZSuS+1N2xbEzJq654ZZ7lV2b7WGyjZRhlkb5H/XGHDx0YtuoLNoZkriIS2qHjFok9r/IzcQ Ny7X0r1Ic+z9onbihF+FvdWrw1Rmn/YRCNaZ5mO6nng7NSGKAY/JjaPL9kUG0zyfs4u1PJyvbIIuD 8k4JhcSUbODqJuLwxiXtDZFE/TG6iA50bMsxCscvkY8AYRWo5fdFfk7xHJGXoH7Ziw2TwqjTnK/XL ty3PoctHxSF7wkPmxSPDCZNBB4MvJNhFdASDsq4wx+m/zyEJnWbEWW2w4fCwHmUqsCplq+RVoHA2j fPD9K1/A==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz2-00B9PS-FC; Mon, 26 Sep 2022 20:37:36 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wbq-1I; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Rob Herring Subject: [PATCH v2 01/13] dt-bindings: rockchip: Add Hardkernel ODROID-M1 board Date: Mon, 26 Sep 2022 20:37:15 +0200 Message-Id: <20220926183727.1893566-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dongjin Kim Add device tree binding for Hardkernel ODROID-M1 board based on RK3568 SoC. Signed-off-by: Dongjin Kim Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 7811ba64149c..d25a8a0bb2b5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -688,6 +688,11 @@ properties: - const: rockchip,rk3568-bpi-r2pro - const: rockchip,rk3568 =20 + - description: Rockchip RK3568 Hardkernel ODROID-M1 + items: + - const: rockchip,rk3568-odroid-m1 + - const: rockchip,rk3568 + additionalProperties: true =20 ... --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDA2FC6FA82 for ; Mon, 26 Sep 2022 18:38:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbiIZSiZ (ORCPT ); Mon, 26 Sep 2022 14:38:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230001AbiIZShr (ORCPT ); Mon, 26 Sep 2022 14:37:47 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A5C6AA18; Mon, 26 Sep 2022 11:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=UcRFvY9VNq3Tpx8WwH4iQb0zPwQzbGxDBjB49BDEeiQ=; b=znfAGLQmP+5qNN+BAwntNLiSpg 9dugiSn0sBfQDWUvmlODoQGUBOPF1ZdBn4x32HXzyByw8jNdvMHxoOy9yJCMC+Mp5ADkzNEXboKJ0 NMcCIISNc181Y32gG+7h9j5ikC3g9i/DFc7tWTlWHg9h+nZDtR8k+nQ/72Yux+JLnvOzZvcX70oL2 l2kqv1+gP/JPcvNkMw/3RFgXeZCiDMMXhorcqtBzpqFWCw3Fi5shRHn617+X8Cd+X9DBo5BSQ5bJW bavykSKjkjI2I86quxJ0pftyyGkH69RPCP4XOUgW1eB+3xw88n1XLVTEmlcXLGnpv9bKS0BG7WzcG x1F4UQpg==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PT-0o; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wbu-1O; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 02/13] arm64: dts: rockchip: Add Hardkernel ODROID-M1 board Date: Mon, 26 Sep 2022 20:37:16 +0200 Message-Id: <20220926183727.1893566-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dongjin Kim This patch is to add a device tree for new board Hardkernel ODROID-M1 based on Rockchip RK3568, includes basic peripherals - uart/eMMC/uSD/i2c and on-board ethernet. Signed-off-by: Dongjin Kim [aurelien@aurel32.net: addressed issues from initial review] Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 414 ++++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index ef79a672804a..12e2ef73fe80 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -66,3 +66,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts new file mode 100644 index 000000000000..b3016437640b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model =3D "Hardkernel ODROID-M1"; + compatible =3D "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; + + aliases { + ethernet0 =3D &gmac0; + i2c0 =3D &i2c3; + i2c3 =3D &i2c0; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc0; + serial0 =3D &uart1; + serial1 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + leds { + compatible =3D "gpio-leds"; + + led_power: led-0 { + gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_POWER; + color =3D ; + default-state =3D "keep"; + linux,default-trigger =3D "default-on"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_power_pin>; + }; + led_work: led-1 { + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_HEARTBEAT; + color =3D ; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_work_pin>; + }; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks =3D <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents =3D <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + phy-mode =3D "rgmii"; + phy-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status =3D "okay"; + + tx_delay =3D <0x4f>; + rx_delay =3D <0x2d>; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int_l>; + rockchip,system-power-controller; + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + leds { + led_power_pin: led-power-pin { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_work_pin: led-work-pin { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstn= out>; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22AF3C32771 for ; Mon, 26 Sep 2022 18:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230014AbiIZSih (ORCPT ); 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Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PU-3a; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wby-1T; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 03/13] arm64: dts: rockchip: add thermal support to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:17 +0200 Message-Id: <20220926183727.1893566-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the thermal nodes for the ODROID-M1. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index b3016437640b..112c65af3f55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -409,6 +409,12 @@ &sdmmc0 { status =3D "okay"; }; =20 +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + &uart2 { status =3D "okay"; }; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCDCAC6FA82 for ; Mon, 26 Sep 2022 18:38:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbiIZSiB (ORCPT ); Mon, 26 Sep 2022 14:38:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbiIZSho (ORCPT ); Mon, 26 Sep 2022 14:37:44 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EC0B6580D; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=6c+pv0oZJZdbxbzQ9QgG2de+M6SrcJe4oUVVauEVHWI=; b=Mz+MZFhTNTARfDVghkIAcVb0vP LKCz8yR0bfxlgjwwyLX/9UUOV3zVZVBOfeO99ha3yFn57hTIdIb9YLeGXCCrlK6i/nHsdVfJ8tUV5 /rcOAXVPT2OaVo5nKidpSysT75OaX7feF5E1g7NEQ7VrhRkgUi9MVUe1MqoSZl9wSg5MnIUZVVx7h 0z9F0BfpQRM+FNCvLOfWt7uFLcYWNkgmuObrPqXvNDji7ikrUd7KvhgvNO19b0+U1iV1DS13wiIJ3 ZZpPmjL0sqmtbKU0iVzMOkvsFxXjN9LZL0V46n8nMXPxAOUueJkgQrJTf07hmPC6lcqC1SRuVFy7i sEzyhG7w==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PV-6V; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wc1-1Y; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 04/13] arm64: dts: rockchip: Add NOR flash to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:18 +0200 Message-Id: <20220926183727.1893566-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Rockchip Serial Flash Controller for the ODROID-M1 and add the corresponding SPI NOR flash entry. The partitions addresses and sizes are taken from the ODROID-M1 Partition Table page on the ODROID wiki. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 112c65af3f55..877b9515ad98 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -409,6 +409,49 @@ &sdmmc0 { status =3D "okay"; }; =20 +&sfc { + pinctrl-0 =3D <&fspi_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <24000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "SPL"; + reg =3D <0x0 0xe0000>; + }; + partition@e0000 { + label =3D "U-Boot Env"; + reg =3D <0xe0000 0x20000>; + }; + partition@100000 { + label =3D "U-Boot"; + reg =3D <0x100000 0x200000>; + }; + partition@300000 { + label =3D "splash"; + reg =3D <0x300000 0x100000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x400000 0xc00000>; + }; + }; + }; +}; + &tsadc { rockchip,hw-tshut-mode =3D <1>; rockchip,hw-tshut-polarity =3D <0>; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AFE1C6FA82 for ; Mon, 26 Sep 2022 18:38:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230345AbiIZSiF (ORCPT ); Mon, 26 Sep 2022 14:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229933AbiIZShp (ORCPT ); Mon, 26 Sep 2022 14:37:45 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94E936714B; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=C74rqivx+N+6zuXC/egdmBHbQEJxHH+CvqYoF/RHe8Y=; b=RifnPLG0VWe/0BtO0Lnr66d6bS jI6B4TpkDV98xItnvFto5xcI8NQj9sz98UPxEZUQwFlE+BpAgHW+5XdFSjXHuu/Tiw4QrchXb0djH ulPi5WfxcQ7y6JvfYT8jansjm1Z8RYVcxkWOrbO88wNNBY6pXPC/xVCxVJR4E90zGxQMj9w4OYmwM 9jjM0VWpTIOvvFObc/NSlJPI9DRLxkS977xSzPBMkf1dIfUhGsuCwYZJMHiwLUuv7V+NtUJDeJ8nI 5wIOIG2f5KQjqIcpzgkcDjWQEFDMnPOq37t7Y7r4h6ho1U1+7M8BbQvbfmUhaIeqe9G2ZT5XoCAnf 66ToPTnw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PW-8V; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wc6-1e; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 05/13] arm64: dts: rockchip: Add analog audio on ODROID-M1 Date: Mon, 26 Sep 2022 20:37:19 +0200 Message-Id: <20220926183727.1893566-6-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the ODROID-M1, the I2S1 TDM controller is connected to the rk809 codec in I2S mode. It is used to provide a stereo headphones output and a mono speaker output. A GPIO with an external pullup is used as an headphone detection input. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 43 ++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 877b9515ad98..3079abbec5dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -59,6 +59,31 @@ led_work: led-1 { }; }; =20 + rk809-sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_det_pin>; + simple-audio-card,name =3D "Analog RK817"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,hp-det-gpio =3D <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,widgets =3D + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing =3D + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai =3D <&rk809>; + }; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_sys"; @@ -131,10 +156,15 @@ rk809: pmic@20 { reg =3D <0x20>; interrupt-parent =3D <&gpio0>; interrupts =3D ; + assigned-clocks =3D <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents =3D <&cru CLK_I2S1_8CH_TX>; #clock-cells =3D <1>; + clock-names =3D "mclk"; + clocks =3D <&cru I2S1_MCLKOUT_TX>; pinctrl-names =3D "default"; - pinctrl-0 =3D <&pmic_int_l>; + pinctrl-0 =3D <&pmic_int_l>, <&i2s1m0_mclk>; rockchip,system-power-controller; + #sound-dai-cells =3D <0>; vcc1-supply =3D <&vcc3v3_sys>; vcc2-supply =3D <&vcc3v3_sys>; vcc3-supply =3D <&vcc3v3_sys>; @@ -340,6 +370,11 @@ regulator-state-mem { }; }; =20 +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status =3D "okay"; +}; + &mdio0 { rgmii_phy0: ethernet-phy@0 { compatible =3D "ethernet-phy-ieee802.3-c22"; @@ -365,6 +400,12 @@ pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + rk809 { + hp_det_pin: hp-det-pin { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pmu_io_domains { --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 748C6C6FA8E for ; Mon, 26 Sep 2022 18:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231179AbiIZSi3 (ORCPT ); Mon, 26 Sep 2022 14:38:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230002AbiIZShr (ORCPT ); Mon, 26 Sep 2022 14:37:47 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36DB06B8C6; Mon, 26 Sep 2022 11:37:45 -0700 (PDT) DKIM-Signature: v=1; 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Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 06/13] arm64: dts: rockchip: Enable vop2 and hdmi tx on ODROID-M1 Date: Mon, 26 Sep 2022 20:37:20 +0200 Message-Id: <20220926183727.1893566-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the RK356x Video Output Processor (VOP) 2 on ODROID M1. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 3079abbec5dc..a7077d159099 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "rk3568.dtsi" =20 / { @@ -37,6 +38,17 @@ dc_12v: dc-12v-regulator { regulator-max-microvolt =3D <12000000>; }; =20 + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -131,6 +143,24 @@ &gmac0_rgmii_clk rx_delay =3D <0x2d>; }; =20 +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + &i2c0 { status =3D "okay"; =20 @@ -502,3 +532,20 @@ &tsadc { &uart2 { status =3D "okay"; }; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90BB6C32771 for ; Mon, 26 Sep 2022 18:38:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229682AbiIZSiU (ORCPT ); Mon, 26 Sep 2022 14:38:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229997AbiIZShr (ORCPT ); Mon, 26 Sep 2022 14:37:47 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A7AE6AEBB; Mon, 26 Sep 2022 11:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=aXxuht31ENiCKS8lMo5oW78O/VnDrXq1XV/X5vPEVVk=; b=oLXEz85Y75QEKbttjK259qMj/2 5N2ZDFKtkpKG1xnva9VgKjd/iQh9inAvkqtgLyhQgzWE+0zNlYtxZ4vkeazZ4CIRr4ULUUATsySSY 7+VVZ+7f/zEp9DVneMwWVoZJWJRBFo49d87zmT39S6DcvAFJVtRd7yU3N1qka18OaMMdDEh6r/ckx 4gNABwsEcMlX8H88WmL33khvz9bbK2tnLJzUzJnaAik5Jh3ocnwOO/wdqDQlCAafb2SVoaxkep0ek reMLboBbG0gj0ITR1qZzKc4UNGY07oHMqZOlcr9xhiPHZb4pkNq96xFLAMl1AZmIplSO2ih1bflbA 7Udz6t+w==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PY-DD; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcD-1o; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 07/13] arm64: dts: rockchip: Enable HDMI audio on ODROID-M1. Date: Mon, 26 Sep 2022 20:37:21 +0200 Message-Id: <20220926183727.1893566-8-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This enables the i2s0 controller and the hdmi-sound node on the ODROID-M1. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index a7077d159099..8748dbf9a772 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -161,6 +161,10 @@ hdmi_out_con: endpoint { }; }; =20 +&hdmi_sound { + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -400,6 +404,10 @@ regulator-state-mem { }; }; =20 +&i2s0_8ch { + status =3D "okay"; +}; + &i2s1_8ch { rockchip,trcm-sync-tx-only; status =3D "okay"; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9A7EC32771 for ; Mon, 26 Sep 2022 18:37:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbiIZShy (ORCPT ); Mon, 26 Sep 2022 14:37:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229826AbiIZShm (ORCPT ); Mon, 26 Sep 2022 14:37:42 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24C046714B; Mon, 26 Sep 2022 11:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=2V79ABvMxRRI/ldzFJx1RxAvUilUTQjQFT1E2OVvnlM=; b=g67+evlZ71Xyyl4r+Dk9HmrLdb +VowUgXkdoiKxqa/3olZ1t2vRBPf9EWxWlyaxtedhnhAQYMkclNALrlYKa5ePwTViOTVCfdOROX8p wu0+SOB+UT0bVsLQ9nERtfyGG/oQy/hfL3JbKBch2KZFsSmcOyrbQT41bJCtzjU81xaFBSWDvtUBu RGiiPCIryj0jiyh/1XYeHMbgipwRX2Nn7QuZrSG55br0A6WscAKSJA62RDLvIwfqapBZunVFCzUdv eIYS7Sfazr85/jIWItitFGVogDC/vhhIUgFr+PUmg2WliUCYe5fY6USpId3YfcMFwyMgaCAq9U5vC wXp9zQ1Q==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9PZ-39; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcH-1t; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 08/13] arm64: dts: rockchip: Enable the GPU on ODROID-M1 Date: Mon, 26 Sep 2022 20:37:22 +0200 Message-Id: <20220926183727.1893566-9-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the GPU core on the Rockchip RK3568 ODROID-M1. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 8748dbf9a772..281d8fdc0885 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -143,6 +143,11 @@ &gmac0_rgmii_clk rx_delay =3D <0x2d>; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + &hdmi { avdd-0v9-supply =3D <&vdda0v9_image>; avdd-1v8-supply =3D <&vcca1v8_image>; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C538CC32771 for ; Mon, 26 Sep 2022 18:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231243AbiIZSid (ORCPT ); Mon, 26 Sep 2022 14:38:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230008AbiIZShr (ORCPT ); Mon, 26 Sep 2022 14:37:47 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 836D36B8D3; Mon, 26 Sep 2022 11:37:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=kilOzW0pwUETTqeqUPsVrB9s7w7J8Zt9YgnjJdCajnk=; b=iI9i9CuIefkpcuji6V0Jtjk90n VUmdj3sZvoUZHaHS8vWZlRJzwijvlY5GfiOH8OxLRps+HgECdStL438WyrRuBhaJRaASeLDOXh4tY 8/NQEr1VEIfHWzltCPen+fQkm6D5feO3TZUasSXY5fUjp0bOQE+nnNTJjyKFiPLMDvU+2F7nrZrvQ 5jAzjDWSIeK7emjPRfgxX6ECik7WIlig9eM/b1pk6ftkn0tUfeahMdigCyvS4uWRiGaIKP8hgDAMs Hdtl6R29fTm45h/sepEFUpJnpRvlM+PY7Df0LXLpyl49nEZkWTyOUEavODXazi27gmyjv7oaD1HyC loeDZF9g==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9Pa-CB; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcM-1y; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 09/13] arm64: dts: rockchip: Enable the USB 2.0 ports on ODROID-M1 Date: Mon, 26 Sep 2022 20:37:23 +0200 Message-Id: <20220926183727.1893566-10-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Rockchip RK3568 has two USB OHCI/EHCI controllers connected to a PHY providing one host-only port and one OTG port. On the ODROID-M1, they are both used in host mode. The USB ports are powered by a DC/DC converter providing 5V and named VCC5V0_SYS on the schematics, followed by a power switch. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 281d8fdc0885..595f56c41a15 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -105,6 +105,28 @@ vcc3v3_sys: vcc3v3-sys-regulator { regulator-max-microvolt =3D <3300000>; vin-supply =3D <&dc_12v>; }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_host_en_pin>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; }; =20 &cpu0 { @@ -449,6 +471,15 @@ hp_det_pin: hp-det-pin { rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pmu_io_domains { @@ -546,6 +577,36 @@ &uart2 { status =3D "okay"; }; =20 +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + &vop { assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 458C5C32771 for ; Mon, 26 Sep 2022 18:38:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230399AbiIZSiJ (ORCPT ); Mon, 26 Sep 2022 14:38:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229974AbiIZShp (ORCPT ); Mon, 26 Sep 2022 14:37:45 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2596969F4D; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; 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Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 10/13] arm64: dts: rockchip: Enable the USB 3.0 ports on ODROID-M1 Date: Mon, 26 Sep 2022 20:37:24 +0200 Message-Id: <20220926183727.1893566-11-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Rockchip RK3568 has two USB XHCI controllers. The USB 2.0 signals are connected to a PHY providing one host-only port and one OTG port. The USB 3.0 signals are connected to two USB3.0/PCIE/SATA combo PHY. The ODROID M1 has 2 type A USB 3.0 connectors, with the USB 3.0 signals connected to the two combo PHYs. For the USB 2.0 signals, one connector is connected to the host-only PHY and uses the same power switch as the USB 2.0 ports. The other connector has its own power switch and is connected to the OTG PHY, which is also connected to a device only micro-USB connector. The purpose of this micro-USB connector is for firmware update using the Rockusb vendor specific USB class. Therefore it does not make sense to enable this port on Linux, and the PHY is forced to host mode. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 49 ++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 595f56c41a15..8f7c9dd8c47c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -127,6 +127,30 @@ vcc5v0_usb_host: vcc5v0-usb-host-regulator { regulator-max-microvolt =3D <5000000>; vin-supply =3D <&vcc5v0_sys>; }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_pin>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0 { + /* Used for USB3 */ + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&combphy1 { + /* Used for USB3 */ + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; }; =20 &cpu0 { @@ -476,7 +500,7 @@ usb { vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { + vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -585,6 +609,11 @@ &usb_host0_ohci { status =3D "okay"; }; =20 +&usb_host0_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + &usb_host1_ehci { status =3D "okay"; }; @@ -593,6 +622,24 @@ &usb_host1_ohci { status =3D "okay"; }; =20 +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + &usb2phy1 { status =3D "okay"; }; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83301C6FA8E for ; Mon, 26 Sep 2022 18:38:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230178AbiIZSiN (ORCPT ); Mon, 26 Sep 2022 14:38:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229946AbiIZShp (ORCPT ); Mon, 26 Sep 2022 14:37:45 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4F1367172; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=VGtINPdmigb+hvxoDDBg5P5cbXE3IySxZEaVA1DOgmE=; b=gpyCoZXyTfwEcD7kf9FUMZQPdT QhD4IxGfbF4f1u2XzAw4/mvwEmFofavAuS+7/dxFK8+XlRdZZ6XP0ajrspLb1IdfveBhZ/1FYQ3gb 7UuB5wAqnDCiUjEdhiReWFKDt/NuJNo6fPHco2H9Q8LmA5EIgfERK2ie7aWza1tD7DJcIZh9r634c /zY6QASkWw8V2onIa5gM0+LhnmvxmW7YccvhNOIV6qGHGIAudzf5KI4zBwN9Lpsv42GIHBfJIoBsD S8fue3MuY9JL7Rt5r3nEB+PWWkcV0An0oYxvxRR8z0Q0OP0QRIfOTisp2E4Zvlyet1xE32bdgyjiY H6q9Akjw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9Pc-FX; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcT-29; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 11/13] arm64: dts: rockchip: Add SATA support to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:25 +0200 Message-Id: <20220926183727.1893566-12-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Combo PHY and SATA nodes in ODROID-M1. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index 8f7c9dd8c47c..a595014942aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -153,6 +153,11 @@ &combphy1 { status =3D "okay"; }; =20 +&combphy2 { + /* used for SATA */ + status =3D "okay"; +}; + &cpu0 { cpu-supply =3D <&vdd_cpu>; }; @@ -524,6 +529,10 @@ &saradc { status =3D "okay"; }; =20 +&sata2 { + status =3D "okay"; +}; + &sdhci { bus-width =3D <8>; max-frequency =3D <200000000>; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6668CC6FA82 for ; Mon, 26 Sep 2022 18:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiIZSiR (ORCPT ); Mon, 26 Sep 2022 14:38:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229957AbiIZShp (ORCPT ); Mon, 26 Sep 2022 14:37:45 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C573E67445; Mon, 26 Sep 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=guTQUyIY3Ak74CaPrHeNLBZ+hPVciKbJ6JW4ThPI6EE=; b=wkF7ieiwQQIoTHYfp0GEjpgjiE VAIHPVje++9TPaVC0Lr2L6bxjJiWTnml8+sFg8S9gyG1sv/6mtkhD/apAEJM9tKyRsMa4fLMwGGan /e5rCkBEfBrjK5xqERdTXvzJXKZgeBGECPZ6A3+NCrhHBBdhP4s1SDyBKPGO6rr+YqQD44KzfQOwA CIc8CNNrY5ITkeuu59c4AA8v7hLTDTAEYsNFyzF/H0GaNFGtKnBomImXQJzoFwmw4IynQK5CVtCtx NGftOMUA8mS897MgSK9LP65LqWybl4leNuG8nKlUpDu76CC4MDs+MOUZ7QafVj7QFekotp+cF2KF/ uagx2tCw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz4-00B9Pd-Eb; Mon, 26 Sep 2022 20:37:38 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcX-2E; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 12/13] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:26 +0200 Message-Id: <20220926183727.1893566-13-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot. Signed-off-by: Aurelien Jarno --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index a595014942aa..a9092c663a6e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -96,6 +96,19 @@ simple-audio-card,codec { }; }; =20 + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie"; + enable-active-high; + gpio =3D <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc3v3_sys>; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_sys"; @@ -479,6 +492,18 @@ rgmii_phy0: ethernet-phy@0 { }; }; =20 +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_pin>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + &pinctrl { leds { led_power_pin: led-power-pin { @@ -489,6 +514,15 @@ led_work_pin: led-work-pin { }; }; =20 + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins =3D <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins =3D <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.35.1 From nobody Mon Apr 6 11:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE04C07E9D for ; Mon, 26 Sep 2022 18:38:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230401AbiIZSik (ORCPT ); Mon, 26 Sep 2022 14:38:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230025AbiIZShr (ORCPT ); Mon, 26 Sep 2022 14:37:47 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3717D6B8C9; Mon, 26 Sep 2022 11:37:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=UfzKuWJOv8eIX9wiiTT81pyTbtqfkVKUm12eKluKnrk=; b=WcmJMtBTBxXhlBwH9znoS6/EkQ b+r8vV4uLraqh1T5vD2oCIUp5VaxYCDn4hYaV/FKQBKXSKrLXtbnMKBAng9TIjk/Ewve+Saa3B2ax v9oTsxA5e6D8piOZTlxtS9tx+wiEy/ggkWBkfZ+W84sdf+cjrm7AynDHHblP0Y9BtGpB5Kr4qnPZR Q6VTN9qXe9b0BuedE8nbykauf5vtZ3mrX5N8sHfV9GME9gL39obLAn3XyYG05+X3LbTP2U0Vu5nN2 O+DoChQloXKWNWnZ2v9NtdcvGXGKeAZkYlDazdL6XH6iAmqlBO1Wk6yEgXpNhVui7POAJcbYsyApM NFi0lvug==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ocsz3-00B9Pe-Go; Mon, 26 Sep 2022 20:37:37 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ocsz1-007wcb-2J; Mon, 26 Sep 2022 20:37:35 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno Subject: [PATCH v2 13/13] arm64: dts: rockchip: Add IR receiver node to ODROID-M1 Date: Mon, 26 Sep 2022 20:37:27 +0200 Message-Id: <20220926183727.1893566-14-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926183727.1893566-1-aurelien@aurel32.net> References: <20220926183727.1893566-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the infrared receiver and its associated pinctrl entry. Note that there is an external pullup to VCC3V3_SYS. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-odroid-m1.dts index a9092c663a6e..1f3d66e2c659 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -49,6 +49,13 @@ hdmi_con_in: endpoint { }; }; =20 + ir-receiver { + compatible =3D "gpio-ir-receiver"; + gpios =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_receiver_pin>; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -505,6 +512,11 @@ &pcie3x2 { }; =20 &pinctrl { + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; leds { led_power_pin: led-power-pin { rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; --=20 2.35.1