From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62392C07E9D for ; Mon, 26 Sep 2022 14:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235256AbiIZOzJ (ORCPT ); Mon, 26 Sep 2022 10:55:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235173AbiIZOy3 (ORCPT ); Mon, 26 Sep 2022 10:54:29 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7690193799 for ; Mon, 26 Sep 2022 06:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664198493; x=1695734493; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sCEnmrg9GWDdV+abb6W1IKSbIi92j5+nKGixxLBe/4o=; b=aVrbTHsg6pVXcS0dsAhjvspOFQc2SDKpuuDnpnFx0hM11EhNtqymHNLJ AlPjtNyyKzttlzMYBfmFSuRG0pvKxYEY/NbwSCNkJZyr24XcZad7zWIPL Bhgid9pk/Xaaf0CP1Ug4XnuKJkAj6j+3v4uCvjLhXul+nhKvjGQrrgAQj n02e3ZiKwP0RTPTwg4bM/lY3ou5tINuNSAmaU92XSqRmPi2Kq2x7IeMuq wrvYOsmB5kPB9PAPAXN8OzmidTTjc16N3dboLbJp4gbIsdVlth1aZAkXm 3lmbKFmhnf7JEWfcLPB84fNYwW1BywDyVmomaIfQmZSL9J7AdfaSTlg5k A==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750284" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750284" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525649" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525649" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:31 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] iommu/vt-d: Remove unnecessary SVA data accesses in page fault path Date: Mon, 26 Sep 2022 21:15:24 +0800 Message-Id: <20220926131529.4045281-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The existing I/O page fault handling code accesses the per-PASID SVA data structures. This is unnecessary and makes the fault handling code only suitable for SVA scenarios. This removes the SVA data accesses from the I/O page fault reporting and responding code, so that the fault handling code could be generic. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220914011821.400986-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/iommu.h | 2 +- drivers/iommu/intel/svm.c | 60 +++++-------------------------------- 2 files changed, 8 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 74b0e19e23ee..b5fb7706e97c 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -586,6 +586,7 @@ struct intel_iommu { #ifdef CONFIG_INTEL_IOMMU_SVM struct page_req_dsc *prq; unsigned char prq_name[16]; /* Name for PRQ interrupt */ + unsigned long prq_seq_number; struct completion prq_complete; struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASI= Ds */ #endif @@ -761,7 +762,6 @@ struct intel_svm_dev { struct device *dev; struct intel_iommu *iommu; struct iommu_sva sva; - unsigned long prq_seq_number; u32 pasid; int users; u16 did; diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 8bcfb93dda56..d1cab931dcb0 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -48,23 +48,6 @@ static void *pasid_private_find(ioasid_t pasid) return xa_load(&pasid_private_array, pasid); } =20 -static struct intel_svm_dev * -svm_lookup_device_by_sid(struct intel_svm *svm, u16 sid) -{ - struct intel_svm_dev *sdev =3D NULL, *t; - - rcu_read_lock(); - list_for_each_entry_rcu(t, &svm->devs, list) { - if (t->sid =3D=3D sid) { - sdev =3D t; - break; - } - } - rcu_read_unlock(); - - return sdev; -} - static struct intel_svm_dev * svm_lookup_device_by_dev(struct intel_svm *svm, struct device *dev) { @@ -706,11 +689,10 @@ static void handle_bad_prq_event(struct intel_iommu *= iommu, =20 static irqreturn_t prq_event_thread(int irq, void *d) { - struct intel_svm_dev *sdev =3D NULL; struct intel_iommu *iommu =3D d; - struct intel_svm *svm =3D NULL; struct page_req_dsc *req; int head, tail, handled; + struct pci_dev *pdev; u64 address; =20 /* @@ -730,8 +712,6 @@ static irqreturn_t prq_event_thread(int irq, void *d) pr_err("IOMMU: %s: Page request without PASID\n", iommu->name); bad_req: - svm =3D NULL; - sdev =3D NULL; handle_bad_prq_event(iommu, req, QI_RESP_INVALID); goto prq_advance; } @@ -758,34 +738,19 @@ static irqreturn_t prq_event_thread(int irq, void *d) if (unlikely(req->lpig && !req->rd_req && !req->wr_req)) goto prq_advance; =20 - if (!svm || svm->pasid !=3D req->pasid) { - /* - * It can't go away, because the driver is not permitted - * to unbind the mm while any page faults are outstanding. - */ - svm =3D pasid_private_find(req->pasid); - if (IS_ERR_OR_NULL(svm) || (svm->flags & SVM_FLAG_SUPERVISOR_MODE)) - goto bad_req; - } - - if (!sdev || sdev->sid !=3D req->rid) { - sdev =3D svm_lookup_device_by_sid(svm, req->rid); - if (!sdev) - goto bad_req; - } - - sdev->prq_seq_number++; - + pdev =3D pci_get_domain_bus_and_slot(iommu->segment, + PCI_BUS_NUM(req->rid), + req->rid & 0xff); /* * If prq is to be handled outside iommu driver via receiver of * the fault notifiers, we skip the page response here. */ - if (intel_svm_prq_report(iommu, sdev->dev, req)) + if (!pdev || intel_svm_prq_report(iommu, &pdev->dev, req)) handle_bad_prq_event(iommu, req, QI_RESP_INVALID); =20 - trace_prq_report(iommu, sdev->dev, req->qw_0, req->qw_1, + trace_prq_report(iommu, &pdev->dev, req->qw_0, req->qw_1, req->priv_data[0], req->priv_data[1], - sdev->prq_seq_number); + iommu->prq_seq_number++); prq_advance: head =3D (head + sizeof(*req)) & PRQ_RING_MASK; } @@ -881,8 +846,6 @@ int intel_svm_page_response(struct device *dev, struct iommu_page_response *msg) { struct iommu_fault_page_request *prm; - struct intel_svm_dev *sdev =3D NULL; - struct intel_svm *svm =3D NULL; struct intel_iommu *iommu; bool private_present; bool pasid_present; @@ -901,8 +864,6 @@ int intel_svm_page_response(struct device *dev, if (!msg || !evt) return -EINVAL; =20 - mutex_lock(&pasid_mutex); - prm =3D &evt->fault.prm; sid =3D PCI_DEVID(bus, devfn); pasid_present =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; @@ -919,12 +880,6 @@ int intel_svm_page_response(struct device *dev, goto out; } =20 - ret =3D pasid_to_svm_sdev(dev, prm->pasid, &svm, &sdev); - if (ret || !sdev) { - ret =3D -ENODEV; - goto out; - } - /* * Per VT-d spec. v3.0 ch7.7, system software must respond * with page group response if private data is present (PDP) @@ -954,6 +909,5 @@ int intel_svm_page_response(struct device *dev, qi_submit_sync(iommu, &desc, 1, 0); } out: - mutex_unlock(&pasid_mutex); return ret; } --=20 2.34.1 From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A9A7C32771 for ; Mon, 26 Sep 2022 14:55:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235293AbiIZOzN (ORCPT ); Mon, 26 Sep 2022 10:55:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235190AbiIZOyb (ORCPT ); Mon, 26 Sep 2022 10:54:31 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6670B93784 for ; Mon, 26 Sep 2022 06:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664198495; x=1695734495; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sdksnCzyeOLKr/bm2XXYYY4lKlJEMlbXE8c0TLgwxP4=; b=gC1gF+WDhCjQTJn4GS1sHvKgXv66W7iGb5Bat8NO6pETlDm47QKkpF8+ fm3r84Pel1RtUH4r5Upqij8EpmYEGmMeskdcP2FOBZ9x97r7mkjjdx5z9 /5jZnjEE9NPTP6l66oi4BtXLRB7d/r4S7USvYakAEYxKEfBxfAs6BhidH NLRsvBUytUqsW2B7QglhIsfRANH862fuRzDyrjG94UQkPHQVUcXgX1cfo fvqtANB4SyXKvBI/fEv5oCqXZKhtIbPapXZ8g6f5LwJbupmG6ydI141SI Ej6UlSvu1KSGTs+7UNfqTgO7Hlg4q6prw4T1CDp+5Z9F0PdZxBJfUJnp8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750290" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750290" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525654" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525654" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:32 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] iommu/vt-d: Decouple PASID & PRI enabling from SVA Date: Mon, 26 Sep 2022 21:15:25 +0800 Message-Id: <20220926131529.4045281-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously the PCI PASID and PRI capabilities are enabled in the path of iommu device probe only if INTEL_IOMMU_SVM is configured and the device supports ATS. As we've already decoupled the I/O page fault handler from SVA, we could also decouple PASID and PRI enabling from it to make room for growth of new features like kernel DMA with PASID, SIOV and nested translation. At the same time, the iommu_enable_dev_iotlb() helper is also called in iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) path. It's unnecessary and duplicate. This cleanups this helper to make the code neat. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220915085814.2261409-1-baolu.lu@linux.int= el.com --- drivers/iommu/intel/iommu.h | 1 - drivers/iommu/intel/iommu.c | 78 ++++++++----------------------------- drivers/iommu/intel/Kconfig | 5 +-- 3 files changed, 18 insertions(+), 66 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index b5fb7706e97c..8f29a183467d 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -742,7 +742,6 @@ extern int dmar_ir_support(void); void *alloc_pgtable_page(int node); void free_pgtable_page(void *vaddr); void iommu_flush_write_buffer(struct intel_iommu *iommu); -int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev= ); struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn= ); =20 #ifdef CONFIG_INTEL_IOMMU_SVM diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 31bc50e538a3..af17177b6d76 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -199,6 +199,11 @@ static inline void context_set_domain_id(struct contex= t_entry *context, context->hi |=3D (value & ((1 << 16) - 1)) << 8; } =20 +static inline void context_set_pasid(struct context_entry *context) +{ + context->lo |=3D CONTEXT_PASIDE; +} + static inline int context_domain_id(struct context_entry *c) { return((c->hi >> 8) & 0xffff); @@ -1350,21 +1355,18 @@ static void __iommu_flush_iotlb(struct intel_iommu = *iommu, u16 did, } =20 static struct device_domain_info * -iommu_support_dev_iotlb(struct dmar_domain *domain, struct intel_iommu *io= mmu, - u8 bus, u8 devfn) +domain_lookup_dev_info(struct dmar_domain *domain, + struct intel_iommu *iommu, u8 bus, u8 devfn) { struct device_domain_info *info; unsigned long flags; =20 - if (!iommu->qi) - return NULL; - spin_lock_irqsave(&domain->lock, flags); list_for_each_entry(info, &domain->devices, link) { if (info->iommu =3D=3D iommu && info->bus =3D=3D bus && info->devfn =3D=3D devfn) { spin_unlock_irqrestore(&domain->lock, flags); - return info->ats_supported ? info : NULL; + return info; } } spin_unlock_irqrestore(&domain->lock, flags); @@ -1389,7 +1391,7 @@ static void domain_update_iotlb(struct dmar_domain *d= omain) spin_unlock_irqrestore(&domain->lock, flags); } =20 -static void iommu_enable_dev_iotlb(struct device_domain_info *info) +static void iommu_enable_pci_caps(struct device_domain_info *info) { struct pci_dev *pdev; =20 @@ -1412,7 +1414,6 @@ static void iommu_enable_dev_iotlb(struct device_doma= in_info *info) info->pfsid =3D pci_dev_id(pf_pdev); } =20 -#ifdef CONFIG_INTEL_IOMMU_SVM /* The PCIe spec, in its wisdom, declares that the behaviour of the device if you enable PASID support after ATS support is undefined. So always enable PASID support on devices which @@ -1425,7 +1426,7 @@ static void iommu_enable_dev_iotlb(struct device_doma= in_info *info) (info->pasid_enabled ? pci_prg_resp_pasid_required(pdev) : 1) && !pci_reset_pri(pdev) && !pci_enable_pri(pdev, PRQ_DEPTH)) info->pri_enabled =3D 1; -#endif + if (info->ats_supported && pci_ats_page_aligned(pdev) && !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) { info->ats_enabled =3D 1; @@ -1448,16 +1449,16 @@ static void iommu_disable_dev_iotlb(struct device_d= omain_info *info) info->ats_enabled =3D 0; domain_update_iotlb(info->domain); } -#ifdef CONFIG_INTEL_IOMMU_SVM + if (info->pri_enabled) { pci_disable_pri(pdev); info->pri_enabled =3D 0; } + if (info->pasid_enabled) { pci_disable_pasid(pdev); info->pasid_enabled =3D 0; } -#endif } =20 static void __iommu_flush_dev_iotlb(struct device_domain_info *info, @@ -1907,7 +1908,7 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, u8 bus, u8 devfn) { struct device_domain_info *info =3D - iommu_support_dev_iotlb(domain, iommu, bus, devfn); + domain_lookup_dev_info(domain, iommu, bus, devfn); u16 did =3D domain_id_iommu(domain, iommu); int translation =3D CONTEXT_TT_MULTI_LEVEL; struct context_entry *context; @@ -1980,6 +1981,8 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, context_set_sm_dte(context); if (info && info->pri_supported) context_set_sm_pre(context); + if (info && info->pasid_supported) + context_set_pasid(context); } else { struct dma_pte *pgd =3D domain->pgd; int agaw; @@ -2037,7 +2040,7 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, } else { iommu_flush_write_buffer(iommu); } - iommu_enable_dev_iotlb(info); + iommu_enable_pci_caps(info); =20 ret =3D 0; =20 @@ -4574,52 +4577,6 @@ static void intel_iommu_get_resv_regions(struct devi= ce *device, list_add_tail(®->list, head); } =20 -int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev) -{ - struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct context_entry *context; - struct dmar_domain *domain; - u64 ctx_lo; - int ret; - - domain =3D info->domain; - if (!domain) - return -EINVAL; - - spin_lock(&iommu->lock); - ret =3D -EINVAL; - if (!info->pasid_supported) - goto out; - - context =3D iommu_context_addr(iommu, info->bus, info->devfn, 0); - if (WARN_ON(!context)) - goto out; - - ctx_lo =3D context[0].lo; - - if (!(ctx_lo & CONTEXT_PASIDE)) { - ctx_lo |=3D CONTEXT_PASIDE; - context[0].lo =3D ctx_lo; - wmb(); - iommu->flush.flush_context(iommu, - domain_id_iommu(domain, iommu), - PCI_DEVID(info->bus, info->devfn), - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - } - - /* Enable PASID support in the device, if it wasn't already */ - if (!info->pasid_enabled) - iommu_enable_dev_iotlb(info); - - ret =3D 0; - - out: - spin_unlock(&iommu->lock); - - return ret; -} - static struct iommu_group *intel_iommu_device_group(struct device *dev) { if (dev_is_pci(dev)) @@ -4643,9 +4600,6 @@ static int intel_iommu_enable_sva(struct device *dev) if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE)) return -ENODEV; =20 - if (intel_iommu_enable_pasid(iommu, dev)) - return -ENODEV; - if (!info->pasid_enabled || !info->pri_enabled || !info->ats_enabled) return -EINVAL; =20 diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig index 39a06d245f12..cd0ec7ed48b6 100644 --- a/drivers/iommu/intel/Kconfig +++ b/drivers/iommu/intel/Kconfig @@ -21,6 +21,8 @@ config INTEL_IOMMU select IOASID select IOMMU_DMA select PCI_ATS + select PCI_PRI + select PCI_PASID help DMA remapping (DMAR) devices support enables independent address translations for Direct Memory Access (DMA) from devices. @@ -48,10 +50,7 @@ config INTEL_IOMMU_DEBUGFS config INTEL_IOMMU_SVM bool "Support for Shared Virtual Memory with Intel IOMMU" depends on X86_64 - select PCI_PASID - select PCI_PRI select MMU_NOTIFIER - select IOASID select IOMMU_SVA help Shared Virtual Memory (SVM) provides a facility for devices --=20 2.34.1 From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20567C6FA83 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750293" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750293" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525663" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525663" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:34 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] iommu/vt-d: Remove pasid_set_eafe() Date: Mon, 26 Sep 2022 21:15:26 +0800 Message-Id: <20220926131529.4045281-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It is not used anywhere in the tree. Remove it to avoid dead code. No functional change intended. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220915081645.1834555-1-baolu.lu@linux.int= el.com --- drivers/iommu/intel/pasid.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index c5e7e8b020a5..ccaf32949254 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -392,16 +392,6 @@ pasid_set_flpm(struct pasid_entry *pe, u64 value) pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); } =20 -/* - * Setup the Extended Access Flag Enable (EAFE) field (Bit 135) - * of a scalable mode PASID entry. - */ -static inline void -pasid_set_eafe(struct pasid_entry *pe) -{ - pasid_set_bits(&pe->val[2], 1 << 7, 1 << 7); -} - static void pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid) --=20 2.34.1 From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E89AC07E9D for ; Mon, 26 Sep 2022 14:55:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234224AbiIZOzS (ORCPT ); Mon, 26 Sep 2022 10:55:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235206AbiIZOyb (ORCPT ); Mon, 26 Sep 2022 10:54:31 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C4619321B for ; Mon, 26 Sep 2022 06:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664198497; x=1695734497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5LlA/u/VYUbmCHDKN9YVHV+hnazEB1G6k/0nGrQd6dQ=; b=Fhq0CgP7gnqGVYOXgYp91CemniI41srFw7japEZ3IpKHcR2MxxwAiVM/ 8V/RBvATnfN8prLdytcnXEK4kIKNk3GORNK86MDc+qIc8qejHXdajSrWz jWYxgpdRmVylQ2uCdKINDGOjM6SHe0sczWcyQHEoiYrGUf5engRNsSPie 28F1VI419pBE5CCaV8uWCXfLPAx5Oglf4HKQIU0o8P84kdcufZ43v+dfY DElIai9x0rjujDDLLTQRtTUJ4jX3lepnCZHkTv59q+EtaIpUvE6ZWj53w NMTDqVdKUD1RZ1G3+uEYapw79/ybstI9bbsrmLw22ZY/Nb9JJ4SLjjprn A==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750299" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750299" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525668" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525668" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:35 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support Date: Mon, 26 Sep 2022 21:15:27 +0800 Message-Id: <20220926131529.4045281-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yi Liu This renaming better describes it is for first level page table (a.k.a first stage page table since VT-d spec 3.4). Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220916071326.2223901-1-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 2 +- drivers/iommu/intel/cap_audit.c | 4 ++-- drivers/iommu/intel/iommu.c | 2 +- drivers/iommu/intel/pasid.c | 2 +- drivers/iommu/intel/svm.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 8f29a183467d..99cc75ecac63 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -146,7 +146,7 @@ /* * Decoding Capability Register */ -#define cap_5lp_support(c) (((c) >> 60) & 1) +#define cap_fl5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) #define cap_read_drain(c) (((c) >> 55) & 1) diff --git a/drivers/iommu/intel/cap_audit.c b/drivers/iommu/intel/cap_audi= t.c index 3ee68393122f..806986696841 100644 --- a/drivers/iommu/intel/cap_audit.c +++ b/drivers/iommu/intel/cap_audit.c @@ -37,7 +37,7 @@ static inline void check_dmar_capabilities(struct intel_i= ommu *a, MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK); MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK); =20 - CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK); + CHECK_FEATURE_MISMATCH(a, b, cap, fl5lp_support, CAP_FL5LP_MASK); CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK); CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK); CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK); @@ -84,7 +84,7 @@ static int cap_audit_hotplug(struct intel_iommu *iommu, e= num cap_audit_type type goto out; } =20 - CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK); + CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl5lp_support, CAP_FL5LP_MASK); CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK); CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK); CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index af17177b6d76..7410d6232cbb 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -404,7 +404,7 @@ static unsigned long __iommu_calculate_sagaw(struct int= el_iommu *iommu) { unsigned long fl_sagaw, sl_sagaw; =20 - fl_sagaw =3D BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0); + fl_sagaw =3D BIT(2) | (cap_fl5lp_support(iommu->cap) ? BIT(3) : 0); sl_sagaw =3D cap_sagaw(iommu->cap); =20 /* Second level only. */ diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index ccaf32949254..c30ddac40ee5 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -519,7 +519,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *i= ommu, } } =20 - if ((flags & PASID_FLAG_FL5LP) && !cap_5lp_support(iommu->cap)) { + if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) { pr_err("No 5-level paging support for first-level on %s\n", iommu->name); return -EINVAL; diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index d1cab931dcb0..7d08eb034f2d 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -164,7 +164,7 @@ void intel_svm_check(struct intel_iommu *iommu) } =20 if (cpu_feature_enabled(X86_FEATURE_LA57) && - !cap_5lp_support(iommu->cap)) { + !cap_fl5lp_support(iommu->cap)) { pr_err("%s SVM disabled, incompatible paging mode\n", iommu->name); return; --=20 2.34.1 From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A442EC32771 for ; Mon, 26 Sep 2022 14:55:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235425AbiIZOz3 (ORCPT ); Mon, 26 Sep 2022 10:55:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235222AbiIZOyb (ORCPT ); Mon, 26 Sep 2022 10:54:31 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0296692F6B for ; Mon, 26 Sep 2022 06:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664198497; x=1695734497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PnmH4tiC7HuVSl3cVloykZSS5RyOXcfcPLxPjpvq+kQ=; b=A3tOQeBjOeGLoiuSRLVMlamGyB4zdVsxuysajFepogFy3BugtclK6w2u 6y8cy60V8iOOzdGMTnSIgYvAcymMw27ucQfp87W9X+IJyQAyETa+b4mhT uX1dZjbUEndiJcNWC0HynrlE3AysNMHsG7uxbC8tdh2RYEUw1+NGI2DL+ q28wa5Kg2zjgIfICE/jhQVz+KQtAMwnlzTETe/ZOElWO73caKVaNRk1/5 13HoQxPSt3Nj/SXCcgCZWzV124JDkvZ3QjUPDHejQ33b+rO0UmkOQK/1t w6W3tWcl3Z/IhmpZ9b/cfDQEgt+F8cNHdyFrzkvkLhUzFZvLm8qDJDkyV g==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750312" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750312" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525678" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525678" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:36 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation Date: Mon, 26 Sep 2022 21:15:28 +0800 Message-Id: <20220926131529.4045281-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some VT-d hardware implementations invalidate all interrupt remapping hardware translation caches as part of SIRTP flow. The VT-d spec adds a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section 11.4.2 in VT-d spec) capability bit to indicate this. The spec also states in 11.4.4 that hardware also performs global invalidation on all interrupt remapping caches as part of Interrupt Remapping Disable operation if ESIRTPS capability bit is set. This checks the ESIRTPS capability bit and skip software global cache invalidation if it's set. Signed-off-by: Jacob Pan Signed-off-by: Lu Baolu Reviewed-by: Jerry Snitselaar Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220921065741.3572495-1-baolu.lu@linux.int= el.com --- drivers/iommu/intel/iommu.h | 1 + drivers/iommu/intel/irq_remapping.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 99cc75ecac63..bddf6c69587d 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -146,6 +146,7 @@ /* * Decoding Capability Register */ +#define cap_esirtps(c) (((c) >> 62) & 1) #define cap_fl5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 2e9683e970f8..5962bb5027d0 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -494,7 +494,8 @@ static void iommu_set_irq_remapping(struct intel_iommu = *iommu, int mode) * Global invalidation of interrupt entry cache to make sure the * hardware uses the new irq remapping table. */ - qi_global_iec(iommu); + if (!cap_esirtps(iommu->cap)) + qi_global_iec(iommu); } =20 static void iommu_enable_irq_remapping(struct intel_iommu *iommu) @@ -680,7 +681,8 @@ static void iommu_disable_irq_remapping(struct intel_io= mmu *iommu) * global invalidation of interrupt entry cache before disabling * interrupt-remapping. */ - qi_global_iec(iommu); + if (!cap_esirtps(iommu->cap)) + qi_global_iec(iommu); =20 raw_spin_lock_irqsave(&iommu->register_lock, flags); =20 --=20 2.34.1 From nobody Fri Dec 19 20:14:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF732C07E9D for ; Mon, 26 Sep 2022 14:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235420AbiIZOzW (ORCPT ); Mon, 26 Sep 2022 10:55:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235229AbiIZOyb (ORCPT ); Mon, 26 Sep 2022 10:54:31 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE4E974BB7 for ; Mon, 26 Sep 2022 06:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664198498; x=1695734498; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xLujIRTj17nrnMKvg1CiEngbHNEpsa7tZnJMoZQG/+Y=; b=MU/12+T5yuzsgh/DHLjtx1Q1Cyod2L6CA2oC5ynmuVT+RUtxHU/VbzVV ECQa3C/wg+ROcRUg82XcoVwTgVMaOAMRAxDZBHf+AXYryAWyxkYzKJMie qih5xHuz4BV3sWFmoY3NkeGrcfDO9dOVBqusjST9ceb9AnvtObrlRV7Pq NsRs4tWJkFlt8MuTXEQSXJq7jV7sqMeTGTWz/w+8GpZQGg68wAwiEXpky 0QWjAh0yxYqpP7TfuiJvb12H/TjhzBHLYIL2OzKLVzuWMvrpIPfiGo2ze jUEApjYes9ZZYoBjh8hz/lWsUcZSJ50gEk6ZEEW9FXZbMZkFpOaTwNvTj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="280750320" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="280750320" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 06:21:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="683525686" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="683525686" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2022 06:21:37 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] iommu/vt-d: Avoid unnecessary global DMA cache invalidation Date: Mon, 26 Sep 2022 21:15:29 +0800 Message-Id: <20220926131529.4045281-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926131529.4045281-1-baolu.lu@linux.intel.com> References: <20220926131529.4045281-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some VT-d hardware implementations invalidate all DMA remapping hardware translation caches as part of SRTP flow. The VT-d spec adds a ESRTPS (Enhanced Set Root Table Pointer Support, section 11.4.2 in VT-d spec) capability bit to indicate this. With this bit set, software has no need to issue the global invalidation request. Signed-off-by: Lu Baolu Reviewed-by: Jerry Snitselaar Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20220919062523.3438951-3-baolu.lu@linux.int= el.com --- drivers/iommu/intel/iommu.h | 1 + drivers/iommu/intel/iommu.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index bddf6c69587d..92023dff9513 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -146,6 +146,7 @@ /* * Decoding Capability Register */ +#define cap_esrtps(c) (((c) >> 63) & 1) #define cap_esirtps(c) (((c) >> 62) & 1) #define cap_fl5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 7410d6232cbb..2d142ee7bbfa 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1239,6 +1239,13 @@ static void iommu_set_root_entry(struct intel_iommu = *iommu) =20 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); =20 + /* + * Hardware invalidates all DMA remapping hardware translation + * caches as part of SRTP flow. + */ + if (cap_esrtps(iommu->cap)) + return; + iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); if (sm_supported(iommu)) qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0); --=20 2.34.1