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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:14 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 01/15] arm64: dts: qcom: sm8250: align TLMM pin configuration with DT schema Date: Sun, 25 Sep 2022 13:05:54 +0200 Message-Id: <20220925110608.145728-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Drop also unneeded split between mux and config. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 +- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 38 +- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 16 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 556 +++++++----------- 4 files changed, 239 insertions(+), 383 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts= /qcom/qrb5165-rb5.dts index bf8077a1cf9a..62aa32f460ad 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1210,33 +1210,33 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; =20 - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins =3D "gpio63"; function =3D "gpio"; bias-disable; }; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; bias-disable; drive-strength =3D <16>; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - data { + data-pins { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio77"; function =3D "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8250-mtp.dts index a102aa5efa32..9db6136321b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -799,31 +799,19 @@ wcd_tx: wcd9380-tx@0,3 { &tlmm { gpio-reserved-ranges =3D <28 4>, <40 4>; =20 - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins =3D "gpio32"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio32"; - drive-strength =3D <16>; - output-high; - }; - }; - - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins =3D "gpio32"; - function =3D "gpio"; - }; - - config { - pins =3D "gpio32"; - drive-strength =3D <16>; - bias-disable; - output-low; - }; + wcd938x_reset_default: wcd938x-reset-default-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <16>; + output-high; + }; + + wcd938x_reset_sleep: wcd938x-reset-sleep-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/ar= m64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 549e0a2aa9fe..72162852fae7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -582,34 +582,34 @@ &slpi { &tlmm { gpio-reserved-ranges =3D <40 4>, <52 4>; =20 - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <16>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc2_data"; drive-strength =3D <16>; bias-pull-up; }; }; =20 - mdm2ap_default: mdm2ap-default { + mdm2ap_default: mdm2ap-default-state { pins =3D "gpio1", "gpio3"; function =3D "gpio"; drive-strength =3D <8>; bias-disable; }; =20 - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins =3D "gpio39"; function =3D "gpio"; drive-strength =3D <2>; @@ -617,14 +617,14 @@ ts_int_default: ts-int-default { input-enable; }; =20 - ap2mdm_default: ap2mdm-default { + ap2mdm_default: ap2mdm-default-state { pins =3D "gpio56", "gpio57"; function =3D "gpio"; drive-strength =3D <16>; bias-disable; }; =20 - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins =3D "gpio77"; function =3D "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index e0416d611b66..7eac3ba90c63 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3798,8 +3798,8 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 181>; wakeup-parent =3D <&pdc>; =20 - cci0_default: cci0-default { - cci0_i2c0_default: cci0-i2c0-default { + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { /* SDA, SCL */ pins =3D "gpio101", "gpio102"; function =3D "cci_i2c"; @@ -3808,7 +3808,7 @@ cci0_i2c0_default: cci0-i2c0-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci0_i2c1_default: cci0-i2c1-default { + cci0_i2c1_default: cci0-i2c1-default-pins { /* SDA, SCL */ pins =3D "gpio103", "gpio104"; function =3D "cci_i2c"; @@ -3818,8 +3818,8 @@ cci0_i2c1_default: cci0-i2c1-default { }; }; =20 - cci0_sleep: cci0-sleep { - cci0_i2c0_sleep: cci0-i2c0-sleep { + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { /* SDA, SCL */ pins =3D "gpio101", "gpio102"; function =3D "cci_i2c"; @@ -3828,7 +3828,7 @@ cci0_i2c0_sleep: cci0-i2c0-sleep { bias-pull-down; }; =20 - cci0_i2c1_sleep: cci0-i2c1-sleep { + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { /* SDA, SCL */ pins =3D "gpio103", "gpio104"; function =3D "cci_i2c"; @@ -3838,8 +3838,8 @@ cci0_i2c1_sleep: cci0-i2c1-sleep { }; }; =20 - cci1_default: cci1-default { - cci1_i2c0_default: cci1-i2c0-default { + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { /* SDA, SCL */ pins =3D "gpio105","gpio106"; function =3D "cci_i2c"; @@ -3848,7 +3848,7 @@ cci1_i2c0_default: cci1-i2c0-default { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci1_i2c1_default: cci1-i2c1-default { + cci1_i2c1_default: cci1-i2c1-default-pins { /* SDA, SCL */ pins =3D "gpio107","gpio108"; function =3D "cci_i2c"; @@ -3858,8 +3858,8 @@ cci1_i2c1_default: cci1-i2c1-default { }; }; =20 - cci1_sleep: cci1-sleep { - cci1_i2c0_sleep: cci1-i2c0-sleep { + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { /* SDA, SCL */ pins =3D "gpio105","gpio106"; function =3D "cci_i2c"; @@ -3868,7 +3868,7 @@ cci1_i2c0_sleep: cci1-i2c0-sleep { drive-strength =3D <2>; /* 2 mA */ }; =20 - cci1_i2c1_sleep: cci1-i2c1-sleep { + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { /* SDA, SCL */ pins =3D "gpio107","gpio108"; function =3D "cci_i2c"; @@ -3878,22 +3878,22 @@ cci1_i2c1_sleep: cci1-i2c1-sleep { }; }; =20 - pri_mi2s_active: pri-mi2s-active { - sclk { + pri_mi2s_active: pri-mi2s-active-state { + sclk-pins { pins =3D "gpio138"; function =3D "mi2s0_sck"; drive-strength =3D <8>; bias-disable; }; =20 - ws { + ws-pins { pins =3D "gpio141"; function =3D "mi2s0_ws"; drive-strength =3D <8>; output-high; }; =20 - data0 { + data0-pins { pins =3D "gpio139"; function =3D "mi2s0_data0"; drive-strength =3D <8>; @@ -3901,7 +3901,7 @@ data0 { output-high; }; =20 - data1 { + data1-pins { pins =3D "gpio140"; function =3D "mi2s0_data1"; drive-strength =3D <8>; @@ -3909,632 +3909,500 @@ data1 { }; }; =20 - qup_i2c0_default: qup-i2c0-default { - mux { - pins =3D "gpio28", "gpio29"; - function =3D "qup0"; - }; - - config { - pins =3D "gpio28", "gpio29"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins =3D "gpio28", "gpio29"; + function =3D "qup0"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins =3D "gpio4", "gpio5"; - function =3D "qup1"; - }; - - config { - pins =3D "gpio4", "gpio5"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "qup1"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c2_default: qup-i2c2-default { - mux { - pins =3D "gpio115", "gpio116"; - function =3D "qup2"; - }; - - config { - pins =3D "gpio115", "gpio116"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins =3D "gpio115", "gpio116"; + function =3D "qup2"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c3_default: qup-i2c3-default { - mux { - pins =3D "gpio119", "gpio120"; - function =3D "qup3"; - }; - - config { - pins =3D "gpio119", "gpio120"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins =3D "gpio119", "gpio120"; + function =3D "qup3"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c4_default: qup-i2c4-default { - mux { - pins =3D "gpio8", "gpio9"; - function =3D "qup4"; - }; - - config { - pins =3D "gpio8", "gpio9"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins =3D "gpio8", "gpio9"; + function =3D "qup4"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c5_default: qup-i2c5-default { - mux { - pins =3D "gpio12", "gpio13"; - function =3D "qup5"; - }; - - config { - pins =3D "gpio12", "gpio13"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "qup5"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c6_default: qup-i2c6-default { - mux { - pins =3D "gpio16", "gpio17"; - function =3D "qup6"; - }; - - config { - pins =3D "gpio16", "gpio17"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins =3D "gpio16", "gpio17"; + function =3D "qup6"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c7_default: qup-i2c7-default { - mux { - pins =3D "gpio20", "gpio21"; - function =3D "qup7"; - }; - - config { - pins =3D "gpio20", "gpio21"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins =3D "gpio20", "gpio21"; + function =3D "qup7"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c8_default: qup-i2c8-default { - mux { - pins =3D "gpio24", "gpio25"; - function =3D "qup8"; - }; - - config { - pins =3D "gpio24", "gpio25"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins =3D "gpio24", "gpio25"; + function =3D "qup8"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c9_default: qup-i2c9-default { - mux { - pins =3D "gpio125", "gpio126"; - function =3D "qup9"; - }; - - config { - pins =3D "gpio125", "gpio126"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins =3D "gpio125", "gpio126"; + function =3D "qup9"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c10_default: qup-i2c10-default { - mux { - pins =3D "gpio129", "gpio130"; - function =3D "qup10"; - }; - - config { - pins =3D "gpio129", "gpio130"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins =3D "gpio129", "gpio130"; + function =3D "qup10"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c11_default: qup-i2c11-default { - mux { - pins =3D "gpio60", "gpio61"; - function =3D "qup11"; - }; - - config { - pins =3D "gpio60", "gpio61"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins =3D "gpio60", "gpio61"; + function =3D "qup11"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c12_default: qup-i2c12-default { - mux { - pins =3D "gpio32", "gpio33"; - function =3D "qup12"; - }; - - config { - pins =3D "gpio32", "gpio33"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins =3D "gpio32", "gpio33"; + function =3D "qup12"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c13_default: qup-i2c13-default { - mux { - pins =3D "gpio36", "gpio37"; - function =3D "qup13"; - }; - - config { - pins =3D "gpio36", "gpio37"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup13"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c14_default: qup-i2c14-default { - mux { - pins =3D "gpio40", "gpio41"; - function =3D "qup14"; - }; - - config { - pins =3D "gpio40", "gpio41"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins =3D "gpio40", "gpio41"; + function =3D "qup14"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c15_default: qup-i2c15-default { - mux { - pins =3D "gpio44", "gpio45"; - function =3D "qup15"; - }; - - config { - pins =3D "gpio44", "gpio45"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins =3D "gpio44", "gpio45"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c16_default: qup-i2c16-default { - mux { - pins =3D "gpio48", "gpio49"; - function =3D "qup16"; - }; - - config { - pins =3D "gpio48", "gpio49"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c16_default: qup-i2c16-default-state { + pins =3D "gpio48", "gpio49"; + function =3D "qup16"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c17_default: qup-i2c17-default { - mux { - pins =3D "gpio52", "gpio53"; - function =3D "qup17"; - }; - - config { - pins =3D "gpio52", "gpio53"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c17_default: qup-i2c17-default-state { + pins =3D "gpio52", "gpio53"; + function =3D "qup17"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c18_default: qup-i2c18-default { - mux { - pins =3D "gpio56", "gpio57"; - function =3D "qup18"; - }; - - config { - pins =3D "gpio56", "gpio57"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c18_default: qup-i2c18-default-state { + pins =3D "gpio56", "gpio57"; + function =3D "qup18"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_i2c19_default: qup-i2c19-default { - mux { - pins =3D "gpio0", "gpio1"; - function =3D "qup19"; - }; - - config { - pins =3D "gpio0", "gpio1"; - drive-strength =3D <2>; - bias-disable; - }; + qup_i2c19_default: qup-i2c19-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup19"; + drive-strength =3D <2>; + bias-disable; }; =20 - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-state { pins =3D "gpio31"; function =3D "qup0"; }; =20 - qup_spi0_cs_gpio: qup-spi0-cs-gpio { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins =3D "gpio31"; function =3D "gpio"; }; =20 - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins =3D "gpio28", "gpio29", "gpio30"; function =3D "qup0"; }; =20 - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-state { pins =3D "gpio7"; function =3D "qup1"; }; =20 - qup_spi1_cs_gpio: qup-spi1-cs-gpio { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins =3D "gpio7"; function =3D "gpio"; }; =20 - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins =3D "gpio4", "gpio5", "gpio6"; function =3D "qup1"; }; =20 - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-state { pins =3D "gpio118"; function =3D "qup2"; }; =20 - qup_spi2_cs_gpio: qup-spi2-cs-gpio { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins =3D "gpio118"; function =3D "gpio"; }; =20 - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins =3D "gpio115", "gpio116", "gpio117"; function =3D "qup2"; }; =20 - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-state { pins =3D "gpio122"; function =3D "qup3"; }; =20 - qup_spi3_cs_gpio: qup-spi3-cs-gpio { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins =3D "gpio122"; function =3D "gpio"; }; =20 - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins =3D "gpio119", "gpio120", "gpio121"; function =3D "qup3"; }; =20 - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-state { pins =3D "gpio11"; function =3D "qup4"; }; =20 - qup_spi4_cs_gpio: qup-spi4-cs-gpio { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins =3D "gpio11"; function =3D "gpio"; }; =20 - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins =3D "gpio8", "gpio9", "gpio10"; function =3D "qup4"; }; =20 - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-state { pins =3D "gpio15"; function =3D "qup5"; }; =20 - qup_spi5_cs_gpio: qup-spi5-cs-gpio { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins =3D "gpio15"; function =3D "gpio"; }; =20 - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins =3D "gpio12", "gpio13", "gpio14"; function =3D "qup5"; }; =20 - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-state { pins =3D "gpio19"; function =3D "qup6"; }; =20 - qup_spi6_cs_gpio: qup-spi6-cs-gpio { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins =3D "gpio19"; function =3D "gpio"; }; =20 - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins =3D "gpio16", "gpio17", "gpio18"; function =3D "qup6"; }; =20 - qup_spi7_cs: qup-spi7-cs { + qup_spi7_cs: qup-spi7-cs-state { pins =3D "gpio23"; function =3D "qup7"; }; =20 - qup_spi7_cs_gpio: qup-spi7-cs-gpio { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins =3D "gpio23"; function =3D "gpio"; }; =20 - qup_spi7_data_clk: qup-spi7-data-clk { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins =3D "gpio20", "gpio21", "gpio22"; function =3D "qup7"; }; =20 - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-state { pins =3D "gpio27"; function =3D "qup8"; }; =20 - qup_spi8_cs_gpio: qup-spi8-cs-gpio { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins =3D "gpio27"; function =3D "gpio"; }; =20 - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins =3D "gpio24", "gpio25", "gpio26"; function =3D "qup8"; }; =20 - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-state { pins =3D "gpio128"; function =3D "qup9"; }; =20 - qup_spi9_cs_gpio: qup-spi9-cs-gpio { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins =3D "gpio128"; function =3D "gpio"; }; =20 - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins =3D "gpio125", "gpio126", "gpio127"; function =3D "qup9"; }; =20 - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-state { pins =3D "gpio132"; function =3D "qup10"; }; =20 - qup_spi10_cs_gpio: qup-spi10-cs-gpio { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins =3D "gpio132"; function =3D "gpio"; }; =20 - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins =3D "gpio129", "gpio130", "gpio131"; function =3D "qup10"; }; =20 - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-state { pins =3D "gpio63"; function =3D "qup11"; }; =20 - qup_spi11_cs_gpio: qup-spi11-cs-gpio { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins =3D "gpio63"; function =3D "gpio"; }; =20 - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins =3D "gpio60", "gpio61", "gpio62"; function =3D "qup11"; }; =20 - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-state { pins =3D "gpio35"; function =3D "qup12"; }; =20 - qup_spi12_cs_gpio: qup-spi12-cs-gpio { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins =3D "gpio35"; function =3D "gpio"; }; =20 - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins =3D "gpio32", "gpio33", "gpio34"; function =3D "qup12"; }; =20 - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-state { pins =3D "gpio39"; function =3D "qup13"; }; =20 - qup_spi13_cs_gpio: qup-spi13-cs-gpio { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins =3D "gpio39"; function =3D "gpio"; }; =20 - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins =3D "gpio36", "gpio37", "gpio38"; function =3D "qup13"; }; =20 - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-state { pins =3D "gpio43"; function =3D "qup14"; }; =20 - qup_spi14_cs_gpio: qup-spi14-cs-gpio { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins =3D "gpio43"; function =3D "gpio"; }; =20 - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins =3D "gpio40", "gpio41", "gpio42"; function =3D "qup14"; }; =20 - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-state { pins =3D "gpio47"; function =3D "qup15"; }; =20 - qup_spi15_cs_gpio: qup-spi15-cs-gpio { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins =3D "gpio47"; function =3D "gpio"; }; =20 - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins =3D "gpio44", "gpio45", "gpio46"; function =3D "qup15"; }; =20 - qup_spi16_cs: qup-spi16-cs { + qup_spi16_cs: qup-spi16-cs-state { pins =3D "gpio51"; function =3D "qup16"; }; =20 - qup_spi16_cs_gpio: qup-spi16-cs-gpio { + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { pins =3D "gpio51"; function =3D "gpio"; }; =20 - qup_spi16_data_clk: qup-spi16-data-clk { + qup_spi16_data_clk: qup-spi16-data-clk-state { pins =3D "gpio48", "gpio49", "gpio50"; function =3D "qup16"; }; =20 - qup_spi17_cs: qup-spi17-cs { + qup_spi17_cs: qup-spi17-cs-state { pins =3D "gpio55"; function =3D "qup17"; }; =20 - qup_spi17_cs_gpio: qup-spi17-cs-gpio { + qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { pins =3D "gpio55"; function =3D "gpio"; }; =20 - qup_spi17_data_clk: qup-spi17-data-clk { + qup_spi17_data_clk: qup-spi17-data-clk-state { pins =3D "gpio52", "gpio53", "gpio54"; function =3D "qup17"; }; =20 - qup_spi18_cs: qup-spi18-cs { + qup_spi18_cs: qup-spi18-cs-state { pins =3D "gpio59"; function =3D "qup18"; }; =20 - qup_spi18_cs_gpio: qup-spi18-cs-gpio { + qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { pins =3D "gpio59"; function =3D "gpio"; }; =20 - qup_spi18_data_clk: qup-spi18-data-clk { + qup_spi18_data_clk: qup-spi18-data-clk-state { pins =3D "gpio56", "gpio57", "gpio58"; function =3D "qup18"; }; =20 - qup_spi19_cs: qup-spi19-cs { + qup_spi19_cs: qup-spi19-cs-state { pins =3D "gpio3"; function =3D "qup19"; }; =20 - qup_spi19_cs_gpio: qup-spi19-cs-gpio { + qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { pins =3D "gpio3"; function =3D "gpio"; }; =20 - qup_spi19_data_clk: qup-spi19-data-clk { + qup_spi19_data_clk: qup-spi19-data-clk-state { pins =3D "gpio0", "gpio1", "gpio2"; function =3D "qup19"; }; =20 - qup_uart2_default: qup-uart2-default { - mux { - pins =3D "gpio117", "gpio118"; - function =3D "qup2"; - }; + qup_uart2_default: qup-uart2-default-state { + pins =3D "gpio117", "gpio118"; + function =3D "qup2"; }; =20 - qup_uart6_default: qup-uart6-default { - mux { - pins =3D "gpio16", "gpio17", - "gpio18", "gpio19"; - function =3D "qup6"; - }; + qup_uart6_default: qup-uart6-default-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "qup6"; }; =20 - qup_uart12_default: qup-uart12-default { - mux { - pins =3D "gpio34", "gpio35"; - function =3D "qup12"; - }; + qup_uart12_default: qup-uart12-default-state { + pins =3D "gpio34", "gpio35"; + function =3D "qup12"; }; =20 - qup_uart17_default: qup-uart17-default { - mux { - pins =3D "gpio52", "gpio53", - "gpio54", "gpio55"; - function =3D "qup17"; - }; + qup_uart17_default: qup-uart17-default-state { + pins =3D "gpio52", "gpio53", "gpio54", "gpio55"; + function =3D "qup17"; }; =20 - qup_uart18_default: qup-uart18-default { - mux { - pins =3D "gpio58", "gpio59"; - function =3D "qup18"; - }; + qup_uart18_default: qup-uart18-default-state { + pins =3D "gpio58", "gpio59"; + function =3D "qup18"; }; =20 - tert_mi2s_active: tert-mi2s-active { - sck { + tert_mi2s_active: tert-mi2s-active-state { + sck-pins { pins =3D "gpio133"; function =3D "mi2s2_sck"; drive-strength =3D <8>; bias-disable; }; =20 - data0 { + data0-pins { pins =3D "gpio134"; function =3D "mi2s2_data0"; drive-strength =3D <8>; @@ -4542,7 +4410,7 @@ data0 { output-high; }; =20 - ws { + ws-pins { pins =3D "gpio135"; function =3D "mi2s2_ws"; drive-strength =3D <8>; @@ -4550,42 +4418,42 @@ ws { }; }; =20 - sdc2_sleep_state: sdc2-sleep { - clk { + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <2>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <2>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc2_data"; drive-strength =3D <2>; bias-pull-up; }; }; =20 - pcie0_default_state: pcie0-default { - perst { + pcie0_default_state: pcie0-default-state { + perst-pins { pins =3D "gpio79"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio80"; function =3D "pci_e0"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio81"; function =3D "gpio"; drive-strength =3D <2>; @@ -4593,22 +4461,22 @@ wake { }; }; =20 - pcie1_default_state: pcie1-default { - perst { + pcie1_default_state: pcie1-default-state { + perst-pins { pins =3D "gpio82"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio83"; function =3D "pci_e1"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio84"; function =3D "gpio"; drive-strength =3D <2>; @@ -4616,22 +4484,22 @@ wake { }; }; =20 - pcie2_default_state: pcie2-default { - perst { + pcie2_default_state: pcie2-default-state { + perst-pins { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-down; }; =20 - clkreq { + clkreq-pins { pins =3D "gpio86"; function =3D "pci_e2"; drive-strength =3D <2>; bias-pull-up; }; =20 - wake { + wake-pins { pins =3D "gpio87"; function =3D "gpio"; drive-strength =3D <2>; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4AD8C04A95 for ; Sun, 25 Sep 2022 11:06:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231981AbiIYLG0 (ORCPT ); Sun, 25 Sep 2022 07:06:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231965AbiIYLGT (ORCPT ); Sun, 25 Sep 2022 07:06:19 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAC7F31ECC for ; Sun, 25 Sep 2022 04:06:17 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id b6so4576915ljr.10 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:15 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 02/15] arm64: dts: qcom: sm8250-sony-xperia-edo: fix touchscreen bias-disable Date: Sun, 25 Sep 2022 13:05:55 +0200 Message-Id: <20220925110608.145728-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The property to disable bias is "bias-disable". Fixes: e76c7e1f15fe ("arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen= ") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/ar= m64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 72162852fae7..601a21c381f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -613,7 +613,7 @@ ts_int_default: ts-int-default-state { pins =3D "gpio39"; function =3D "gpio"; drive-strength =3D <2>; - bias-disabled; + bias-disable; input-enable; }; =20 --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57507C6FA83 for ; Sun, 25 Sep 2022 11:06:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232683AbiIYLGh (ORCPT ); Sun, 25 Sep 2022 07:06:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232225AbiIYLGW (ORCPT ); Sun, 25 Sep 2022 07:06:22 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADE7E31ED9 for ; Sun, 25 Sep 2022 04:06:18 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id o2so6734431lfc.10 for ; Sun, 25 Sep 2022 04:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=c3vr9ZcVCz9cz4XS0JEceE2ICtAEiQioi8Jl3QwESv4=; b=jMdOMRCSdiINsgdxHOvy9wHBcF7bRjSjqJjTHA1FEq+LmhWXa54aYuTs3N7QSp8C+q /161jGZdpnmlk1alg9Z/Io/u/ByDy3FYP6UxCbVBcnJJVnwseYggOC2j5pGvIdu9yoEL 7Iwpy1ECYXUEdezqJgUWTk7ftYS5ZUS/e/rM0vUZtLK6TpAn/5X/tXw13IXxhHZwL4kH 3w6lkegER3vLyqVGu6M37s5BvLVMb26xLpo0RZrMY0HVn9MezZ4QMthShoXU8ThzXTOE 1cJwgrl3zvM9FZHqD2zrOlnPTRgubLyQVxrQjSYS0bbzHaBiO2B9rtkQNaB/MuSd4r6k qZug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=c3vr9ZcVCz9cz4XS0JEceE2ICtAEiQioi8Jl3QwESv4=; b=S8OVBat8fHqZ7WVFewDFoXc+g9djJMeeyxZF8A77GAp1+kRnnNZkoZ2O2DVnVGbEtB oXrMtNuJmS/QidoS5sakH3Hm+58y70Laip76XstRAspzzAT2LDDk072aPR6JxspB5vB3 esJV/X9g7Hci2fSYdoxJTg7AQ2yHx7GJF5SVM7lBm5zItUxkJhkNtgcB34lQ69eLOace JqZZ+OLRLU7AjLWgrHOh0H9lMY6Thth/00xo5sHNZ/1AGnV1dQyTdXHLBhHBkT9nKdCD UDGT2Smig/hVXlkJKD49iqtgy+jps97m6UM4Bzw6w6ptoGnvXD/5WfE+IfC4mumxwRFz o4/A== X-Gm-Message-State: ACrzQf3ODzK36qtgRIeID+wBOA3HsVeIoWh5XJi1EiXhAxUU3Od88o9o 0X0QJ/HxKuioGhr0DOGQBRBCvQ== X-Google-Smtp-Source: AMsMyM4JC1lcNK87LMmGzqJjfEddk8jD/YrDbuIGylz78nIuBbuzfAIBJ5M9k/y3RUqvYddCxvXufg== X-Received: by 2002:a19:5505:0:b0:497:ad71:39f4 with SMTP id n5-20020a195505000000b00497ad7139f4mr6660486lfe.226.1664103976886; Sun, 25 Sep 2022 04:06:16 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:16 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 03/15] arm64: dts: qcom: sc8280xp: align TLMM pin configuration with DT schema Date: Sun, 25 Sep 2022 13:05:56 +0200 Message-Id: <20220925110608.145728-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sc8280xp-crd.dtb: pinctrl@f100000: kybd-default-state: 'oneOf' condi= tional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'disable', 'int-n', 'reset' do not match any of the regexes: 'pinctrl-[= 0-9]+' 'disable', 'int-n', 'reset' do not match any of the regexes: '-pins$', = 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 12 ++++++------ .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index fea7d8273ccd..a2027f1d1d04 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -374,19 +374,19 @@ &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 kybd_default: kybd-default-state { - disable { + disable-pins { pins =3D "gpio102"; function =3D "gpio"; output-low; }; =20 - int-n { + int-n-pins { pins =3D "gpio104"; function =3D "gpio"; bias-disable; }; =20 - reset { + reset-pins { pins =3D "gpio105"; function =3D "gpio"; bias-disable; @@ -410,7 +410,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; =20 tpad_default: tpad-default-state { - int-n { + int-n-pins { pins =3D "gpio182"; function =3D "gpio"; bias-disable; @@ -418,13 +418,13 @@ int-n { }; =20 ts0_default: ts0-default-state { - int-n { + int-n-pins { pins =3D "gpio175"; function =3D "gpio"; bias-disable; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio99"; function =3D "gpio"; output-high; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index b2b744bb8a53..68b61e8d03c0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -350,19 +350,19 @@ &tlmm { gpio-reserved-ranges =3D <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7= >; =20 kybd_default: kybd-default-state { - disable { + disable-pins { pins =3D "gpio102"; function =3D "gpio"; output-low; }; =20 - int-n { + int-n-pins { pins =3D "gpio104"; function =3D "gpio"; bias-disable; }; =20 - reset { + reset-pins { pins =3D "gpio105"; function =3D "gpio"; bias-disable; @@ -384,7 +384,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; =20 tpad_default: tpad-default-state { - int-n { + int-n-pins { pins =3D "gpio182"; function =3D "gpio"; bias-disable; @@ -392,13 +392,13 @@ int-n { }; =20 ts0_default: ts0-default-state { - int-n { + int-n-pins { pins =3D "gpio175"; function =3D "gpio"; bias-disable; }; =20 - reset-n { + reset-n-pins { pins =3D "gpio99"; function =3D "gpio"; output-high; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36F80C04A95 for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:17 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 04/15] arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema (really) Date: Sun, 25 Sep 2022 13:05:57 +0200 Message-Id: <20220925110608.145728-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. I already tried to do this in commit d801357a0573 ("arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema") and I missed the fact that these nodes were not part of "state" node. Bindings did not catch these errors due to its own issues. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 8 +- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 44 +-- .../arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 8 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 26 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 20 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 316 +++++++++--------- 6 files changed, 211 insertions(+), 211 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/d= ts/qcom/sc7280-crd-r3.dts index dddb505e220b..1185141f348e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -118,25 +118,25 @@ &wcd9385 { }; =20 &tlmm { - tp_int_odl: tp-int-odl { + tp_int_odl: tp-int-odl-state { pins =3D "gpio7"; function =3D "gpio"; bias-disable; }; =20 - ts_int_l: ts-int-l { + ts_int_l: ts-int-l-state { pins =3D "gpio55"; function =3D "gpio"; bias-pull-up; }; =20 - ts_reset_l: ts-reset-l { + ts_reset_l: ts-reset-l-state { pins =3D "gpio54"; function =3D "gpio"; bias-disable; }; =20 - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins =3D "gpio81"; function =3D "gpio"; bias-pull-down; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index c11e37160f34..6a9389c40159 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -744,27 +744,27 @@ &tlmm { pinctrl-names =3D "default"; pinctrl-0 =3D <&bios_flash_wp_od>; =20 - amp_en: amp-en-pins { + amp_en: amp-en-state { pins =3D "gpio63"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins =3D "gpio18"; function =3D "gpio"; bias-pull-up; }; =20 - bios_flash_wp_od: bios-flash-wp-od-pins { + bios_flash_wp_od: bios-flash-wp-od-state { pins =3D "gpio16"; function =3D "gpio"; /* Has external pull */ bias-disable; }; =20 - en_fp_rails: en-fp-rails-pins { + en_fp_rails: en-fp-rails-state { pins =3D "gpio77"; function =3D "gpio"; bias-disable; @@ -772,60 +772,60 @@ en_fp_rails: en-fp-rails-pins { output-high; }; =20 - en_pp3300_codec: en-pp3300-codec-pins { + en_pp3300_codec: en-pp3300-codec-state { pins =3D "gpio105"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - en_pp3300_dx_edp: en-pp3300-dx-edp-pins { + en_pp3300_dx_edp: en-pp3300-dx-edp-state { pins =3D "gpio80"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - fp_rst_l: fp-rst-l-pins { + fp_rst_l: fp-rst-l-state { pins =3D "gpio78"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - fp_to_ap_irq_l: fp-to-ap-irq-l-pins { + fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins =3D "gpio61"; function =3D "gpio"; /* Has external pullup */ bias-disable; }; =20 - fpmcu_boot0: fpmcu-boot0-pins { + fpmcu_boot0: fpmcu-boot0-state { pins =3D "gpio68"; function =3D "gpio"; bias-disable; }; =20 - gsc_ap_int_odl: gsc-ap-int-odl-pins { + gsc_ap_int_odl: gsc-ap-int-odl-state { pins =3D "gpio104"; function =3D "gpio"; bias-pull-up; }; =20 - hp_irq: hp-irq-pins { + hp_irq: hp-irq-state { pins =3D "gpio101"; function =3D "gpio"; bias-pull-up; }; =20 - hub_en: hub-en-pins { + hub_en: hub-en-state { pins =3D "gpio157"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - pe_wake_odl: pe-wake-odl-pins { + pe_wake_odl: pe-wake-odl-state { pins =3D "gpio3"; function =3D "gpio"; /* Has external pull */ @@ -834,45 +834,45 @@ pe_wake_odl: pe-wake-odl-pins { }; =20 /* For ap_spi_fp */ - qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins { + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-state { pins =3D "gpio39"; function =3D "gpio"; output-high; }; =20 /* For ap_ec_spi */ - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; function =3D "gpio"; output-high; }; =20 - sar0_irq_odl: sar0-irq-odl-pins { + sar0_irq_odl: sar0-irq-odl-state { pins =3D "gpio141"; function =3D "gpio"; bias-pull-up; }; =20 - sar1_irq_odl: sar1-irq-odl-pins { + sar1_irq_odl: sar1-irq-odl-state { pins =3D "gpio140"; function =3D "gpio"; bias-pull-up; }; =20 - sd_cd_odl: sd-cd-odl-pins { + sd_cd_odl: sd-cd-odl-state { pins =3D "gpio91"; function =3D "gpio"; bias-pull-up; }; =20 - ssd_en: ssd-en-pins { + ssd_en: ssd-en-state { pins =3D "gpio51"; function =3D "gpio"; bias-disable; drive-strength =3D <2>; }; =20 - ssd_rst_l: ssd-rst-l-pins { + ssd_rst_l: ssd-rst-l-state { pins =3D "gpio2"; function =3D "gpio"; bias-disable; @@ -880,14 +880,14 @@ ssd_rst_l: ssd-rst-l-pins { output-low; }; =20 - tp_int_odl: tp-int-odl-pins { + tp_int_odl: tp-int-odl-state { pins =3D "gpio7"; function =3D "gpio"; /* Has external pullup */ bias-disable; }; =20 - wf_cam_en: wf-cam-en-pins { + wf_cam_en: wf-cam-en-state { pins =3D "gpio119"; function =3D "gpio"; /* Has external pulldown */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index 7f5143e9bb80..b35f3738933c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -79,26 +79,26 @@ cr50: tpm@0 { }; =20 &tlmm { - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins =3D "gpio18"; function =3D "gpio"; input-enable; bias-pull-up; }; =20 - h1_ap_int_odl: h1-ap-int-odl-pins { + h1_ap_int_odl: h1-ap-int-odl-state { pins =3D "gpio104"; function =3D "gpio"; input-enable; bias-pull-up; }; =20 - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; output-high; }; =20 - qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins { + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins =3D "gpio59"; output-high; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index cd432a2856a7..11982c14b704 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -747,24 +747,24 @@ &sdc2_data { }; =20 &tlmm { - amp_en: amp-en { + amp_en: amp-en-state { pins =3D "gpio63"; bias-pull-down; drive-strength =3D <2>; }; =20 - bt_en: bt-en-pins { + bt_en: bt-en-state { pins =3D "gpio85"; function =3D "gpio"; output-low; bias-disable; }; =20 - nvme_pwren: nvme-pwren-pins { + nvme_pwren: nvme-pwren-state { function =3D "gpio"; }; =20 - pcie1_reset_n: pcie1-reset-n-pins { + pcie1_reset_n: pcie1-reset-n-state { pins =3D "gpio2"; function =3D "gpio"; =20 @@ -773,7 +773,7 @@ pcie1_reset_n: pcie1-reset-n-pins { bias-disable; }; =20 - pcie1_wake_n: pcie1-wake-n-pins { + pcie1_wake_n: pcie1-wake-n-state { pins =3D "gpio3"; function =3D "gpio"; =20 @@ -781,7 +781,7 @@ pcie1_wake_n: pcie1-wake-n-pins { bias-pull-up; }; =20 - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins =3D "gpio28"; function =3D "gpio"; /* @@ -794,7 +794,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { bias-bus-hold; }; =20 - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins =3D "gpio29"; function =3D "gpio"; /* @@ -806,7 +806,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { bias-pull-down; }; =20 - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins =3D "gpio30"; function =3D "gpio"; /* @@ -816,7 +816,7 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; =20 - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins =3D "gpio31"; function =3D "gpio"; /* @@ -827,25 +827,25 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { bias-pull-up; }; =20 - sd_cd: sd-cd-pins { + sd_cd: sd-cd-state { pins =3D "gpio91"; function =3D "gpio"; bias-pull-up; }; =20 - sw_ctrl: sw-ctrl-pins { + sw_ctrl: sw-ctrl-state { pins =3D "gpio86"; function =3D "gpio"; bias-pull-down; }; =20 - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; }; =20 - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/d= ts/qcom/sc7280-qcard.dtsi index 4b8c676b0bb1..a42b5878a75f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -595,7 +595,7 @@ pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { }; =20 &tlmm { - mos_bt_en: mos-bt-en-pins { + mos_bt_en: mos-bt-en-state { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; @@ -603,7 +603,7 @@ mos_bt_en: mos-bt-en-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins =3D "gpio28"; function =3D "gpio"; /* @@ -617,7 +617,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins =3D "gpio29"; function =3D "gpio"; /* @@ -630,7 +630,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins =3D "gpio31"; function =3D "gpio"; /* @@ -642,7 +642,7 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { }; =20 /* For mos_bt_uart */ - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins =3D "gpio30"; function =3D "gpio"; /* @@ -652,32 +652,32 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; =20 - ts_int_conn: ts-int-conn-pins { + ts_int_conn: ts-int-conn-state { pins =3D "gpio55"; function =3D "gpio"; bias-pull-up; }; =20 - ts_rst_conn: ts-rst-conn-pins { + ts_rst_conn: ts-rst-conn-state { pins =3D "gpio54"; function =3D "gpio"; drive-strength =3D <2>; }; =20 - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins =3D "gpio81"; function =3D "gpio"; bias-pull-down; drive-strength =3D <2>; }; =20 - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; }; =20 - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins =3D "gpio83"; function =3D "gpio"; drive-strength =3D <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 28e3fb9992d9..1a603cf61d8b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4253,791 +4253,791 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 175>; wakeup-parent =3D <&pdc>; =20 - dp_hot_plug_det: dp-hot-plug-det-pins { + dp_hot_plug_det: dp-hot-plug-det-state { pins =3D "gpio47"; function =3D "dp_hot"; }; =20 - edp_hot_plug_det: edp-hot-plug-det-pins { + edp_hot_plug_det: edp-hot-plug-det-state { pins =3D "gpio60"; function =3D "edp_hot"; }; =20 - mi2s0_data0: mi2s0-data0-pins { + mi2s0_data0: mi2s0-data0-state { pins =3D "gpio98"; function =3D "mi2s0_data0"; }; =20 - mi2s0_data1: mi2s0-data1-pins { + mi2s0_data1: mi2s0-data1-state { pins =3D "gpio99"; function =3D "mi2s0_data1"; }; =20 - mi2s0_mclk: mi2s0-mclk-pins { + mi2s0_mclk: mi2s0-mclk-state { pins =3D "gpio96"; function =3D "pri_mi2s"; }; =20 - mi2s0_sclk: mi2s0-sclk-pins { + mi2s0_sclk: mi2s0-sclk-state { pins =3D "gpio97"; function =3D "mi2s0_sck"; }; =20 - mi2s0_ws: mi2s0-ws-pins { + mi2s0_ws: mi2s0-ws-state { pins =3D "gpio100"; function =3D "mi2s0_ws"; }; =20 - mi2s1_data0: mi2s1-data0-pins { + mi2s1_data0: mi2s1-data0-state { pins =3D "gpio107"; function =3D "mi2s1_data0"; }; =20 - mi2s1_sclk: mi2s1-sclk-pins { + mi2s1_sclk: mi2s1-sclk-state { pins =3D "gpio106"; function =3D "mi2s1_sck"; }; =20 - mi2s1_ws: mi2s1-ws-pins { + mi2s1_ws: mi2s1-ws-state { pins =3D "gpio108"; function =3D "mi2s1_ws"; }; =20 - pcie1_clkreq_n: pcie1-clkreq-n-pins { + pcie1_clkreq_n: pcie1-clkreq-n-state { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; }; =20 - qspi_clk: qspi-clk-pins { + qspi_clk: qspi-clk-state { pins =3D "gpio14"; function =3D "qspi_clk"; }; =20 - qspi_cs0: qspi-cs0-pins { + qspi_cs0: qspi-cs0-state { pins =3D "gpio15"; function =3D "qspi_cs"; }; =20 - qspi_cs1: qspi-cs1-pins { + qspi_cs1: qspi-cs1-state { pins =3D "gpio19"; function =3D "qspi_cs"; }; =20 - qspi_data01: qspi-data01-pins { + qspi_data01: qspi-data01-state { pins =3D "gpio12", "gpio13"; function =3D "qspi_data"; }; =20 - qspi_data12: qspi-data12-pins { + qspi_data12: qspi-data12-state { pins =3D "gpio16", "gpio17"; function =3D "qspi_data"; }; =20 - qup_i2c0_data_clk: qup-i2c0-data-clk-pins { + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins =3D "gpio0", "gpio1"; function =3D "qup00"; }; =20 - qup_i2c1_data_clk: qup-i2c1-data-clk-pins { + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins =3D "gpio4", "gpio5"; function =3D "qup01"; }; =20 - qup_i2c2_data_clk: qup-i2c2-data-clk-pins { + qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins =3D "gpio8", "gpio9"; function =3D "qup02"; }; =20 - qup_i2c3_data_clk: qup-i2c3-data-clk-pins { + qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins =3D "gpio12", "gpio13"; function =3D "qup03"; }; =20 - qup_i2c4_data_clk: qup-i2c4-data-clk-pins { + qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins =3D "gpio16", "gpio17"; function =3D "qup04"; }; =20 - qup_i2c5_data_clk: qup-i2c5-data-clk-pins { + qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins =3D "gpio20", "gpio21"; function =3D "qup05"; }; =20 - qup_i2c6_data_clk: qup-i2c6-data-clk-pins { + qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins =3D "gpio24", "gpio25"; function =3D "qup06"; }; =20 - qup_i2c7_data_clk: qup-i2c7-data-clk-pins { + qup_i2c7_data_clk: qup-i2c7-data-clk-state { pins =3D "gpio28", "gpio29"; function =3D "qup07"; }; =20 - qup_i2c8_data_clk: qup-i2c8-data-clk-pins { + qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins =3D "gpio32", "gpio33"; function =3D "qup10"; }; =20 - qup_i2c9_data_clk: qup-i2c9-data-clk-pins { + qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins =3D "gpio36", "gpio37"; function =3D "qup11"; }; =20 - qup_i2c10_data_clk: qup-i2c10-data-clk-pins { + qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins =3D "gpio40", "gpio41"; function =3D "qup12"; }; =20 - qup_i2c11_data_clk: qup-i2c11-data-clk-pins { + qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins =3D "gpio44", "gpio45"; function =3D "qup13"; }; =20 - qup_i2c12_data_clk: qup-i2c12-data-clk-pins { + qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins =3D "gpio48", "gpio49"; function =3D "qup14"; }; =20 - qup_i2c13_data_clk: qup-i2c13-data-clk-pins { + qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins =3D "gpio52", "gpio53"; function =3D "qup15"; }; =20 - qup_i2c14_data_clk: qup-i2c14-data-clk-pins { + qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins =3D "gpio56", "gpio57"; function =3D "qup16"; }; =20 - qup_i2c15_data_clk: qup-i2c15-data-clk-pins { + qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins =3D "gpio60", "gpio61"; function =3D "qup17"; }; =20 - qup_spi0_data_clk: qup-spi0-data-clk-pins { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins =3D "gpio0", "gpio1", "gpio2"; function =3D "qup00"; }; =20 - qup_spi0_cs: qup-spi0-cs-pins { + qup_spi0_cs: qup-spi0-cs-state { pins =3D "gpio3"; function =3D "qup00"; }; =20 - qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins =3D "gpio3"; function =3D "gpio"; }; =20 - qup_spi1_data_clk: qup-spi1-data-clk-pins { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins =3D "gpio4", "gpio5", "gpio6"; function =3D "qup01"; }; =20 - qup_spi1_cs: qup-spi1-cs-pins { + qup_spi1_cs: qup-spi1-cs-state { pins =3D "gpio7"; function =3D "qup01"; }; =20 - qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins =3D "gpio7"; function =3D "gpio"; }; =20 - qup_spi2_data_clk: qup-spi2-data-clk-pins { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins =3D "gpio8", "gpio9", "gpio10"; function =3D "qup02"; }; =20 - qup_spi2_cs: qup-spi2-cs-pins { + qup_spi2_cs: qup-spi2-cs-state { pins =3D "gpio11"; function =3D "qup02"; }; =20 - qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins =3D "gpio11"; function =3D "gpio"; }; =20 - qup_spi3_data_clk: qup-spi3-data-clk-pins { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins =3D "gpio12", "gpio13", "gpio14"; function =3D "qup03"; }; =20 - qup_spi3_cs: qup-spi3-cs-pins { + qup_spi3_cs: qup-spi3-cs-state { pins =3D "gpio15"; function =3D "qup03"; }; =20 - qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins =3D "gpio15"; function =3D "gpio"; }; =20 - qup_spi4_data_clk: qup-spi4-data-clk-pins { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins =3D "gpio16", "gpio17", "gpio18"; function =3D "qup04"; }; =20 - qup_spi4_cs: qup-spi4-cs-pins { + qup_spi4_cs: qup-spi4-cs-state { pins =3D "gpio19"; function =3D "qup04"; }; =20 - qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins =3D "gpio19"; function =3D "gpio"; }; =20 - qup_spi5_data_clk: qup-spi5-data-clk-pins { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins =3D "gpio20", "gpio21", "gpio22"; function =3D "qup05"; }; =20 - qup_spi5_cs: qup-spi5-cs-pins { + qup_spi5_cs: qup-spi5-cs-state { pins =3D "gpio23"; function =3D "qup05"; }; =20 - qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins =3D "gpio23"; function =3D "gpio"; }; =20 - qup_spi6_data_clk: qup-spi6-data-clk-pins { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins =3D "gpio24", "gpio25", "gpio26"; function =3D "qup06"; }; =20 - qup_spi6_cs: qup-spi6-cs-pins { + qup_spi6_cs: qup-spi6-cs-state { pins =3D "gpio27"; function =3D "qup06"; }; =20 - qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins =3D "gpio27"; function =3D "gpio"; }; =20 - qup_spi7_data_clk: qup-spi7-data-clk-pins { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins =3D "gpio28", "gpio29", "gpio30"; function =3D "qup07"; }; =20 - qup_spi7_cs: qup-spi7-cs-pins { + qup_spi7_cs: qup-spi7-cs-state { pins =3D "gpio31"; function =3D "qup07"; }; =20 - qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins =3D "gpio31"; function =3D "gpio"; }; =20 - qup_spi8_data_clk: qup-spi8-data-clk-pins { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins =3D "gpio32", "gpio33", "gpio34"; function =3D "qup10"; }; =20 - qup_spi8_cs: qup-spi8-cs-pins { + qup_spi8_cs: qup-spi8-cs-state { pins =3D "gpio35"; function =3D "qup10"; }; =20 - qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins =3D "gpio35"; function =3D "gpio"; }; =20 - qup_spi9_data_clk: qup-spi9-data-clk-pins { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins =3D "gpio36", "gpio37", "gpio38"; function =3D "qup11"; }; =20 - qup_spi9_cs: qup-spi9-cs-pins { + qup_spi9_cs: qup-spi9-cs-state { pins =3D "gpio39"; function =3D "qup11"; }; =20 - qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins =3D "gpio39"; function =3D "gpio"; }; =20 - qup_spi10_data_clk: qup-spi10-data-clk-pins { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins =3D "gpio40", "gpio41", "gpio42"; function =3D "qup12"; }; =20 - qup_spi10_cs: qup-spi10-cs-pins { + qup_spi10_cs: qup-spi10-cs-state { pins =3D "gpio43"; function =3D "qup12"; }; =20 - qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins =3D "gpio43"; function =3D "gpio"; }; =20 - qup_spi11_data_clk: qup-spi11-data-clk-pins { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins =3D "gpio44", "gpio45", "gpio46"; function =3D "qup13"; }; =20 - qup_spi11_cs: qup-spi11-cs-pins { + qup_spi11_cs: qup-spi11-cs-state { pins =3D "gpio47"; function =3D "qup13"; }; =20 - qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins =3D "gpio47"; function =3D "gpio"; }; =20 - qup_spi12_data_clk: qup-spi12-data-clk-pins { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins =3D "gpio48", "gpio49", "gpio50"; function =3D "qup14"; }; =20 - qup_spi12_cs: qup-spi12-cs-pins { + qup_spi12_cs: qup-spi12-cs-state { pins =3D "gpio51"; function =3D "qup14"; }; =20 - qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins =3D "gpio51"; function =3D "gpio"; }; =20 - qup_spi13_data_clk: qup-spi13-data-clk-pins { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins =3D "gpio52", "gpio53", "gpio54"; function =3D "qup15"; }; =20 - qup_spi13_cs: qup-spi13-cs-pins { + qup_spi13_cs: qup-spi13-cs-state { pins =3D "gpio55"; function =3D "qup15"; }; =20 - qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins =3D "gpio55"; function =3D "gpio"; }; =20 - qup_spi14_data_clk: qup-spi14-data-clk-pins { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins =3D "gpio56", "gpio57", "gpio58"; function =3D "qup16"; }; =20 - qup_spi14_cs: qup-spi14-cs-pins { + qup_spi14_cs: qup-spi14-cs-state { pins =3D "gpio59"; function =3D "qup16"; }; =20 - qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins =3D "gpio59"; function =3D "gpio"; }; =20 - qup_spi15_data_clk: qup-spi15-data-clk-pins { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins =3D "gpio60", "gpio61", "gpio62"; function =3D "qup17"; }; =20 - qup_spi15_cs: qup-spi15-cs-pins { + qup_spi15_cs: qup-spi15-cs-state { pins =3D "gpio63"; function =3D "qup17"; }; =20 - qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins =3D "gpio63"; function =3D "gpio"; }; =20 - qup_uart0_cts: qup-uart0-cts-pins { + qup_uart0_cts: qup-uart0-cts-state { pins =3D "gpio0"; function =3D "qup00"; }; =20 - qup_uart0_rts: qup-uart0-rts-pins { + qup_uart0_rts: qup-uart0-rts-state { pins =3D "gpio1"; function =3D "qup00"; }; =20 - qup_uart0_tx: qup-uart0-tx-pins { + qup_uart0_tx: qup-uart0-tx-state { pins =3D "gpio2"; function =3D "qup00"; }; =20 - qup_uart0_rx: qup-uart0-rx-pins { + qup_uart0_rx: qup-uart0-rx-state { pins =3D "gpio3"; function =3D "qup00"; }; =20 - qup_uart1_cts: qup-uart1-cts-pins { + qup_uart1_cts: qup-uart1-cts-state { pins =3D "gpio4"; function =3D "qup01"; }; =20 - qup_uart1_rts: qup-uart1-rts-pins { + qup_uart1_rts: qup-uart1-rts-state { pins =3D "gpio5"; function =3D "qup01"; }; =20 - qup_uart1_tx: qup-uart1-tx-pins { + qup_uart1_tx: qup-uart1-tx-state { pins =3D "gpio6"; function =3D "qup01"; }; =20 - qup_uart1_rx: qup-uart1-rx-pins { + qup_uart1_rx: qup-uart1-rx-state { pins =3D "gpio7"; function =3D "qup01"; }; =20 - qup_uart2_cts: qup-uart2-cts-pins { + qup_uart2_cts: qup-uart2-cts-state { pins =3D "gpio8"; function =3D "qup02"; }; =20 - qup_uart2_rts: qup-uart2-rts-pins { + qup_uart2_rts: qup-uart2-rts-state { pins =3D "gpio9"; function =3D "qup02"; }; =20 - qup_uart2_tx: qup-uart2-tx-pins { + qup_uart2_tx: qup-uart2-tx-state { pins =3D "gpio10"; function =3D "qup02"; }; =20 - qup_uart2_rx: qup-uart2-rx-pins { + qup_uart2_rx: qup-uart2-rx-state { pins =3D "gpio11"; function =3D "qup02"; }; =20 - qup_uart3_cts: qup-uart3-cts-pins { + qup_uart3_cts: qup-uart3-cts-state { pins =3D "gpio12"; function =3D "qup03"; }; =20 - qup_uart3_rts: qup-uart3-rts-pins { + qup_uart3_rts: qup-uart3-rts-state { pins =3D "gpio13"; function =3D "qup03"; }; =20 - qup_uart3_tx: qup-uart3-tx-pins { + qup_uart3_tx: qup-uart3-tx-state { pins =3D "gpio14"; function =3D "qup03"; }; =20 - qup_uart3_rx: qup-uart3-rx-pins { + qup_uart3_rx: qup-uart3-rx-state { pins =3D "gpio15"; function =3D "qup03"; }; =20 - qup_uart4_cts: qup-uart4-cts-pins { + qup_uart4_cts: qup-uart4-cts-state { pins =3D "gpio16"; function =3D "qup04"; }; =20 - qup_uart4_rts: qup-uart4-rts-pins { + qup_uart4_rts: qup-uart4-rts-state { pins =3D "gpio17"; function =3D "qup04"; }; =20 - qup_uart4_tx: qup-uart4-tx-pins { + qup_uart4_tx: qup-uart4-tx-state { pins =3D "gpio18"; function =3D "qup04"; }; =20 - qup_uart4_rx: qup-uart4-rx-pins { + qup_uart4_rx: qup-uart4-rx-state { pins =3D "gpio19"; function =3D "qup04"; }; =20 - qup_uart5_cts: qup-uart5-cts-pins { + qup_uart5_cts: qup-uart5-cts-state { pins =3D "gpio20"; function =3D "qup05"; }; =20 - qup_uart5_rts: qup-uart5-rts-pins { + qup_uart5_rts: qup-uart5-rts-state { pins =3D "gpio21"; function =3D "qup05"; }; =20 - qup_uart5_tx: qup-uart5-tx-pins { + qup_uart5_tx: qup-uart5-tx-state { pins =3D "gpio22"; function =3D "qup05"; }; =20 - qup_uart5_rx: qup-uart5-rx-pins { + qup_uart5_rx: qup-uart5-rx-state { pins =3D "gpio23"; function =3D "qup05"; }; =20 - qup_uart6_cts: qup-uart6-cts-pins { + qup_uart6_cts: qup-uart6-cts-state { pins =3D "gpio24"; function =3D "qup06"; }; =20 - qup_uart6_rts: qup-uart6-rts-pins { + qup_uart6_rts: qup-uart6-rts-state { pins =3D "gpio25"; function =3D "qup06"; }; =20 - qup_uart6_tx: qup-uart6-tx-pins { + qup_uart6_tx: qup-uart6-tx-state { pins =3D "gpio26"; function =3D "qup06"; }; =20 - qup_uart6_rx: qup-uart6-rx-pins { + qup_uart6_rx: qup-uart6-rx-state { pins =3D "gpio27"; function =3D "qup06"; }; =20 - qup_uart7_cts: qup-uart7-cts-pins { + qup_uart7_cts: qup-uart7-cts-state { pins =3D "gpio28"; function =3D "qup07"; }; =20 - qup_uart7_rts: qup-uart7-rts-pins { + qup_uart7_rts: qup-uart7-rts-state { pins =3D "gpio29"; function =3D "qup07"; }; =20 - qup_uart7_tx: qup-uart7-tx-pins { + qup_uart7_tx: qup-uart7-tx-state { pins =3D "gpio30"; function =3D "qup07"; }; =20 - qup_uart7_rx: qup-uart7-rx-pins { + qup_uart7_rx: qup-uart7-rx-state { pins =3D "gpio31"; function =3D "qup07"; }; =20 - qup_uart8_cts: qup-uart8-cts-pins { + qup_uart8_cts: qup-uart8-cts-state { pins =3D "gpio32"; function =3D "qup10"; }; =20 - qup_uart8_rts: qup-uart8-rts-pins { + qup_uart8_rts: qup-uart8-rts-state { pins =3D "gpio33"; function =3D "qup10"; }; =20 - qup_uart8_tx: qup-uart8-tx-pins { + qup_uart8_tx: qup-uart8-tx-state { pins =3D "gpio34"; function =3D "qup10"; }; =20 - qup_uart8_rx: qup-uart8-rx-pins { + qup_uart8_rx: qup-uart8-rx-state { pins =3D "gpio35"; function =3D "qup10"; }; =20 - qup_uart9_cts: qup-uart9-cts-pins { + qup_uart9_cts: qup-uart9-cts-state { pins =3D "gpio36"; function =3D "qup11"; }; =20 - qup_uart9_rts: qup-uart9-rts-pins { + qup_uart9_rts: qup-uart9-rts-state { pins =3D "gpio37"; function =3D "qup11"; }; =20 - qup_uart9_tx: qup-uart9-tx-pins { + qup_uart9_tx: qup-uart9-tx-state { pins =3D "gpio38"; function =3D "qup11"; }; =20 - qup_uart9_rx: qup-uart9-rx-pins { + qup_uart9_rx: qup-uart9-rx-state { pins =3D "gpio39"; function =3D "qup11"; }; =20 - qup_uart10_cts: qup-uart10-cts-pins { + qup_uart10_cts: qup-uart10-cts-state { pins =3D "gpio40"; function =3D "qup12"; }; =20 - qup_uart10_rts: qup-uart10-rts-pins { + qup_uart10_rts: qup-uart10-rts-state { pins =3D "gpio41"; function =3D "qup12"; }; =20 - qup_uart10_tx: qup-uart10-tx-pins { + qup_uart10_tx: qup-uart10-tx-state { pins =3D "gpio42"; function =3D "qup12"; }; =20 - qup_uart10_rx: qup-uart10-rx-pins { + qup_uart10_rx: qup-uart10-rx-state { pins =3D "gpio43"; function =3D "qup12"; }; =20 - qup_uart11_cts: qup-uart11-cts-pins { + qup_uart11_cts: qup-uart11-cts-state { pins =3D "gpio44"; function =3D "qup13"; }; =20 - qup_uart11_rts: qup-uart11-rts-pins { + qup_uart11_rts: qup-uart11-rts-state { pins =3D "gpio45"; function =3D "qup13"; }; =20 - qup_uart11_tx: qup-uart11-tx-pins { + qup_uart11_tx: qup-uart11-tx-state { pins =3D "gpio46"; function =3D "qup13"; }; =20 - qup_uart11_rx: qup-uart11-rx-pins { + qup_uart11_rx: qup-uart11-rx-state { pins =3D "gpio47"; function =3D "qup13"; }; =20 - qup_uart12_cts: qup-uart12-cts-pins { + qup_uart12_cts: qup-uart12-cts-state { pins =3D "gpio48"; function =3D "qup14"; }; =20 - qup_uart12_rts: qup-uart12-rts-pins { + qup_uart12_rts: qup-uart12-rts-state { pins =3D "gpio49"; function =3D "qup14"; }; =20 - qup_uart12_tx: qup-uart12-tx-pins { + qup_uart12_tx: qup-uart12-tx-state { pins =3D "gpio50"; function =3D "qup14"; }; =20 - qup_uart12_rx: qup-uart12-rx-pins { + qup_uart12_rx: qup-uart12-rx-state { pins =3D "gpio51"; function =3D "qup14"; }; =20 - qup_uart13_cts: qup-uart13-cts-pins { + qup_uart13_cts: qup-uart13-cts-state { pins =3D "gpio52"; function =3D "qup15"; }; =20 - qup_uart13_rts: qup-uart13-rts-pins { + qup_uart13_rts: qup-uart13-rts-state { pins =3D "gpio53"; function =3D "qup15"; }; =20 - qup_uart13_tx: qup-uart13-tx-pins { + qup_uart13_tx: qup-uart13-tx-state { pins =3D "gpio54"; function =3D "qup15"; }; =20 - qup_uart13_rx: qup-uart13-rx-pins { + qup_uart13_rx: qup-uart13-rx-state { pins =3D "gpio55"; function =3D "qup15"; }; =20 - qup_uart14_cts: qup-uart14-cts-pins { + qup_uart14_cts: qup-uart14-cts-state { pins =3D "gpio56"; function =3D "qup16"; }; =20 - qup_uart14_rts: qup-uart14-rts-pins { + qup_uart14_rts: qup-uart14-rts-state { pins =3D "gpio57"; function =3D "qup16"; }; =20 - qup_uart14_tx: qup-uart14-tx-pins { + qup_uart14_tx: qup-uart14-tx-state { pins =3D "gpio58"; function =3D "qup16"; }; =20 - qup_uart14_rx: qup-uart14-rx-pins { + qup_uart14_rx: qup-uart14-rx-state { pins =3D "gpio59"; function =3D "qup16"; }; =20 - qup_uart15_cts: qup-uart15-cts-pins { + qup_uart15_cts: qup-uart15-cts-state { pins =3D "gpio60"; function =3D "qup17"; }; =20 - qup_uart15_rts: qup-uart15-rts-pins { + qup_uart15_rts: qup-uart15-rts-state { pins =3D "gpio61"; function =3D "qup17"; }; =20 - qup_uart15_tx: qup-uart15-tx-pins { + qup_uart15_tx: qup-uart15-tx-state { pins =3D "gpio62"; function =3D "qup17"; }; =20 - qup_uart15_rx: qup-uart15-rx-pins { + qup_uart15_rx: qup-uart15-rx-state { pins =3D "gpio63"; function =3D "qup17"; }; =20 - sdc1_clk: sdc1-clk-pins { + sdc1_clk: sdc1-clk-state { pins =3D "sdc1_clk"; }; =20 - sdc1_cmd: sdc1-cmd-pins { + sdc1_cmd: sdc1-cmd-state { pins =3D "sdc1_cmd"; }; =20 - sdc1_data: sdc1-data-pins { + sdc1_data: sdc1-data-state { pins =3D "sdc1_data"; }; =20 - sdc1_rclk: sdc1-rclk-pins { + sdc1_rclk: sdc1-rclk-state { pins =3D "sdc1_rclk"; }; =20 - sdc1_clk_sleep: sdc1-clk-sleep-pins { + sdc1_clk_sleep: sdc1-clk-sleep-state { pins =3D "sdc1_clk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_cmd_sleep: sdc1-cmd-sleep-pins { + sdc1_cmd_sleep: sdc1-cmd-sleep-state { pins =3D "sdc1_cmd"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_data_sleep: sdc1-data-sleep-pins { + sdc1_data_sleep: sdc1-data-sleep-state { pins =3D "sdc1_data"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc1_rclk_sleep: sdc1-rclk-sleep-pins { + sdc1_rclk_sleep: sdc1-rclk-sleep-state { pins =3D "sdc1_rclk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_clk: sdc2-clk-pins { + sdc2_clk: sdc2-clk-state { pins =3D "sdc2_clk"; }; =20 - sdc2_cmd: sdc2-cmd-pins { + sdc2_cmd: sdc2-cmd-state { pins =3D "sdc2_cmd"; }; =20 - sdc2_data: sdc2-data-pins { + sdc2_data: sdc2-data-state { pins =3D "sdc2_data"; }; =20 - sdc2_clk_sleep: sdc2-clk-sleep-pins { + sdc2_clk_sleep: sdc2-clk-sleep-state { pins =3D "sdc2_clk"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_cmd_sleep: sdc2-cmd-sleep-pins { + sdc2_cmd_sleep: sdc2-cmd-sleep-state { pins =3D "sdc2_cmd"; drive-strength =3D <2>; bias-bus-hold; }; =20 - sdc2_data_sleep: sdc2-data-sleep-pins { + sdc2_data_sleep: sdc2-data-sleep-state { pins =3D "sdc2_data"; drive-strength =3D <2>; bias-bus-hold; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA5F3C04A95 for ; Sun, 25 Sep 2022 11:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232769AbiIYLGz (ORCPT ); Sun, 25 Sep 2022 07:06:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231994AbiIYLGY (ORCPT ); Sun, 25 Sep 2022 07:06:24 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ECE431ECC for ; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:18 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 05/15] arm64: dts: qcom: sc7280-herobrine: correct number of gpio-line-names Date: Sun, 25 Sep 2022 13:05:58 +0200 Message-Id: <20220925110608.145728-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are 175 GPIOs (gpio0-174). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64= /boot/dts/qcom/sc7280-herobrine-crd.dts index f0f26af1e421..4e0b013e25f4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -372,5 +372,6 @@ &tlmm { "", /* 170 */ "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", + "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch= /arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts index ccbe50b6249a..739e81bd6d68 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts @@ -328,6 +328,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index c1a671968725..c8ff13db30b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -358,6 +358,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch= /arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 4566722bf4dd..3dff610fb946 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -321,6 +321,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64FA3C6FA82 for ; Sun, 25 Sep 2022 11:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232504AbiIYLGt (ORCPT ); Sun, 25 Sep 2022 07:06:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232029AbiIYLGY (ORCPT ); Sun, 25 Sep 2022 07:06:24 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571AB31ED5 for ; Sun, 25 Sep 2022 04:06:22 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id bu25so4876874lfb.3 for ; Sun, 25 Sep 2022 04:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ZUzEaSllhqvzoVgJ7uqfQ1HJ9zhADuolKSzj+1WZwig=; b=oUjLFV5ndMlH6do8ocKXpCh33Dd8hcfHbop7KuwzwO8Q9v+hS35Ie4D7rmwbuRvw7U d5ADwhgfqfbdRUTcqfrVJZwmiglngMRS3w5dBnaV2x2BR9j59z+w42XBZU9w4c66BHs+ WhA0v41RFSGG8GOXLVNQDsGHfZPjYCsnrLCW4wjZ9mJhQiGjNMjchd77QNmtpWyUT/5P bShsxhN++s4omRHiz2eCwGRQ0QGVqR6btt2k777Bygv9E1kLgfG9+Oj668ygPIrI0TV6 iLm2j7qz3XUFwaA3cPDCOrkCFfC46Wy9bCUhXwAZg1yzKDFKfrVMI/IeJ+YkwGbtkUCX xu0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ZUzEaSllhqvzoVgJ7uqfQ1HJ9zhADuolKSzj+1WZwig=; b=KzK+NYioTzWvvnonUtK+MYB7ZKfFZOCBM7wIyy2/LF/LQNANo3iAyEJTV0/81aWoeE pQXDK2dUqRiX8mTzWtqwZVYkWEe74aiKwBKOk4KYj2iS6yFtLEyA2lKYT1YAsHQrF5E8 ypuXANyj/Yiop5JKm9L+klYWOXwfT6zcg1dqd15Wjp8/DojDoxYAvWbQ22OQSN1PsI7i rVsxMEEEq9XGbIhewiRAUbCqHvlrFYHekWgVPENuCxThgRMb4E7oe01AWi8UNdwESYwa +rYonPcgB7wtRAeefTA9+jQuwohvlsnnaSd17vRSYno+czAyw3rdJxnMhU3k1ckRPLaN berg== X-Gm-Message-State: ACrzQf208RIZuo/YG0NidfH6jJiozMueEv9WRIyZ2U8vAhP1CcmXym65 0FUJayY2FEYRQSMQ85Aamt3hJQ== X-Google-Smtp-Source: AMsMyM4b7i4gt7nRpoAFCdZhF5YO4Q43RnApfftf20qkRe/DF9WBCdcm6hl9GPG3NOGiWbL+3NLJ8A== X-Received: by 2002:a05:6512:3a88:b0:49f:5648:87fc with SMTP id q8-20020a0565123a8800b0049f564887fcmr6480651lfu.143.1664103980586; Sun, 25 Sep 2022 04:06:20 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:20 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 06/15] arm64: dts: qcom: sc7280-idp-ec-h1: add missing QUP GPIO functions Date: Sun, 25 Sep 2022 13:05:59 +0200 Message-Id: <20220925110608.145728-7-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add default GPIO function to SPI10 and SPI14 chip-select pins on SC7280 IDP, as required by bindings. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index b35f3738933c..3cfeb118d379 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -95,11 +95,13 @@ h1_ap_int_odl: h1-ap-int-odl-state { =20 qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins =3D "gpio43"; + function =3D "gpio"; output-high; }; =20 qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins =3D "gpio59"; + function =3D "gpio"; output-high; }; }; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 227A5C04A95 for ; Sun, 25 Sep 2022 11:07:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232833AbiIYLHA (ORCPT ); Sun, 25 Sep 2022 07:07:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232314AbiIYLGY (ORCPT ); Sun, 25 Sep 2022 07:06:24 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2855D31ECA for ; Sun, 25 Sep 2022 04:06:22 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id x29so4635999ljq.2 for ; Sun, 25 Sep 2022 04:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PIf5lS5eiFlvx8Q7bNQDnxAmu2D0wzgz/3fhk0Yq79k=; b=nQxFx48EQD5BJ7IzPSUkdqMunlxhqg26lRJ/CQfpYIztBQeY0sDNYXxiHaqN01P2cG W0a2fp7Y8ULgbwzNrLqlwHkcpYNlE2IHcdmxdsZ5/GyK6Z1beLtAghXrEp8z2at/gvU+ RNkChxZYJAizIT4fHyL5Ig9ijnAWPnqT+GRuqGP8768Ri/Y/oQ50gP+pM309tu6x0bXe FJEbieF63dcETQ5NlAGuiwLXIwCqqpbZxeBiWR8KkxNcDS44G82MWq8WHIC6rPbqdw0/ sWpKUT99s6La9cRMPRoMbP1b4sExfF4UqO3AGhynJAS2b0FSDlYg/OPelqXzyxq990xh K43w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PIf5lS5eiFlvx8Q7bNQDnxAmu2D0wzgz/3fhk0Yq79k=; b=L/y2kTW627075IuIxYYjZI9bPcJqblfqQ8So+uaiviYlx7Khvf0kdX9M/1ei+rcE+i ssMrdNNI19pBWNsIETagqMe5YhvzVsrMmN/rmfUCviKhlpCIOAm22xvh6Iz8/F9RpBMt z4q8d7KCUWeLWibi6VADbYSBfbDihwDsF/qLLgRHLhaXlrcq7ZU25iLY3+pc1ucpiA00 x23bfPS7VLBBJFxcmbCpfuOoVmJt6PlpK1Tee3Chyb0q0J53gYp7feHiCloPLuAdLhc/ /SyaBMNOx3KBcHH5972abyUXdrAK1waBBX2tNlzdGabcNjEPmqJjZpgE7GyaRgmPQeDy K5Iw== X-Gm-Message-State: ACrzQf0AFmajyOlj7PTHkhLI+AbHlgAQIVKaTSRU8hpNat3GIwzA4lQL jZEc0zWyf1xikZ3XxlhbwfI9zg== X-Google-Smtp-Source: AMsMyM5QmqFE+3Dj261av4khX95/Dk3QtGvKf9NK4QJ4gVZfRGuZeSAK+rvPUQFne0JL4l9vuRFszA== X-Received: by 2002:a2e:9886:0:b0:26c:57d9:10c6 with SMTP id b6-20020a2e9886000000b0026c57d910c6mr5491416ljj.309.1664103981612; Sun, 25 Sep 2022 04:06:21 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:21 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 07/15] arm64: dts: qcom: msm8953: align TLMM pin configuration with DT schema Date: Sun, 25 Sep 2022 13:06:00 +0200 Message-Id: <20220925110608.145728-8-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm632-fairphone-fp3.dtb: pinctrl@1000000: 'cd-off-pins', 'cd-on-pin= s', 'gpio-key-default-pins', .... do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 70 +++++++++++++-------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index 6b992a6d56c1..db94e6fd18f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -460,229 +460,229 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells =3D <2>; =20 - uart_console_active: uart-console-active-pins { + uart_console_active: uart-console-active-state { pins =3D "gpio4", "gpio5"; function =3D "blsp_uart2"; drive-strength =3D <2>; bias-disable; }; =20 - uart_console_sleep: uart-console-sleep-pins { + uart_console_sleep: uart-console-sleep-state { pins =3D "gpio4", "gpio5"; function =3D "blsp_uart2"; drive-strength =3D <2>; bias-pull-down; }; =20 - sdc1_clk_on: sdc1-clk-on-pins { + sdc1_clk_on: sdc1-clk-on-state { pins =3D "sdc1_clk"; bias-disable; drive-strength =3D <16>; }; =20 - sdc1_clk_off: sdc1-clk-off-pins { + sdc1_clk_off: sdc1-clk-off-state { pins =3D "sdc1_clk"; bias-disable; drive-strength =3D <2>; }; =20 - sdc1_cmd_on: sdc1-cmd-on-pins { + sdc1_cmd_on: sdc1-cmd-on-state { pins =3D "sdc1_cmd"; bias-disable; drive-strength =3D <10>; }; =20 - sdc1_cmd_off: sdc1-cmd-off-pins { + sdc1_cmd_off: sdc1-cmd-off-state { pins =3D "sdc1_cmd"; bias-disable; drive-strength =3D <2>; }; =20 - sdc1_data_on: sdc1-data-on-pins { + sdc1_data_on: sdc1-data-on-state { pins =3D "sdc1_data"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc1_data_off: sdc1-data-off-pins { + sdc1_data_off: sdc1-data-off-state { pins =3D "sdc1_data"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc1_rclk_on: sdc1-rclk-on-pins { + sdc1_rclk_on: sdc1-rclk-on-state { pins =3D "sdc1_rclk"; bias-pull-down; }; =20 - sdc1_rclk_off: sdc1-rclk-off-pins { + sdc1_rclk_off: sdc1-rclk-off-state { pins =3D "sdc1_rclk"; bias-pull-down; }; =20 - sdc2_clk_on: sdc2-clk-on-pins { + sdc2_clk_on: sdc2-clk-on-state { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - sdc2_clk_off: sdc2-clk-off-pins { + sdc2_clk_off: sdc2-clk-off-state { pins =3D "sdc2_clk"; bias-disable; drive-strength =3D <2>; }; =20 - sdc2_cmd_on: sdc2-cmd-on-pins { + sdc2_cmd_on: sdc2-cmd-on-state { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc2_cmd_off: sdc2-cmd-off-pins { + sdc2_cmd_off: sdc2-cmd-off-state { pins =3D "sdc2_cmd"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc2_data_on: sdc2-data-on-pins { + sdc2_data_on: sdc2-data-on-state { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <10>; }; =20 - sdc2_data_off: sdc2-data-off-pins { + sdc2_data_off: sdc2-data-off-state { pins =3D "sdc2_data"; bias-pull-up; drive-strength =3D <2>; }; =20 - sdc2_cd_on: cd-on-pins { + sdc2_cd_on: cd-on-state { pins =3D "gpio133"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; =20 - sdc2_cd_off: cd-off-pins { + sdc2_cd_off: cd-off-state { pins =3D "gpio133"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - gpio_key_default: gpio-key-default-pins { + gpio_key_default: gpio-key-default-state { pins =3D "gpio85"; function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; =20 - i2c_1_default: i2c-1-default-pins { + i2c_1_default: i2c-1-default-state { pins =3D "gpio2", "gpio3"; function =3D "blsp_i2c1"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_1_sleep: i2c-1-sleep-pins { + i2c_1_sleep: i2c-1-sleep-state { pins =3D "gpio2", "gpio3"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_2_default: i2c-2-default-pins { + i2c_2_default: i2c-2-default-state { pins =3D "gpio6", "gpio7"; function =3D "blsp_i2c2"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_2_sleep: i2c-2-sleep-pins { + i2c_2_sleep: i2c-2-sleep-state { pins =3D "gpio6", "gpio7"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_3_default: i2c-3-default-pins { + i2c_3_default: i2c-3-default-state { pins =3D "gpio10", "gpio11"; function =3D "blsp_i2c3"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_3_sleep: i2c-3-sleep-pins { + i2c_3_sleep: i2c-3-sleep-state { pins =3D "gpio10", "gpio11"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_4_default: i2c-4-default-pins { + i2c_4_default: i2c-4-default-state { pins =3D "gpio14", "gpio15"; function =3D "blsp_i2c4"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_4_sleep: i2c-4-sleep-pins { + i2c_4_sleep: i2c-4-sleep-state { pins =3D "gpio14", "gpio15"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_5_default: i2c-5-default-pins { + i2c_5_default: i2c-5-default-state { pins =3D "gpio18", "gpio19"; function =3D "blsp_i2c5"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_5_sleep: i2c-5-sleep-pins { + i2c_5_sleep: i2c-5-sleep-state { pins =3D "gpio18", "gpio19"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_6_default: i2c-6-default-pins { + i2c_6_default: i2c-6-default-state { pins =3D "gpio22", "gpio23"; function =3D "blsp_i2c6"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_6_sleep: i2c-6-sleep-pins { + i2c_6_sleep: i2c-6-sleep-state { pins =3D "gpio22", "gpio23"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_7_default: i2c-7-default-pins { + i2c_7_default: i2c-7-default-state { pins =3D "gpio135", "gpio136"; function =3D "blsp_i2c7"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_7_sleep: i2c-7-sleep-pins { + i2c_7_sleep: i2c-7-sleep-state { pins =3D "gpio135", "gpio136"; function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; =20 - i2c_8_default: i2c-8-default-pins { + i2c_8_default: i2c-8-default-state { pins =3D "gpio98", "gpio99"; function =3D "blsp_i2c8"; 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:22 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 08/15] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Date: Sun, 25 Sep 2022 13:06:01 +0200 Message-Id: <20220925110608.145728-9-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm845-lg-judyln.dtb: gpios@c000: 'vol-up-active-pins' does not matc= h any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/bo= ot/dts/qcom/sdm845-lg-common.dtsi index 20f275f8694d..1eb423e4be24 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -604,7 +604,7 @@ pinconf { }; =20 &pm8998_gpio { - vol_up_pin_a: vol-up-active-pins { + vol_up_pin_a: vol-up-active-state { pins =3D "gpio6"; function =3D "normal"; input-enable; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A5EC04A95 for ; Sun, 25 Sep 2022 11:07:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233009AbiIYLHQ (ORCPT ); Sun, 25 Sep 2022 07:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231887AbiIYLGc (ORCPT ); Sun, 25 Sep 2022 07:06:32 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFE34326C3 for ; Sun, 25 Sep 2022 04:06:25 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id u18so6755285lfo.8 for ; Sun, 25 Sep 2022 04:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Ltd+pnwzPyeoA6eImt7eQVAAefud/sfm9oMKcojNkgE=; b=tlLlTMpTqrKh2WFQxL0HxNPtdRO4n/J/OM+kRemabxcSv9/uTCsvSxp/EsJEuEEloT 7aHKKjmatBWss8LjUYe9lwWMzBLV2357i+qCsMXVsSwM654tuDXcXlJWUw/hc+8qkdos U2Jw8NbRsMO6KPt2y7qXPnge9OFyvK994HDQX+bhYkgiKvdisDeBqlbMdjxIhnZ5wunm nAAcofJ4QOWGr+Uodn24B2o2RNDCofxT4M9XN+KI1XNU4Ez8Lw/7+UwtJetT+9bWsMWX LYQ/UY5peaR+fFehrp+0pNULIY8Si8LXuwuewdy61wcVKjTxzCQUGr/eraIK+v92qASn LmEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Ltd+pnwzPyeoA6eImt7eQVAAefud/sfm9oMKcojNkgE=; b=Im+5RIUUd+RxVQ9omTfGg8InUSNAEt7Wtzzpys9W2pfSkEIBk2T4e2K5+vGheyI3tg lxjMxMQo+T5Dv/ionODeIc1WqWVzxBJdE0f5gzWBJ0vR29e1tbWsLXCrA7kXV/yV7PJx mp+dHYE1TCrSrA0j7/s4Db3uDVCLlKA841BA8xArGR7hWQC1K9aczPIz8Jy5SD6Vb5AP Q3UEX5uEs+dNIiVWjFWGq4wStGvZEAXpbaG08cTK5Voa7ERfnd9pUUcUsm9gYuQPYbrs rUP/Sdz2qHyyYeLRlu1tAtalzozd2s6qlXu3fBHgg6pQ7KqOClt6nNWZabKRVOeJu4Jv ougQ== X-Gm-Message-State: ACrzQf3WFl1fnpGxIqL1PhoZVrRzbHThwWD9RJ2gCvvVPSZdzUlYEBpD v656LR9Js36qu61K1IO5wwIJ7A== X-Google-Smtp-Source: AMsMyM57t13wYv+t4apXeTo8L58bPl0in9J6WQ8xwsyPKvSKngP7eSxTQLlL2f2v+koI5KRxQNjDdQ== X-Received: by 2002:a05:6512:3403:b0:48c:9727:50b0 with SMTP id i3-20020a056512340300b0048c972750b0mr6404437lfr.309.1664103983645; Sun, 25 Sep 2022 04:06:23 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:23 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 09/15] arm64: dts: qcom: sm6125-sony-xperia: add missing SD CD GPIO functions Date: Sun, 25 Sep 2022 13:06:02 +0200 Message-Id: <20220925110608.145728-10-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add default GPIO function to SD card detect pins on SM6125 Sony Xperia, as required by bindings: qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: sdc2-off-state:= 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'cmd-pins', 'data-pins', 'sd-cd-pins' do not match any of t= he regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b= /arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 6a8b88cc4385..9af4b76fa6d7 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -89,6 +89,7 @@ &hsusb_phy1 { &sdc2_off_state { sd-cd-pins { pins =3D "gpio98"; + function =3D "gpio"; drive-strength =3D <2>; bias-disable; }; @@ -97,6 +98,7 @@ sd-cd-pins { &sdc2_on_state { sd-cd-pins { pins =3D "gpio98"; + function =3D "gpio"; drive-strength =3D <2>; bias-pull-up; }; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B23AEC04A95 for ; Sun, 25 Sep 2022 11:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232743AbiIYLHL (ORCPT ); Sun, 25 Sep 2022 07:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232566AbiIYLG2 (ORCPT ); Sun, 25 Sep 2022 07:06:28 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E49632048 for ; Sun, 25 Sep 2022 04:06:25 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id l12so4587806ljg.9 for ; Sun, 25 Sep 2022 04:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=RktSTcq3H5K8cHqTQr3Yf2+8uyprOBIhojh+e4mNQp4=; b=l06ERLARHFaw2C3l79m4hdGEQ5hP5sCW8oJSqQJ+pTSNb+TNSerspOXmApfYLF6eTT h4eJ4JrVezLAMjJ9YMSquAMm6xAJcheRTJl5hWLdiuaHRz0VXVELG6iEXiQOdTBn4z0N DpP4rBGOSDLB2pxemS7gTG2I2jktsZgKZIBZ8G2bhDragzAFV/uPdqqcgG6T+HI7C2Wt Dd6yiFi1y/EK8NN322/4wOg35NFiGZq+GegddSv40OgC3slZpr/tktIM4QShJWnsfMzh jWokUoy6MhJZugEj1Q1/6Z36++ovR9SBNTe/e00IpfrpEkFYT+ZFIi6l4ltCi4wa+Kqx HZfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=RktSTcq3H5K8cHqTQr3Yf2+8uyprOBIhojh+e4mNQp4=; b=IdUAZ7OUbWiDV7DkOplQquQkM9di7wkP0UTENfhoimBAAyPHXOXK78GO+SsX9Pbnpz RnmlHDPpLd5h00fNVL+3182RKhManDhW2fR2QbiuDnN7ZoNJ4Al/ISt7KHLz1faOAiRE pe1QGuN/KNCs1b2btv8rZdPMKCZqkWrK6AtuS5/YbvLzsqweyZIxJcgJe60xZT6xfOij hoY3hQadDXkLUbmiEXjytH5wda7JJX3PDsV5tPa8vFfYJhmUEINTEsvkAGimcUS4ZWm0 MUHUvFaeJWrqREL1w7r1w4qBmazkxooLsrqjyRMi+5kZfuhSCc6kUTFI1UDflUejsC30 8PGg== X-Gm-Message-State: ACrzQf1G9Mi3CWlRjMRAUJ0fmWSwejBWLgStjTc7gfGO0Io9J3/Y1lCY nQvt4iVcfpImBPjeNqsNMpnxHA== X-Google-Smtp-Source: AMsMyM4cddoHnv3mAdRS7zpT4z3TQb+pEIcd96DKWxxHxwIYJJHyzQa39m5rP/hwPFfCjtvGslbWcg== X-Received: by 2002:a05:651c:227:b0:26a:b322:b243 with SMTP id z7-20020a05651c022700b0026ab322b243mr5504422ljn.13.1664103984591; Sun, 25 Sep 2022 04:06:24 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:24 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 10/15] arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema Date: Sun, 25 Sep 2022 13:06:03 +0200 Message-Id: <20220925110608.145728-11-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 1fe3fa3ad877..af49a748e511 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -407,13 +407,13 @@ data-pins { }; =20 sdc2_on_state: sdc2-on-state { - clk { + clk-pins { pins =3D "sdc2_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd-pins-pins { + cmd-pins { pins =3D "sdc2_cmd"; drive-strength =3D <10>; bias-pull-up; --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13443C6FA82 for ; Sun, 25 Sep 2022 11:07:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233029AbiIYLH0 (ORCPT ); Sun, 25 Sep 2022 07:07:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232473AbiIYLGn (ORCPT ); Sun, 25 Sep 2022 07:06:43 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0DCB326EC for ; Sun, 25 Sep 2022 04:06:27 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id i26so6730632lfp.11 for ; Sun, 25 Sep 2022 04:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aNLcQQxhPdFOgwRsvgsgtamBjwIOHo82jCWuV4BIKpM=; b=jhrnCb/Fnu5wUNoCrnU7J6oEwA36I+carel3+GeIXo3O64+NhfX1igqSU+OMZcJoIl FO5V4Uj2NKbTH2jRVxTmMU2q4DJEoQPqGgOAllwV2vnRiO+vsipU8JnyDm3kFc17zyLI atdtsSHSpaTBjd1saeK72U1nPuerTAy4+O0pqW4d8A1uihYB35LnCbGDiY69gSjdUguA FdaHFsjX0KE1Efwl92ljN1U1xOkStbp8KtKWCAG7clw50OPOecxh7ke51SvmWLq2eLdX 4FduUBYWk8wXv8LwPGGTev5mSbPpXCmqvecwR7r4eX0jgp/kbCe/wSnix7jc8sAHfZMr NKRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aNLcQQxhPdFOgwRsvgsgtamBjwIOHo82jCWuV4BIKpM=; b=Qdtbr5d2ULRHbrr0SR5hZmJlmXSvNbp0DPgbXWc7wZBsfX/LrHp4S08Y1GqcggeRP4 KneG3phlbtHUErtldllZSHBdfsQF9yJfQjlVNHQWU1sLJBBq9IfdZDBfteE/0XCOhRs1 fcABxSzT5zf0b7U7pWyQvuZXi3PLGWZ9VEwQZE+yUfRpDU49O3WkDXprcyqHVFss3k5z tnM98nuMQK4wLR24crZbaNA5TYhTxrH8JTiIhYowFSwZUkuZWHyPFP91sdilEip7FW4b V3l5uAHZ8YbutwtShTBh4CWPipYnTDcDtEnOxaHpDoEVfFUM69/aII0XlUgCg9eEIwc5 4UjA== X-Gm-Message-State: ACrzQf01DvvX3EGMysRxiDoMeoXvmEk0U8tpulR5cgAeCvvvhYXeuXsV VgWWAj0vm+1DjY3hDxwQ2vL53g== X-Google-Smtp-Source: AMsMyM56CWbj1FJw/0qknzbYyh2y3pGIMvVHX90IMH40I9yAU3a7RcLmecGWI5czIsSEJGRZO/amMA== X-Received: by 2002:a05:6512:3b8e:b0:49a:d2f4:6b7d with SMTP id g14-20020a0565123b8e00b0049ad2f46b7dmr6324123lfv.627.1664103985707; Sun, 25 Sep 2022 04:06:25 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:25 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 11/15] dt-bindings: pinctrl: qcom,sm8250: add gpio-reserved-ranges and gpio-line-names Date: Sun, 25 Sep 2022 13:06:04 +0200 Message-Id: <20220925110608.145728-12-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document common GPIO properties (gpio-reserved-ranges and gpio-line-names), already used on qrb5165-rb5 board. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Konrad Dybcio --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index c44d02d28bc9..d7d8e5d3b659 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -49,6 +49,13 @@ properties: gpio-ranges: maxItems: 1 =20 + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 180 + wakeup-parent: true =20 #PIN CONFIGURATION NODES --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74B3DC6FA82 for ; Sun, 25 Sep 2022 11:07:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232816AbiIYLHW (ORCPT ); Sun, 25 Sep 2022 07:07:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232648AbiIYLGd (ORCPT ); Sun, 25 Sep 2022 07:06:33 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C37D326D4 for ; Sun, 25 Sep 2022 04:06:27 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id w8so6727863lft.12 for ; Sun, 25 Sep 2022 04:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=VSmY5xCkqiUsI4yIOTfQRDN1TkL1CLqf4sQwb5AGTxQ=; b=CL2wvxjrpI5m4RFjdiR5YX7W1keSnVPz4ThoUmZTYvg5yqMhzIj0GaOLFgYcD9O+Qz VfBVJL854P7vyabGSCRSUj12DTIEFF3l0MxSRZrKfJdR49UnzH6gvmMpbHzkSwicJXOQ uH/bCR6fn0++LyGn8OfH+LlPqTD4UlihTS+6yB/7tTeEFIPRxx4/4LoBJFz47/dB7W+z BY8v6ZvxX41rvnBvKD2nT8g9NDWVMYilJoTc2YH4vtLxs71lTy3+5mQHIPmBAVvwaXil +SPfldLU/Df3gAPuTq3Ngqi2CcoktLQuGY9dMbtgMEyHwtAsiLxG9A+uuJILf+7MrZJs 8pag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=VSmY5xCkqiUsI4yIOTfQRDN1TkL1CLqf4sQwb5AGTxQ=; b=1qy/+4ukwM0ccoDClsO7gYMRYCGvt1d8JYlpkIzCJ70l5meqbvEzJUIl1C4XxEnhXT Jjv221BbsvIWzQKFWQ3Lc7fgCXiXg3NAOkarqG5adt9vqGWhzd5eQQkKtg4g5xqe6rxt o2E4G0xdzXXmogtuWj7xorpESF8XixHg+6965c4IQP6eQPaCaVXRPMhvnAmMCKwHAMA7 WZ0U5QWYu0EcBqR3lk7Ikw/mXud5vc59Uo60vwML/Q8Hg/UNdlT06ab5nXGCZM6rm2bL B/9V8p01gd9Wo0oVzOClsD+YE4iyrPBJOt5KuG+ZYV8COjHLG3WweWr9cTCvINQF9oP4 /S4Q== X-Gm-Message-State: ACrzQf0GobaJBreD5wI29IiqS4mP8dBXetN9Ojt3I2CQmb8SMK7zUoRF 1a7wWIZmiOpDc9IqQr1jhpNZzQ== X-Google-Smtp-Source: AMsMyM73q2RDaQcZoazF1ZKCRhvF5so9kyPxoFlYXT1HtJrWL8sn9+2NCd1sSBYbXeF+omu1bAF+aQ== X-Received: by 2002:ac2:4e03:0:b0:485:74c4:97ce with SMTP id e3-20020ac24e03000000b0048574c497cemr6417726lfr.13.1664103986653; Sun, 25 Sep 2022 04:06:26 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:26 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 12/15] dt-bindings: pinctrl: qcom,sm8250: fix matching pin config Date: Sun, 25 Sep 2022 13:06:05 +0200 Message-Id: <20220925110608.145728-13-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. The change causes indentation decrement, so the diff-hunk looks big, but there are no functional changes in the subnode "properties" section. The only difference there is removal of blank lines between common GPIO pinconf properties. Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 145 +++++++++--------- 1 file changed, 75 insertions(+), 70 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index d7d8e5d3b659..da708c748a36 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -58,77 +58,82 @@ properties: =20 wakeup-parent: true =20 -#PIN CONFIGURATION NODES patternProperties: - '^.*$': - if: - type: object - then: - properties: - pins: - description: - List of gpio pins affected by the properties specified in this - subnode. - items: - oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" - - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] - minItems: 1 - maxItems: 36 - - function: - description: - Specify the alternative function to be configured for the spec= ified - pins. - - enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_time= r4, cri_trng, - cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_p= xi1, - ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gc= c_gp3, gpio, - ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsyn= c0, - mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_d= ata1, - mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck= , mi2s1_ws, - mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, p= ci_e1, - pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll= _reset, - pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, = qspi2, qspi3, - qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup1= 3, qup14, - qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup= 5, qup6, - qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc4= 0, sdc41, - sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_= ch0, tgu_ch1, - tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, t= sif0_data, - tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data= , tsif1_en, - tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_tri= gger ] - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - required: - - pins - - allOf: - - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - - if: - properties: - pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" - then: - required: - - function - - additionalProperties: false + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8250-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8250-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8250-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4= , cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi= 1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_= gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_dat= a1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, = mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci= _e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_r= eset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qs= pi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13,= qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5,= qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40,= sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch= 0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsi= f0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, = tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigg= er ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + output-high: true + output-low: true + + required: + - pins + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + then: + required: + - function + + additionalProperties: false =20 allOf: - $ref: "pinctrl.yaml#" --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 341CBC6FA82 for ; Sun, 25 Sep 2022 11:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232888AbiIYLHi (ORCPT ); Sun, 25 Sep 2022 07:07:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232862AbiIYLHB (ORCPT ); Sun, 25 Sep 2022 07:07:01 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 389D432A9B for ; Sun, 25 Sep 2022 04:06:30 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id u18so6755421lfo.8 for ; Sun, 25 Sep 2022 04:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=riHAYzYkIc2g3zYGSZW+9OdMXMpN6SWKiUDVtnd2p8Y=; b=FAjG2hl/kiAqhLDcVs30vg9KGRJeyDjbX+BLWPM6AD3GAiEXRESAPtNZtRCNWiOHIR uCOQnrBon4O+kcR2vBQKqEc7Po4hwyA6SskwoIbY+wUWTqjSUc4iSIiwrA41eyFQb2AO gGExYOcYhmEbNNsoS6+yeLVNc2D8+YKUKBvogyofIkzH7kSkYV+KJXPMdBsw6e1b1vfu kUSlfrG998nV8pfJkdVx9RL1dw1rjCvEFJRanm7YhlbUNwrjJBh/3qZ8WT+TORhkreR+ nbhbwPbEDNurnYC3iNM0GFQd2m4D5PFzH8xusbTC71V510fMJV1Yfoop+js5Nf4PMpCV +5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=riHAYzYkIc2g3zYGSZW+9OdMXMpN6SWKiUDVtnd2p8Y=; b=b+OYDFJGJ9F0wWD90/4oVe6h5C4ZZe27YGB6q6cSrQ1c2Ajf8uLJ/hsIdfC6TQopgR VnJyWjXxKoVmpC59CMSbr0rKzFl+KkpNFP9KpVyrV9AQUN+cRjRRNF5tVo85LAXdbhSA HZmMdjom9x7v/eC+lSEy28oXauAJ6MXlrwYSyRBkpWYpsPaOEyI/bYg6VCHcUrDQF4Gp 4B/CrDV+s57YT4LcA8tTHT/6x6xQzWefT79tb4EVml0v+9YcY3RxV6GK7HeP2GDVKuOC tjLCxqnwcorKVLxLSlbOIvT+LcC6loomUQpy66IHViGwwRuytA3kPwmrL1dr4ngYoCRC Yglg== X-Gm-Message-State: ACrzQf2g6jOKGxpAUg6liwYIY8Aflu+6E810tMsg4vO6XTdpjdu+30c8 y+P09NjSZSEe0EhhWGu8bpuQsQ== X-Google-Smtp-Source: AMsMyM414UUOHEtN1KUwC+R69AWTqGrcOBpp9pJXFkZ8hSRwp3sFSvca/3y5uUcNxA3Kbu/o4Ga3Vw== X-Received: by 2002:a19:5f4b:0:b0:49f:a4b7:3f1c with SMTP id a11-20020a195f4b000000b0049fa4b73f1cmr6366363lfj.333.1664103987689; Sun, 25 Sep 2022 04:06:27 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:27 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 13/15] dt-bindings: pinctrl: qcom,sm8250: add input-enable Date: Sun, 25 Sep 2022 13:06:06 +0200 Message-Id: <20220925110608.145728-14-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SM8250 pinctrl driver supports input-enable and DTS already use it (sm8250-sony-xperia-edo-pdx203). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index da708c748a36..94f26a5ae3b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -117,6 +117,7 @@ $defs: bias-pull-down: true bias-pull-up: true bias-disable: true + input-enable: true output-high: true output-low: true =20 --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C258C6FA82 for ; Sun, 25 Sep 2022 11:07:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233039AbiIYLHc (ORCPT ); Sun, 25 Sep 2022 07:07:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232770AbiIYLGz (ORCPT ); Sun, 25 Sep 2022 07:06:55 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7862232A8B for ; Sun, 25 Sep 2022 04:06:29 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id s6so6761977lfo.7 for ; Sun, 25 Sep 2022 04:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rNmuq6Pz/aQimtSFRDztgTKbC2bR/H3agu5f7rLSCzg=; b=lhJfbmpDRntGIA0lyGbpPFdxSL7LkkbDcSHLKx5kr2eyNINm46ButiPOlF2FISPfxE 80sUZGn3W3k4q/PI+P8VdfSPssC1XVeXgAvb/GQteMnLUT3kj9127EDDjrI1ReAhYxgj zIAxzKcCEr4A4LPRIWYkqwjiHm4rpeq2i3ky14spG9fOtEc8l0gVq90KwTddK04nxh/7 +o1XViC/Xrb0pcIOpH3AlHdMFvrdcKct+NIBfV3+1cXPWrmqnsOLQrzCe/LAOLRSymeY 66vrUoj43MefTQXEOW2D3Hja7+yJbAalEFRsXY9Yb0MLNifujuB8ukeyTcHDUkuOIAJi /v9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rNmuq6Pz/aQimtSFRDztgTKbC2bR/H3agu5f7rLSCzg=; b=z/KD6tlealATaAzwQMDa9W41uUJ2cfnNPqGOEN0+fegZ7m40I85C+D5W06N2DrHbAS KLm6pSxcdF+0V3/q9EuudyzFdAtqYOjTQQPFLCaVtiH+t2WmH6yZN21v90j3tjdE3qxc tWy+goMPI09Zk24diB9MbPzWjxWEcbrh6ybY82toufMSvRNv3EyqelauJOHDdAUgfKr1 I7MEKFGlK1kYLvSPqvJTJvsNltoBV0t+pf3aIEC/ZH+ISLP8kCRSeBJSQLE5jAri1AqY 7jfkrBSrxcwi/tnpD1xf29pL24qxQlv4JlEI7M248EV1iHUUegfsk+mFuBwBO1L1qMOT 5/2g== X-Gm-Message-State: ACrzQf0SVJ7o0efbdR9CCmiRtJEoB1VP+Edko5nqG2W46AnauDI++E9a 4dmgomf5VL1U9f4X5aR2tzZrMQ== X-Google-Smtp-Source: AMsMyM4txj2HUIrIkQAQSjBq6E0F7asYTAwikStWbcb62DKC9PGIn9NKOhN8u2/lAgEiptWnmHq0BQ== X-Received: by 2002:a05:6512:31ce:b0:49a:d42f:f4a3 with SMTP id j14-20020a05651231ce00b0049ad42ff4a3mr6681567lfe.171.1664103988770; Sun, 25 Sep 2022 04:06:28 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:28 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 14/15] dt-bindings: pinctrl: qcom,sc7280: add bias-bus-hold and input-enable Date: Sun, 25 Sep 2022 13:06:07 +0200 Message-Id: <20220925110608.145728-15-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SC7280 pinctrl driver supports bias-bus-hold and input-enable, and DTS already use it (sc7280-idp). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 4606ca980dc4..1db05c43d58c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -117,13 +117,11 @@ $defs: Selects the drive strength for the specified pins, in mA. =20 bias-pull-down: true - bias-pull-up: true - + bias-bus-hold: true bias-disable: true - + input-enable: true output-high: true - output-low: true =20 required: --=20 2.34.1 From nobody Thu Apr 2 13:34:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D1A0C04A95 for ; Sun, 25 Sep 2022 11:07:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233074AbiIYLHn (ORCPT ); Sun, 25 Sep 2022 07:07:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232873AbiIYLHB (ORCPT ); Sun, 25 Sep 2022 07:07:01 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5959C31EEB for ; Sun, 25 Sep 2022 04:06:32 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id i26so6730774lfp.11 for ; Sun, 25 Sep 2022 04:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6qiFysm9YOq22jr+04Jj1ATXUz8nTarw0VSyiTjbRuo=; b=KQj4Lxpy7J5c5gtfdn2MCnns59x82sYbZgv+SsKYGc+KtkPtQbxD9V5MkvijEtFyop jWaT/Pr8UzaITtZMpFladmxahteM8r9ioOmcbUY0Hjy0TLxqt3vdxo18/9pfQqOaaroh uShMvSt9QU+U9eIGk3G3X/dyK+m1Hoktrh8qT9X+EGLy/4lKUikwo+BoogkZE91S0/Sv JRTYnbzoRIy8bQWk4J0RsFOR8zOXWzX2rVVTnGsuO22Fm1uCqQnaR3LQl5utfJOJXDIQ dw/HvaUkKjlP1KrQ2iXnlStpbSIBfQkX/zwXzD8vzO23hplm+UiLWIur5cWzWr8s2TTw KcnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6qiFysm9YOq22jr+04Jj1ATXUz8nTarw0VSyiTjbRuo=; b=5Kxkhk4ZXgErpUsmDg95/W6eBMfDLlxmxY5WQSV9i11rmAt50Ld5jz5STC+Z5MetBj 3i2JIdLmzLMbNzzKx/HOLYqTcj5LSOpFic3Nsb7WpljR3aPrITIxreJiFtKT19gbVzwe SB0keIfWL9XVN3oo1uKJM9Fj6H5e8+I4ugHYArG1SiF+UK4dYwNQb5xtuTK+eaJpAJE/ /1TtqGLzUK8PDSSlS0fOiyGp2ND8c6/dJTPJWMJpPnuqyI+rGCJoKLMP5sGm37cbRVsN JzEYwJ/c/tjlFd/ogHEtYjqCH34PsMZpHzIdK74J3FnIyUqCUjfq169d+4gTThN0m2Gr DXiw== X-Gm-Message-State: ACrzQf2/c9UVBEQFGiZilqwjxyl5bQqFB6PUf9DS9E07ahiqNDlG4Aj/ UZgp9mH1Wqowkk67KpjHNs91Jw== X-Google-Smtp-Source: AMsMyM7oWDuDuRm2HN3Eq/tJq4ODnuaLzn5fRVS06W0QrFg8y8fwIm4+jL3RjWbiYRuP+iBkrdqwjA== X-Received: by 2002:a05:6512:1289:b0:49f:1b3d:88c5 with SMTP id u9-20020a056512128900b0049f1b3d88c5mr6834604lfs.499.1664103989735; Sun, 25 Sep 2022 04:06:29 -0700 (PDT) Received: from krzk-bin.. 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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u19-20020ac258d3000000b00492dadd8143sm2177265lfo.168.2022.09.25.04.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 04:06:29 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 15/15] dt-bindings: pinctrl: qcom,sc7280: correct number of GPIOs Date: Sun, 25 Sep 2022 13:06:08 +0200 Message-Id: <20220925110608.145728-16-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> References: <20220925110608.145728-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SC7280 has 175 GPIOs (gpio0-174), so correct size of gpio-line-names and narrow the pattern for matching pin names. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 1db05c43d58c..2a6b5a719d18 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -43,7 +43,7 @@ properties: maxItems: 1 =20 gpio-line-names: - maxItems: 174 + maxItems: 175 =20 wakeup-parent: true =20 @@ -70,7 +70,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] minItems: 1 @@ -132,7 +132,7 @@ $defs: - if: properties: pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" then: required: - function --=20 2.34.1