From nobody Thu Apr 2 15:19:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88501C32771 for ; Sat, 24 Sep 2022 09:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233497AbiIXJYc (ORCPT ); Sat, 24 Sep 2022 05:24:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233484AbiIXJYX (ORCPT ); Sat, 24 Sep 2022 05:24:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8854D13943C; Sat, 24 Sep 2022 02:24:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 24BFD60DED; Sat, 24 Sep 2022 09:24:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55F4EC433D7; Sat, 24 Sep 2022 09:24:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664011461; bh=0Fp5N+iuPZzD55S6xZwszO0M3jKrv7PY7Rm1eU+7P/k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SbM0PyTK/gMt2I+LcMA2scxDkGfXA2p1sqxnfd+fvtl4n6LErlBWm9qYvjh75kAUg jaL574qzcen/zHqZrC8pOlRltL/0mhRKSRNIgjRMGlEVx6xAT/IsKthij5P/515W+k ySlLDPVvU4Eg5ZnGLGzcJQoxiRk4GZkXT8xRpI0iYOadAY/lX3BlDrqPTja/yJqoJd m1JM9tB4vwan4EQ9PJVzNy6ob0RJQgT2E/7dNHmpVI5bWRoXE1ZcvZu046iAoObx8/ 9NbBCYmmkbzWCZxv22dqYG9r4LkNUx4nzWSyL/t030ehuH/dIFaIMisvRiHLsC6Sot MhltOqndg/U+A== Received: by pali.im (Postfix) id CDB93127C; Sat, 24 Sep 2022 11:24:18 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Sergio Paracuellos , Matthias Brugger Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/3] PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macro Date: Sat, 24 Sep 2022 11:24:04 +0200 Message-Id: <20220924092404.31776-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220924092404.31776-1-pali@kernel.org> References: <20220924092404.31776-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCIe config space. Signed-off-by: Pali Roh=C3=A1r Acked-by: Sergio Paracuellos --- drivers/pci/controller/pcie-mt7621.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/= pcie-mt7621.c index 33eb37a2225c..4bd1abf26008 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -30,6 +30,8 @@ #include #include =20 +#include "../pci.h" + /* MediaTek-specific configuration registers */ #define PCIE_FTS_NUM 0x70c #define PCIE_FTS_NUM_MASK GENMASK(15, 8) @@ -120,19 +122,12 @@ static inline void pcie_port_write(struct mt7621_pcie= _port *port, writel_relaxed(val, port->base + reg); } =20 -static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int s= lot, - unsigned int func, unsigned int where) -{ - return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | - (func << 8) | (where & 0xfc) | 0x80000000; -} - static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct mt7621_pcie *pcie =3D bus->sysdata; - u32 address =3D mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + u32 address =3D PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); =20 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); =20 @@ -147,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops =3D { =20 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - u32 address =3D mt7621_pcie_get_cfgaddr(0, dev, 0, reg); + u32 address =3D PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); @@ -156,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsign= ed int dev, u32 reg) static void write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u32 address =3D mt7621_pcie_get_cfgaddr(0, dev, 0, reg); + u32 address =3D PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); --=20 2.20.1