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[84.102.31.32]) by smtp.gmail.com with ESMTPSA id m18-20020a5d56d2000000b0022878c0cc5esm7444627wrw.69.2022.09.23.07.24.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 07:24:39 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com Subject: [PATCH v9 1/4] dt-bindings: counter: add ti,am62-ecap-capture.yaml Date: Fri, 23 Sep 2022 16:24:34 +0200 Message-Id: <20220923142437.271328-2-jpanis@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220923142437.271328-1-jpanis@baylibre.com> References: <20220923142437.271328-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds a YAML binding for TI ECAP used in capture operating mode. Signed-off-by: Julien Panis Reviewed-by: Krzysztof Kozlowski --- .../counter/ti,am62-ecap-capture.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/ti,am62-ecap-= capture.yaml diff --git a/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture= .yaml b/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture.yaml new file mode 100644 index 000000000000..4e0b2d2b303e --- /dev/null +++ b/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/ti,am62-ecap-capture.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Enhanced Capture (eCAP) Module + +maintainers: + - Julien Panis + +description: | + The eCAP module resources can be used to capture timestamps + on input signal events (falling/rising edges). + +properties: + compatible: + const: ti,am62-ecap-capture + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + capture@23100000 { /* eCAP in capture mode on am62x */ + compatible =3D "ti,am62-ecap-capture"; + reg =3D <0x00 0x23100000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 51 0>; + clock-names =3D "fck"; + }; + }; --=20 2.37.3 From nobody Thu Apr 25 10:05:40 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A677CECAAD8 for ; Fri, 23 Sep 2022 14:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232582AbiIWOZD (ORCPT ); Fri, 23 Sep 2022 10:25:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232524AbiIWOYp (ORCPT ); Fri, 23 Sep 2022 10:24:45 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC5292737 for ; Fri, 23 Sep 2022 07:24:42 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id n12so227160wrx.9 for ; Fri, 23 Sep 2022 07:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aZ9inPx/SpVp/+EGUIHCzXQtKEo6kGOnnJXHLc8UgwM=; b=YOGaryDSh5eMCTjfMznfvWNctOo5bnmgrfLp0T2b1FoSvPwCOLhO2KXAHALUJS7chj aoVIBT9sRSrjuc1YwAFtMTW0KVXmGhBwTA9el7BG/DRkEjRyOYyQ6bXGtrVnPqUEsM3Y N1vkorsv0dXIlGOgM5xWHRP3MZprdLjutkwD+aOeoyEeoWQ6W1eXZx3oA7wSehh4FXjT 3IuUEklaMR0ETL8tQfMsc7zCVgJU0RT26bzjYz7aNE+ftTnJYcw2u6Ritend42vFXJd8 j0mOH0ASvCv22tkAuNwANjgmC3gFjhkT86Atps/yR8/6bPJXDTqnOYA9QE8cz1ydGgxw JaVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aZ9inPx/SpVp/+EGUIHCzXQtKEo6kGOnnJXHLc8UgwM=; b=3un0ODRB3smmV5zErjblOYao8v6u2dasVcYIm8U725SV6vw/W1HtxEtKco4IzJet8T WrAUfQsIlGBKRpEcc11AaQpGZRQ8Z4VKFxFmfbhbsn3cRgh04XXc0nsKqjKY7f/fQiz+ YBFcA096Ojx31g9MF0i+pttMIPJS/z0klpud+jaTEf+AXfEz5yhfvMOwSyCKTk1dYj53 c6la99923HwDWt+rcNVglwj1S9w1WdgkzUea1HXqo3T9nBd4I3Wh2TqHCR231i/X5IB1 Yw5w1F6fKyrL50CR9BvV3ep6PNz25yoR1va3xs0wBlLoY7iMWaTgvNfa4sV/fSV34NA/ 4zBw== X-Gm-Message-State: ACrzQf3X5J4aZkafGo4Kt6zP7pzgmxEiW5rXZVHMmjJUDz+RMpn8X7QY rGuVgb0J8wAqPoJ+r2lo16MRTQ== X-Google-Smtp-Source: AMsMyM5KSaCRz7TDVdc4PWQq1dCm9KKmVZbEN5+BoruRlucGDHgFFuxf5Os6GiLXj8b+FzECSYiogw== X-Received: by 2002:a5d:55c1:0:b0:228:6b57:c60b with SMTP id i1-20020a5d55c1000000b002286b57c60bmr5254820wrw.68.1663943080797; Fri, 23 Sep 2022 07:24:40 -0700 (PDT) Received: from baylibre-ThinkPad-T14s-Gen-2i.. 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[84.102.31.32]) by smtp.gmail.com with ESMTPSA id m18-20020a5d56d2000000b0022878c0cc5esm7444627wrw.69.2022.09.23.07.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 07:24:40 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com Subject: [PATCH v9 2/4] Documentation: ABI: sysfs-bus-counter: add frequency & num_overflows items Date: Fri, 23 Sep 2022 16:24:35 +0200 Message-Id: <20220923142437.271328-3-jpanis@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220923142437.271328-1-jpanis@baylibre.com> References: <20220923142437.271328-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds frequency and num_overflows items to counter ABI file (e.g. for TI ECAP hardware used in capture operating mode). Signed-off-by: Julien Panis --- Documentation/ABI/testing/sysfs-bus-counter | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-counter b/Documentation/AB= I/testing/sysfs-bus-counter index 30b6e1faa6f6..e177c6128236 100644 --- a/Documentation/ABI/testing/sysfs-bus-counter +++ b/Documentation/ABI/testing/sysfs-bus-counter @@ -209,6 +209,12 @@ Description: both edges: Any state transition. =20 +What: /sys/bus/counter/devices/counterX/countY/num_overflows +KernelVersion: 6.1 +Contact: linux-iio@vger.kernel.org +Description: + This attribute indicates the number of overflows of count Y. + What: /sys/bus/counter/devices/counterX/countY/ceiling_component_id What: /sys/bus/counter/devices/counterX/countY/floor_component_id What: /sys/bus/counter/devices/counterX/countY/count_mode_component_id @@ -219,11 +225,13 @@ What: /sys/bus/counter/devices/counterX/countY/presc= aler_component_id What: /sys/bus/counter/devices/counterX/countY/preset_component_id What: /sys/bus/counter/devices/counterX/countY/preset_enable_component_id What: /sys/bus/counter/devices/counterX/countY/signalZ_action_component_id +What: /sys/bus/counter/devices/counterX/countY/num_overflows_component_id What: /sys/bus/counter/devices/counterX/signalY/cable_fault_component_id What: /sys/bus/counter/devices/counterX/signalY/cable_fault_enable_compon= ent_id What: /sys/bus/counter/devices/counterX/signalY/filter_clock_prescaler_co= mponent_id What: /sys/bus/counter/devices/counterX/signalY/index_polarity_component_= id What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_componen= t_id +What: /sys/bus/counter/devices/counterX/signalY/frequency_component_id KernelVersion: 5.16 Contact: linux-iio@vger.kernel.org Description: @@ -364,3 +372,9 @@ Description: via index_polarity. The index function (as enabled via preset_enable) is performed synchronously with the quadrature clock on the active level of the index input. + +What: /sys/bus/counter/devices/counterX/signalY/frequency +KernelVersion: 6.1 +Contact: linux-iio@vger.kernel.org +Description: + Read-only attribute that indicates the signal Y frequency, in Hz. --=20 2.37.3 From nobody Thu Apr 25 10:05:40 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0CE1C6FA82 for ; Fri, 23 Sep 2022 14:25:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230229AbiIWOZH (ORCPT ); Fri, 23 Sep 2022 10:25:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232560AbiIWOYr (ORCPT ); Fri, 23 Sep 2022 10:24:47 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09E1629826 for ; Fri, 23 Sep 2022 07:24:43 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id fn7-20020a05600c688700b003b4fb113b86so153318wmb.0 for ; Fri, 23 Sep 2022 07:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PheMdTYDZ6j1xMYSvIegC67vhmDyo3GkK5ooUT3Ma+c=; b=cCVX9NPnI3fOIo5skC0Fca22YilTpgT/pgwIyzbTYX35KlwQr6W4aFGiMLZCCz6GBZ ORKPVMeuY2BwPyueb0NhH4fAzzf8vzvx3QbxcXKnfKBXBvcqs4KSxBvBPOchnoOygEBp iK9HmmbiG1c3K2qWeGTdRu5Q6d1CbN0mA8X8JkYaVAJyVNevi0E//3+GF9ompVoV9wYN cwXky+iuXdszW5P81Ne83XvISwYQBEMVU9DmzQbZ661ZT/PmR5NdFgbieBI73BHLMs4Q AOjJmQXfYj4hshJuOKcWtRYy8T2Ybywhj7bjzuZTd7N1ZDmjPU6WtHpm9cnuFK+sB/lN MtuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PheMdTYDZ6j1xMYSvIegC67vhmDyo3GkK5ooUT3Ma+c=; b=c+Cy/Phg3UFknqmB1pOi9YnXnyhPfFw04pxp505lR0CIlyofVwG3Jdq19gO54cKVCF GcxN0UTcLbA2az7MagOSyW4H6nYM964PLrZ5PhFA1kAwVUJL74AlgXQLK/j1kx/rVfGB ByqwRyrF9TRJjXohqDHdiNEIf9aVlS/HoHXHSTPTmIrj41CMdg1QpxWItALxeSJOtbw9 wsVkEQukVO42mZuHjuIwWwrObRtcgZZwbQxL/mzZmlRYJSsgZYb36ztjmQTchy8LUstV FzMV6DPtVBGYRRN+R1JGcpDGtmjQlGLGXWLVqp1YlPd8lqTm5IsaN8cVtggiPXHxfYpS roog== X-Gm-Message-State: ACrzQf3g9yqS8yjE6gFWfG050sVFIJUEWqiSejoR0wI59YRcXZzN4GEx 5IDC+R2TI2kIjBpBmzF1DgeloQ== X-Google-Smtp-Source: AMsMyM4EyS8gyJCjxMrN/MaZ1u7C1JjZfNBvljEkrSxwDC06+HT9u4P7yprSOCe6G9tMuDeqlRJ9BA== X-Received: by 2002:a05:600c:34c6:b0:3b4:9643:e46d with SMTP id d6-20020a05600c34c600b003b49643e46dmr6321534wmq.9.1663943082252; Fri, 23 Sep 2022 07:24:42 -0700 (PDT) Received: from baylibre-ThinkPad-T14s-Gen-2i.. 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[84.102.31.32]) by smtp.gmail.com with ESMTPSA id m18-20020a5d56d2000000b0022878c0cc5esm7444627wrw.69.2022.09.23.07.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 07:24:41 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com Subject: [PATCH v9 3/4] counter: ti-ecap-capture: capture driver support for ECAP Date: Fri, 23 Sep 2022 16:24:36 +0200 Message-Id: <20220923142437.271328-4-jpanis@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220923142437.271328-1-jpanis@baylibre.com> References: <20220923142437.271328-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ECAP hardware on TI AM62x SoC supports capture feature. It can be used to timestamp events (falling/rising edges) detected on input signal. This commit adds capture driver support for ECAP hardware on AM62x SoC. In the ECAP hardware, capture pin can also be configured to be in PWM mode. Current implementation only supports capture operating mode. Hardware also supports timebase sync between multiple instances, but this driver supports simple independent capture functionality. Signed-off-by: Julien Panis --- drivers/counter/Kconfig | 15 + drivers/counter/Makefile | 1 + drivers/counter/ti-ecap-capture.c | 614 ++++++++++++++++++++++++++++++ 3 files changed, 630 insertions(+) create mode 100644 drivers/counter/ti-ecap-capture.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 5edd155f1911..d388bf26f4dc 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -101,4 +101,19 @@ config INTEL_QEP To compile this driver as a module, choose M here: the module will be called intel-qep. =20 +config TI_ECAP_CAPTURE + tristate "TI eCAP capture driver" + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_KEYSTONE || ARCH_= K3 || COMPILE_TEST + depends on HAS_IOMEM + select REGMAP_MMIO + help + Select this option to enable the Texas Instruments Enhanced Capture + (eCAP) driver in input mode. + + It can be used to timestamp events (falling/rising edges) detected + on ECAP input signal. + + To compile this driver as a module, choose M here: the module + will be called ti-ecap-capture. + endif # COUNTER diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index 8fde6c100ebc..b9a369e0d4fc 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o +obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o diff --git a/drivers/counter/ti-ecap-capture.c b/drivers/counter/ti-ecap-ca= pture.c new file mode 100644 index 000000000000..af10de30aba5 --- /dev/null +++ b/drivers/counter/ti-ecap-capture.c @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ECAP Capture driver + * + * Copyright (C) 2022 Julien Panis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ECAP_DRV_NAME "ecap" + +/* ECAP event IDs */ +#define ECAP_CEVT1 0 +#define ECAP_CEVT2 1 +#define ECAP_CEVT3 2 +#define ECAP_CEVT4 3 +#define ECAP_CNTOVF 4 + +#define ECAP_CEVT_LAST ECAP_CEVT4 +#define ECAP_NB_CEVT (ECAP_CEVT_LAST + 1) + +#define ECAP_EVT_LAST ECAP_CNTOVF +#define ECAP_NB_EVT (ECAP_EVT_LAST + 1) + +/* Registers */ +#define ECAP_TSCNT_REG 0x00 + +#define ECAP_CAP_REG(i) (((i) << 2) + 0x08) + +#define ECAP_ECCTL_REG 0x28 +#define ECAP_CAPPOL_BIT(i) BIT((i) << 1) +#define ECAP_EV_MODE_MASK GENMASK(7, 0) +#define ECAP_CAPLDEN_BIT BIT(8) +#define ECAP_CONT_ONESHT_BIT BIT(16) +#define ECAP_STOPVALUE_MASK GENMASK(18, 17) +#define ECAP_TSCNTSTP_BIT BIT(20) +#define ECAP_SYNCO_DIS_MASK GENMASK(23, 22) +#define ECAP_CAP_APWM_BIT BIT(25) +#define ECAP_ECCTL_EN_MASK (ECAP_CAPLDEN_BIT | ECAP_TSCNTSTP_BIT) +#define ECAP_ECCTL_CFG_MASK (ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK \ + | ECAP_ECCTL_EN_MASK | ECAP_CAP_APWM_BIT \ + | ECAP_CONT_ONESHT_BIT) + +#define ECAP_ECINT_EN_FLG_REG 0x2c +#define ECAP_EVT_EN_MASK GENMASK(ECAP_NB_EVT, ECAP_NB_CEVT) +#define ECAP_EVT_FLG_BIT(i) BIT((i) + 17) + +#define ECAP_ECINT_CLR_FRC_REG 0x30 +#define ECAP_INT_CLR_BIT BIT(0) +#define ECAP_EVT_CLR_BIT(i) BIT((i) + 1) +#define ECAP_EVT_CLR_MASK GENMASK(ECAP_NB_EVT, 0) + +#define ECAP_PID_REG 0x5c + +/* ECAP signals */ +#define ECAP_CLOCK_SIG 0 +#define ECAP_INPUT_SIG 1 + +static const struct regmap_config ecap_cnt_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D ECAP_PID_REG, +}; + +/** + * struct ecap_cnt_dev - device private data structure + * @enabled: device state + * @lock: synchronization lock to prevent I/O race conditions + * @clk: device clock + * @regmap: device register map + * @nb_ovf: number of overflows since capture start + * @pm_ctx: device context for PM operations + * @pm_ctx.ev_mode: event mode bits + * @pm_ctx.time_cntr: timestamp counter value + */ +struct ecap_cnt_dev { + bool enabled; + struct mutex lock; + struct clk *clk; + struct regmap *regmap; + atomic_t nb_ovf; + struct { + u8 ev_mode; + u32 time_cntr; + } pm_ctx; +}; + +static u8 ecap_cnt_capture_get_evmode(struct counter_device *counter) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + unsigned int regval; + + pm_runtime_get_sync(counter->parent); + regmap_read(ecap_dev->regmap, ECAP_ECCTL_REG, ®val); + pm_runtime_put_sync(counter->parent); + + return regval; +} + +static void ecap_cnt_capture_set_evmode(struct counter_device *counter, u8= ev_mode) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + pm_runtime_get_sync(counter->parent); + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_EV_MODE_MASK, e= v_mode); + pm_runtime_put_sync(counter->parent); +} + +static void ecap_cnt_capture_enable(struct counter_device *counter) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + pm_runtime_get_sync(counter->parent); + + /* Enable interrupts on events */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, + ECAP_EVT_EN_MASK, ECAP_EVT_EN_MASK); + + /* Run counter */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_CFG_MASK, + ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK | ECAP_ECCTL_EN_MASK); +} + +static void ecap_cnt_capture_disable(struct counter_device *counter) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + /* Stop counter */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_EN_MASK, = 0); + + /* Disable interrupts on events */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, ECAP_EVT_EN_M= ASK, 0); + + pm_runtime_put_sync(counter->parent); +} + +static u32 ecap_cnt_count_get_val(struct counter_device *counter, unsigned= int reg) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + unsigned int regval; + + pm_runtime_get_sync(counter->parent); + regmap_read(ecap_dev->regmap, reg, ®val); + pm_runtime_put_sync(counter->parent); + + return regval; +} + +static void ecap_cnt_count_set_val(struct counter_device *counter, unsigne= d int reg, u32 val) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + pm_runtime_get_sync(counter->parent); + regmap_write(ecap_dev->regmap, reg, val); + pm_runtime_put_sync(counter->parent); +} + +static int ecap_cnt_count_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + *val =3D ecap_cnt_count_get_val(counter, ECAP_TSCNT_REG); + + return 0; +} + +static int ecap_cnt_count_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + if (val > U32_MAX) + return -ERANGE; + + ecap_cnt_count_set_val(counter, ECAP_TSCNT_REG, val); + + return 0; +} + +static int ecap_cnt_function_read(struct counter_device *counter, + struct counter_count *count, + enum counter_function *function) +{ + *function =3D COUNTER_FUNCTION_INCREASE; + + return 0; +} + +static int ecap_cnt_action_read(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + enum counter_synapse_action *action) +{ + *action =3D (synapse->signal->id =3D=3D ECAP_CLOCK_SIG) ? + COUNTER_SYNAPSE_ACTION_RISING_EDGE : + COUNTER_SYNAPSE_ACTION_NONE; + + return 0; +} + +static int ecap_cnt_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + if (watch->channel > ECAP_CEVT_LAST) + return -EINVAL; + + switch (watch->event) { + case COUNTER_EVENT_CAPTURE: + case COUNTER_EVENT_OVERFLOW: + return 0; + default: + return -EINVAL; + } +} + +static int ecap_cnt_clk_get_freq(struct counter_device *counter, + struct counter_signal *signal, u64 *freq) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *freq =3D clk_get_rate(ecap_dev->clk); + + return 0; +} + +static int ecap_cnt_pol_read(struct counter_device *counter, + struct counter_signal *signal, + size_t idx, enum counter_signal_polarity *pol) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + int bitval; + + pm_runtime_get_sync(counter->parent); + bitval =3D regmap_test_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL= _BIT(idx)); + pm_runtime_put_sync(counter->parent); + + *pol =3D bitval ? COUNTER_SIGNAL_POLARITY_NEGATIVE : COUNTER_SIGNAL_POLAR= ITY_POSITIVE; + + return 0; +} + +static int ecap_cnt_pol_write(struct counter_device *counter, + struct counter_signal *signal, + size_t idx, enum counter_signal_polarity pol) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + pm_runtime_get_sync(counter->parent); + if (pol =3D=3D COUNTER_SIGNAL_POLARITY_NEGATIVE) + regmap_set_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); + else + regmap_clear_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)= ); + pm_runtime_put_sync(counter->parent); + + return 0; +} + +static int ecap_cnt_cap_read(struct counter_device *counter, + struct counter_count *count, + size_t idx, u64 *cap) +{ + *cap =3D ecap_cnt_count_get_val(counter, ECAP_CAP_REG(idx)); + + return 0; +} + +static int ecap_cnt_cap_write(struct counter_device *counter, + struct counter_count *count, + size_t idx, u64 cap) +{ + if (cap > U32_MAX) + return -ERANGE; + + ecap_cnt_count_set_val(counter, ECAP_CAP_REG(idx), cap); + + return 0; +} + +static int ecap_cnt_nb_ovf_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *val =3D atomic_read(&ecap_dev->nb_ovf); + + return 0; +} + +static int ecap_cnt_nb_ovf_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + if (val > U32_MAX) + return -ERANGE; + + atomic_set(&ecap_dev->nb_ovf, val); + + return 0; +} + +static int ecap_cnt_ceiling_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + *val =3D U32_MAX; + + return 0; +} + +static int ecap_cnt_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *enable) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *enable =3D ecap_dev->enabled; + + return 0; +} + +static int ecap_cnt_enable_write(struct counter_device *counter, + struct counter_count *count, u8 enable) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + mutex_lock(&ecap_dev->lock); + + if (enable =3D=3D ecap_dev->enabled) + goto out; + + if (enable) + ecap_cnt_capture_enable(counter); + else + ecap_cnt_capture_disable(counter); + ecap_dev->enabled =3D enable; + +out: + mutex_unlock(&ecap_dev->lock); + + return 0; +} + +static const struct counter_ops ecap_cnt_ops =3D { + .count_read =3D ecap_cnt_count_read, + .count_write =3D ecap_cnt_count_write, + .function_read =3D ecap_cnt_function_read, + .action_read =3D ecap_cnt_action_read, + .watch_validate =3D ecap_cnt_watch_validate, +}; + +static const enum counter_function ecap_cnt_functions[] =3D { + COUNTER_FUNCTION_INCREASE, +}; + +static const enum counter_synapse_action ecap_cnt_clock_actions[] =3D { + COUNTER_SYNAPSE_ACTION_RISING_EDGE, +}; + +static const enum counter_synapse_action ecap_cnt_input_actions[] =3D { + COUNTER_SYNAPSE_ACTION_NONE, +}; + +static struct counter_comp ecap_cnt_clock_ext[] =3D { + COUNTER_COMP_SIGNAL_U64("frequency", ecap_cnt_clk_get_freq, NULL), +}; + +static const enum counter_signal_polarity ecap_cnt_pol_avail[] =3D { + COUNTER_SIGNAL_POLARITY_POSITIVE, + COUNTER_SIGNAL_POLARITY_NEGATIVE, +}; + +static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_avai= l, ECAP_NB_CEVT); + +static struct counter_comp ecap_cnt_signal_ext[] =3D { + COUNTER_COMP_ARRAY_POLARITY(ecap_cnt_pol_read, ecap_cnt_pol_write, ecap_c= nt_pol_array), +}; + +static struct counter_signal ecap_cnt_signals[] =3D { + { + .id =3D ECAP_CLOCK_SIG, + .name =3D "Clock Signal", + .ext =3D ecap_cnt_clock_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_clock_ext), + }, + { + .id =3D ECAP_INPUT_SIG, + .name =3D "Input Signal", + .ext =3D ecap_cnt_signal_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_signal_ext), + }, +}; + +static struct counter_synapse ecap_cnt_synapses[] =3D { + { + .actions_list =3D ecap_cnt_clock_actions, + .num_actions =3D ARRAY_SIZE(ecap_cnt_clock_actions), + .signal =3D &ecap_cnt_signals[ECAP_CLOCK_SIG], + }, + { + .actions_list =3D ecap_cnt_input_actions, + .num_actions =3D ARRAY_SIZE(ecap_cnt_input_actions), + .signal =3D &ecap_cnt_signals[ECAP_INPUT_SIG], + }, +}; + +static DEFINE_COUNTER_ARRAY_CAPTURE(ecap_cnt_cap_array, ECAP_NB_CEVT); + +static struct counter_comp ecap_cnt_count_ext[] =3D { + COUNTER_COMP_ARRAY_CAPTURE(ecap_cnt_cap_read, ecap_cnt_cap_write, ecap_cn= t_cap_array), + COUNTER_COMP_COUNT_U64("num_overflows", ecap_cnt_nb_ovf_read, ecap_cnt_nb= _ovf_write), + COUNTER_COMP_CEILING(ecap_cnt_ceiling_read, NULL), + COUNTER_COMP_ENABLE(ecap_cnt_enable_read, ecap_cnt_enable_write), +}; + +static struct counter_count ecap_cnt_counts[] =3D { + { + .name =3D "Timestamp Counter", + .functions_list =3D ecap_cnt_functions, + .num_functions =3D ARRAY_SIZE(ecap_cnt_functions), + .synapses =3D ecap_cnt_synapses, + .num_synapses =3D ARRAY_SIZE(ecap_cnt_synapses), + .ext =3D ecap_cnt_count_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_count_ext), + }, +}; + +static irqreturn_t ecap_cnt_isr(int irq, void *dev_id) +{ + struct counter_device *counter_dev =3D dev_id; + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + unsigned int clr =3D 0; + unsigned int flg; + int i; + + regmap_read(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, &flg); + + /* Check capture events */ + for (i =3D 0 ; i < ECAP_NB_CEVT ; i++) { + if (flg & ECAP_EVT_FLG_BIT(i)) { + counter_push_event(counter_dev, COUNTER_EVENT_CAPTURE, i); + clr |=3D ECAP_EVT_CLR_BIT(i); + } + } + + /* Check counter overflow */ + if (flg & ECAP_EVT_FLG_BIT(ECAP_CNTOVF)) { + atomic_inc(&ecap_dev->nb_ovf); + for (i =3D 0 ; i < ECAP_NB_CEVT ; i++) + counter_push_event(counter_dev, COUNTER_EVENT_OVERFLOW, i); + clr |=3D ECAP_EVT_CLR_BIT(ECAP_CNTOVF); + } + + clr |=3D ECAP_INT_CLR_BIT; + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_CLR_FRC_REG, ECAP_EVT_CLR= _MASK, clr); + + return IRQ_HANDLED; +} + +static void ecap_cnt_pm_disable(void *dev) +{ + pm_runtime_disable(dev); +} + +static int ecap_cnt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ecap_cnt_dev *ecap_dev; + struct counter_device *counter_dev; + void __iomem *mmio_base; + unsigned long clk_rate; + int ret; + + counter_dev =3D devm_counter_alloc(dev, sizeof(*ecap_dev)); + if (IS_ERR(counter_dev)) + return PTR_ERR(counter_dev); + + counter_dev->name =3D ECAP_DRV_NAME; + counter_dev->parent =3D dev; + counter_dev->ops =3D &ecap_cnt_ops; + counter_dev->signals =3D ecap_cnt_signals; + counter_dev->num_signals =3D ARRAY_SIZE(ecap_cnt_signals); + counter_dev->counts =3D ecap_cnt_counts; + counter_dev->num_counts =3D ARRAY_SIZE(ecap_cnt_counts); + + ecap_dev =3D counter_priv(counter_dev); + + mutex_init(&ecap_dev->lock); + + ecap_dev->clk =3D devm_clk_get_enabled(dev, "fck"); + if (IS_ERR(ecap_dev->clk)) + return dev_err_probe(dev, PTR_ERR(ecap_dev->clk), "failed to get clock\n= "); + + clk_rate =3D clk_get_rate(ecap_dev->clk); + if (!clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + return -EINVAL; + } + + mmio_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmio_base)) + return PTR_ERR(mmio_base); + + ecap_dev->regmap =3D devm_regmap_init_mmio(dev, mmio_base, &ecap_cnt_regm= ap_config); + if (IS_ERR(ecap_dev->regmap)) + return dev_err_probe(dev, PTR_ERR(ecap_dev->regmap), "failed to init reg= map\n"); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get irq\n"); + + ret =3D devm_request_irq(dev, ret, ecap_cnt_isr, 0, pdev->name, counter_d= ev); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + platform_set_drvdata(pdev, counter_dev); + + pm_runtime_enable(dev); + + /* Register a cleanup callback to care for disabling PM */ + ret =3D devm_add_action_or_reset(dev, ecap_cnt_pm_disable, dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add pm disable action\n"); + + ret =3D devm_counter_add(dev, counter_dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add counter\n"); + + return 0; +} + +static int ecap_cnt_remove(struct platform_device *pdev) +{ + struct counter_device *counter_dev =3D platform_get_drvdata(pdev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + if (ecap_dev->enabled) + ecap_cnt_capture_disable(counter_dev); + + return 0; +} + +static int ecap_cnt_suspend(struct device *dev) +{ + struct counter_device *counter_dev =3D dev_get_drvdata(dev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + /* If eCAP is running, stop capture then save timestamp counter */ + if (ecap_dev->enabled) { + /* + * Disabling capture has the following effects: + * - interrupts are disabled + * - loading of capture registers is disabled + * - timebase counter is stopped + */ + ecap_cnt_capture_disable(counter_dev); + ecap_dev->pm_ctx.time_cntr =3D ecap_cnt_count_get_val(counter_dev, ECAP_= TSCNT_REG); + } + + ecap_dev->pm_ctx.ev_mode =3D ecap_cnt_capture_get_evmode(counter_dev); + + clk_disable(ecap_dev->clk); + + return 0; +} + +static int ecap_cnt_resume(struct device *dev) +{ + struct counter_device *counter_dev =3D dev_get_drvdata(dev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + clk_enable(ecap_dev->clk); + + ecap_cnt_capture_set_evmode(counter_dev, ecap_dev->pm_ctx.ev_mode); + + /* If eCAP was running, restore timestamp counter then run capture */ + if (ecap_dev->enabled) { + ecap_cnt_count_set_val(counter_dev, ECAP_TSCNT_REG, ecap_dev->pm_ctx.tim= e_cntr); + ecap_cnt_capture_enable(counter_dev); + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ecap_cnt_pm_ops, ecap_cnt_suspend, ecap_cn= t_resume); + +static const struct of_device_id ecap_cnt_of_match[] =3D { + { .compatible =3D "ti,am62-ecap-capture" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ecap_cnt_of_match); + +static struct platform_driver ecap_cnt_driver =3D { + .probe =3D ecap_cnt_probe, + .remove =3D ecap_cnt_remove, + .driver =3D { + .name =3D "ecap-capture", + .of_match_table =3D ecap_cnt_of_match, + .pm =3D pm_sleep_ptr(&ecap_cnt_pm_ops), + }, +}; +module_platform_driver(ecap_cnt_driver); + +MODULE_DESCRIPTION("ECAP Capture driver"); +MODULE_AUTHOR("Julien Panis "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(COUNTER); --=20 2.37.3 From nobody Thu Apr 25 10:05:40 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80C9DC6FA82 for ; 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[84.102.31.32]) by smtp.gmail.com with ESMTPSA id m18-20020a5d56d2000000b0022878c0cc5esm7444627wrw.69.2022.09.23.07.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 07:24:43 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com Subject: [PATCH v9 4/4] MAINTAINERS: add TI ECAP driver info Date: Fri, 23 Sep 2022 16:24:37 +0200 Message-Id: <20220923142437.271328-5-jpanis@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220923142437.271328-1-jpanis@baylibre.com> References: <20220923142437.271328-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds driver info for TI ECAP used in capture operating mode. Signed-off-by: Julien Panis --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d4999f68bda8..c189117f58eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20322,6 +20322,15 @@ T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_de= vices.git F: drivers/media/platform/ti/davinci/ F: include/media/davinci/ =20 +TI ENHANCED CAPTURE (eCAP) DRIVER +M: Vignesh Raghavendra +R: Julien Panis +L: linux-iio@vger.kernel.org +L: linux-omap@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/counter/ti,am62-ecap-capture.yaml +F: drivers/counter/ti-ecap-capture.c + TI ENHANCED QUADRATURE ENCODER PULSE (eQEP) DRIVER R: David Lechner L: linux-iio@vger.kernel.org --=20 2.37.3