From nobody Fri Mar 29 05:32:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05182C6FA8B for ; Fri, 23 Sep 2022 13:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232402AbiIWNM2 (ORCPT ); Fri, 23 Sep 2022 09:12:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232158AbiIWNMB (ORCPT ); Fri, 23 Sep 2022 09:12:01 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE59F132FE5; Fri, 23 Sep 2022 06:11:56 -0700 (PDT) X-UUID: 714e484a810d45f4b1798e302b1884b9-20220923 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cSfNvRkXsaTSJIsFm9G+GczbyEq3LGT/ioLJVJiL7vc=; b=LmXn0AeKubIHA2B6PveiYdtW2cPvBYzPxEDaIKWSn7f04/nNMjAqNvSbINdRd8JE/Jf9ySG/Brg/KNL9RXiRx9MQc9bPJ0PSX5ViCb4+lxNoHPzw1oa377hx6oefqbpkXF+RGUhUrSLWJVZRr81IVzzLbU5cy6Sr/l7eeKnXSak=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:6aaa0222-613f-41c3-8e00-4480ed828cfd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:6aaa0222-613f-41c3-8e00-4480ed828cfd,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:c784d006-1cee-4c38-b21b-a45f9682fdc0,B ulkID:220923211152A1MBW38C,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 714e484a810d45f4b1798e302b1884b9-20220923 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1732623273; Fri, 23 Sep 2022 21:11:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Sep 2022 21:11:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 21:11:50 +0800 From: Allen-KH Cheng To: Lee Jones , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH 1/5] dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186 Date: Fri, 23 Sep 2022 21:11:44 +0800 Message-ID: <20220923131148.6678-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> References: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new scpsys compatible for mt8186 SoC. Signed-off-by: Allen-KH Cheng Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.y= aml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml index 3737207d8504..c8c4812fffe2 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8167-scpsys - mediatek,mt8173-scpsys - mediatek,mt8183-scpsys + - mediatek,mt8186-scpsys - mediatek,mt8192-scpsys - mediatek,mt8195-scpsys - const: syscon --=20 2.18.0 From nobody Fri Mar 29 05:32:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85DD6C6FA82 for ; Fri, 23 Sep 2022 13:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232432AbiIWNMc (ORCPT ); Fri, 23 Sep 2022 09:12:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232295AbiIWNMD (ORCPT ); Fri, 23 Sep 2022 09:12:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8263B13EACF; Fri, 23 Sep 2022 06:12:01 -0700 (PDT) X-UUID: 59ca6e7af96744fa963862e7fc60655e-20220923 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=w7JAT1zpPu60OdL94EP7gUEL01Fz7GJdxBym3rpcNbI=; b=MWd9mtS1Er7AR5wFA0P6ZJCa3QVJZMi0pS5dKSafckD/ZejS/ikI+UCLZSJKODe4R0Otntc0oOUCWj5T8ZgBYD50pTdnpnbwW6ACJUjNufpiooMMbcwrYoq0KB6r6h/TaEpgtaiYFdfRtqG8h6e62hVednjCuZ2l/wpg9/jb2J0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:66428b21-e23e-4f10-8e16-47aeec8cc712,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:ba23dea2-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 59ca6e7af96744fa963862e7fc60655e-20220923 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1214217162; Fri, 23 Sep 2022 21:11:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Sep 2022 21:11:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 21:11:51 +0800 From: Allen-KH Cheng To: Lee Jones , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH 2/5] arm64: dts: mt8186: Add power domains controller Date: Fri, 23 Sep 2022 21:11:45 +0800 Message-ID: <20220923131148.6678-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> References: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power domains controller for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ 1 file changed, 188 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 64693c17af9e..833e7037fe22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -329,6 +329,194 @@ #interrupt-cells =3D <2>; }; =20 + scpsys: syscon@10006000 { + compatible =3D "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8186-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MFG>; + clock-names =3D "mfg00"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG1 { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_MFG3 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names =3D "csirx_top0", "csirx_top1"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_ADSP_AO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + clock-names =3D "adsp_ao0", "adsp_ao1"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CONN_ON { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_DIS { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_DISP>, + <&topckgen CLK_TOP_MDP>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names =3D "dis0", "dis1", "dis-0", "dis-1", + "dis-2", "dis-3"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_VDEC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names =3D "vdec0", "vdec-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>, + <&topckgen CLK_TOP_SENINF2>, + <&topckgen CLK_TOP_SENINF3>, + <&topckgen CLK_TOP_CAMTM>, + <&camsys CLK_CAM2MM_GALS>; + clock-names =3D "cam0", "cam1", "cam2", "cam3", + "cam4", "cam5", "cam-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IMG { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IMG1>, + <&imgsys1 CLK_IMG1_GALS_IMG1>; + clock-names =3D "img0", "img-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8186_POWER_DOMAIN_IMG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IPE { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IPE>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS_IPE>; + clock-names =3D "ipe0", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_VENC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names =3D "venc0", "venc-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_WPE { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_WPE>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; + clock-names =3D "wpe0", "wpe-0", "wpe-1"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible =3D "mediatek,mt8186-wdt", "mediatek,mt6589-wdt"; --=20 2.18.0 From nobody Fri Mar 29 05:32:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D667FECAAD8 for ; Fri, 23 Sep 2022 13:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232317AbiIWNMh (ORCPT ); Fri, 23 Sep 2022 09:12:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232300AbiIWNME (ORCPT ); Fri, 23 Sep 2022 09:12:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82642139415; Fri, 23 Sep 2022 06:12:02 -0700 (PDT) X-UUID: 0041a2c008384d8789b2985abc5ef81b-20220923 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; 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Fri, 23 Sep 2022 21:11:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Sep 2022 21:11:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 21:11:52 +0800 From: Allen-KH Cheng To: Lee Jones , Matthias Brugger , "Rob Herring" , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH 3/5] arm64: dts: mt8186: Add IOMMU and SMI nodes Date: Fri, 23 Sep 2022 21:11:46 +0800 Message-ID: <20220923131148.6678-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> References: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add iommu and smi nodes for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 173 +++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 833e7037fe22..68f06bef88f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -944,24 +945,113 @@ #reset-cells =3D <1>; }; =20 + smi_common: smi@14002000 { + compatible =3D "mediatek,mt8186-smi-common"; + reg =3D <0 0x14002000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; + clock-names =3D "apb", "smi", "gals0", "gals1"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb0: smi@14003000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,larb-id =3D <0>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb1: smi@14004000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,larb-id =3D <1>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + iommu_mm: iommu@14016000 { + compatible =3D "mediatek,mt8186-iommu-mm"; + reg =3D <0 0x14016000 0 0x1000>; + mediatek,larbs =3D <&larb0 &larb1 &larb2 &larb4 + &larb7 &larb8 &larb9 &larb11 + &larb13 &larb14 &larb16 &larb17 + &larb19 &larb20>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_SMI_IOMMU>; + clock-names =3D "bclk"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + #iommu-cells =3D <1>; + }; + wpesys: clock-controller@14020000 { compatible =3D "mediatek,mt8186-wpesys"; reg =3D <0 0x14020000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb8: smi@14023000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x14023000 0 0x1000>; + mediatek,larb-id =3D <8>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_WPE>; + }; + imgsys1: clock-controller@15020000 { compatible =3D "mediatek,mt8186-imgsys1"; reg =3D <0 0x15020000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb9: smi@1502e000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1502e000 0 0x1000>; + mediatek,larb-id =3D <9>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys1 CLK_IMG1_GALS_IMG1>, + <&imgsys1 CLK_IMG1_LARB9_IMG1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_IMG>; + }; + imgsys2: clock-controller@15820000 { compatible =3D "mediatek,mt8186-imgsys2"; reg =3D <0 0x15820000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb11: smi@1582e000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1582e000 0 0x1000>; + mediatek,larb-id =3D <11>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys1 CLK_IMG1_LARB9_IMG1>, + <&imgsys2 CLK_IMG2_LARB9_IMG2>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_IMG2>; + }; + + larb4: smi@1602e000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1602e000 0 0x1000>; + mediatek,larb-id =3D <4>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + vdecsys: clock-controller@1602f000 { compatible =3D "mediatek,mt8186-vdecsys"; reg =3D <0 0x1602f000 0 0x1000>; @@ -974,12 +1064,65 @@ #clock-cells =3D <1>; }; =20 + larb7: smi@17010000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x17010000 0 0x1000>; + mediatek,larb-id =3D <7>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vencsys CLK_VENC_CKE1_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8186-camsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb13: smi@1a001000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1a001000 0 0x1000>; + mediatek,larb-id =3D <13>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb14: smi@1a002000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1a002000 0 0x1000>; + mediatek,larb-id =3D <14>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb16: smi@1a00f000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1a00f000 0 0x1000>; + mediatek,larb-id =3D <16>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_LARB14>, + <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: smi@1a010000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1a010000 0 0x1000>; + mediatek,larb-id =3D <17>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_LARB13>, + <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible =3D "mediatek,mt8186-camsys_rawa"; reg =3D <0 0x1a04f000 0 0x1000>; @@ -998,10 +1141,40 @@ #clock-cells =3D <1>; }; =20 + larb2: smi@1b002000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1b002000 0 0x1000>; + mediatek,larb-id =3D <2>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + ipesys: clock-controller@1c000000 { compatible =3D "mediatek,mt8186-ipesys"; reg =3D <0 0x1c000000 0 0x1000>; #clock-cells =3D <1>; }; + + larb20: smi@1c00f000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1c00f000 0 0x1000>; + mediatek,larb-id =3D <20>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_IPE>; + }; + + larb19: smi@1c10f000 { + compatible =3D "mediatek,mt8186-smi-larb"; + reg =3D <0 0x1c10f000 0 0x1000>; + mediatek,larb-id =3D <19>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_IPE>; + }; }; }; --=20 2.18.0 From nobody Fri Mar 29 05:32:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03FF9C6FA82 for ; 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Fri, 23 Sep 2022 21:11:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 21:11:52 +0800 From: Allen-KH Cheng To: Lee Jones , Matthias Brugger , "Rob Herring" , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH 4/5] arm64: dts: mt8186: Add dpi node Date: Fri, 23 Sep 2022 21:11:47 +0800 Message-ID: <20220923131148.6678-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> References: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dpi node for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 68f06bef88f3..c6809fdc7d15 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -976,6 +976,25 @@ power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 + dsi0: dsi@14013000 { + compatible =3D "mediatek,mt8186-dsi"; + reg =3D <0 0x14013000 0 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + resets =3D <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + iommu_mm: iommu@14016000 { compatible =3D "mediatek,mt8186-iommu-mm"; reg =3D <0 0x14016000 0 0x1000>; --=20 2.18.0 From nobody Fri Mar 29 05:32:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CFD5C6FA82 for ; Fri, 23 Sep 2022 13:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232357AbiIWNMl (ORCPT ); Fri, 23 Sep 2022 09:12:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232301AbiIWNME (ORCPT ); Fri, 23 Sep 2022 09:12:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2493252BB; Fri, 23 Sep 2022 06:12:00 -0700 (PDT) X-UUID: a9d9e826f4e24c4eb38ca8a305cc181e-20220923 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EAepj9xDcBT7+/oknT8+PQeRJWAYHEbCWQjHMWNe4Ek=; b=QNV7a1kvMWpCrE7N8pvgb7kDENIMR3cOLbAXMpSlMHLU9Jys71VXWVvWU0KGDX3jPnzHHGMTpqfTdS4R7rqL2ohnVWYrQp2haWq0ujUhLooBwxgLAF4b8ZuRcBcgaRuIE22lNuK32WyNWtWrWs4IfEjbLvSirEsdMAoj7yIwC9U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:022fc46d-f8fb-42c5-a9d1-a49881d1a095,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:b923dea2-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: a9d9e826f4e24c4eb38ca8a305cc181e-20220923 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1150637332; Fri, 23 Sep 2022 21:11:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Sep 2022 21:11:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 21:11:53 +0800 From: Allen-KH Cheng To: Lee Jones , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , Allen-KH Cheng Subject: [PATCH 5/5] arm64: dts: mt8186: Add xhci nodes Date: Fri, 23 Sep 2022 21:11:48 +0800 Message-ID: <20220923131148.6678-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> References: <20220923131148.6678-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add xhci nodes for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index c6809fdc7d15..b08af431e525 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -845,6 +845,26 @@ status =3D "disabled"; }; =20 + xhci0: usb@11200000 { + compatible =3D "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB>; + mediatek,syscon-wakeup =3D <&pericfg 0x420 2>; + wakeup-source; + status =3D "disabled"; + }; + mmc0: mmc@11230000 { compatible =3D "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -875,6 +895,27 @@ status =3D "disabled"; }; =20 + xhci1: usb@11280000 { + compatible =3D "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11280000 0 0x1000>, + <0 0x11283e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + mediatek,syscon-wakeup =3D <&pericfg 0x424 2>; + wakeup-source; + status =3D "disabled"; + }; + u3phy0: t-phy@11c80000 { compatible =3D "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; --=20 2.18.0