From nobody Sat Apr 20 09:52:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB730ECAAD8 for ; Fri, 23 Sep 2022 12:23:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232285AbiIWMXE (ORCPT ); Fri, 23 Sep 2022 08:23:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231627AbiIWMV7 (ORCPT ); Fri, 23 Sep 2022 08:21:59 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9668135057; Fri, 23 Sep 2022 05:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663935451; x=1695471451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JFvYHlPONCjo9mSx1lwPnzS8Isz+Ts+1dW0TWufMXSE=; b=GqNxJFKJ9lWhClXJeKDbqFoq+EfSpC0wCI+hkLcuHgeCYdJZgYNPbi3K qrn+4OOo61loXgF9hGHYB/qHHOr1TJBUkOQvcCyAIQ/hXj3c41XxvMgJa gp1B9NGltL2D1QaFib3bXj534xUQXzBb+7GLlbrGCmqYBnR3XpjOarPFy baevSHxm/RmKjlH/dMBuMG4lM3aYR0CJ121F7J0QQaZ9UboWrXY98+s2p BtKuK+HPMcEIJDn0REhUWLt0hlxhlQ9nMHBM7fsDg747EV4zi0X9+payk fsuFPQEb/osamDQtTk6nPJMz8JHnX8OtSPsQYlkkhZAlzZsLJAFO+Mf3y A==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="364595281" X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="364595281" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="762597740" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.139]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:31 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Basheer Ahmed Muddebihal , Matthew Gerlach Subject: [PATCH v2 3/6] fpga: dfl: Add DFHv1 Register Definitions Date: Fri, 23 Sep 2022 05:17:42 -0700 Message-Id: <20220923121745.129167-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Basheer Ahmed Muddebihal This patch adds the definitions for DFHv1 header and related register bitfields. Signed-off-by: Basheer Ahmed Muddebihal Signed-off-by: Matthew Gerlach --- v2: clean up whitespace and one line comments --- include/linux/dfl.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 33d167c53b09..1e53468ba8d8 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -40,8 +40,29 @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ =20 +/* + * CSR Rel Bit, 1'b0 =3D relative (offset from feature DFH start), + * 1'b1 =3D absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* CSR Header Register Bit Definitions */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR addre= ss */ + +/* CSR SIZE Goup Register Bit Definitions */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration i= nstantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Featur= es/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Paramete= rs */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block = in bytes */ + +/* PARAM Header Register Bit Definitions */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next = Param */ + /** * enum dfl_id_type - define the DFL FIU types */ --=20 2.25.1