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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a2f2bb72d5sm2089319wmq.45.2022.09.23.00.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 00:52:14 -0700 (PDT) From: Jean-Philippe Brucker To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: virtualization@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jean-Philippe Brucker Subject: [PATCH v3] dt-bindings: virtio: Convert virtio,pci-iommu to DT schema Date: Fri, 23 Sep 2022 08:44:38 +0100 Message-Id: <20220923074435.420531-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the binding that describes the virtio-pci based IOMMU to DT schema. Change the compatible string to "pci,", which is defined by the PCI Bus Binding, but keep "virtio,pci-iommu" as an option for backward compatibility. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Krzysztof Kozlowski --- v3: Renamed file and type to pci-iommu v2: https://lore.kernel.org/linux-devicetree/20220922161644.372181-1-jean-p= hilippe@linaro.org/ --- .../devicetree/bindings/virtio/iommu.txt | 66 ------------ .../devicetree/bindings/virtio/pci-iommu.yaml | 101 ++++++++++++++++++ 2 files changed, 101 insertions(+), 66 deletions(-) delete mode 100644 Documentation/devicetree/bindings/virtio/iommu.txt create mode 100644 Documentation/devicetree/bindings/virtio/pci-iommu.yaml diff --git a/Documentation/devicetree/bindings/virtio/iommu.txt b/Documenta= tion/devicetree/bindings/virtio/iommu.txt deleted file mode 100644 index 2407fea0651c..000000000000 --- a/Documentation/devicetree/bindings/virtio/iommu.txt +++ /dev/null @@ -1,66 +0,0 @@ -* virtio IOMMU PCI device - -When virtio-iommu uses the PCI transport, its programming interface is -discovered dynamically by the PCI probing infrastructure. However the -device tree statically describes the relation between IOMMU and DMA -masters. Therefore, the PCI root complex that hosts the virtio-iommu -contains a child node representing the IOMMU device explicitly. - -Required properties: - -- compatible: Should be "virtio,pci-iommu" -- reg: PCI address of the IOMMU. As defined in the PCI Bus - Binding reference [1], the reg property is a five-cell - address encoded as (phys.hi phys.mid phys.lo size.hi - size.lo). phys.hi should contain the device's BDF as - 0b00000000 bbbbbbbb dddddfff 00000000. The other cells - should be zero. -- #iommu-cells: Each platform DMA master managed by the IOMMU is assigned - an endpoint ID, described by the "iommus" property [2]. - For virtio-iommu, #iommu-cells must be 1. - -Notes: - -- DMA from the IOMMU device isn't managed by another IOMMU. Therefore the - virtio-iommu node doesn't have an "iommus" property, and is omitted from - the iommu-map property of the root complex. - -Example: - -pcie@10000000 { - compatible =3D "pci-host-ecam-generic"; - ... - - /* The IOMMU programming interface uses slot 00:01.0 */ - iommu0: iommu@0008 { - compatible =3D "virtio,pci-iommu"; - reg =3D <0x00000800 0 0 0 0>; - #iommu-cells =3D <1>; - }; - - /* - * The IOMMU manages all functions in this PCI domain except - * itself. Omit BDF 00:01.0. - */ - iommu-map =3D <0x0 &iommu0 0x0 0x8> - <0x9 &iommu0 0x9 0xfff7>; -}; - -pcie@20000000 { - compatible =3D "pci-host-ecam-generic"; - ... - /* - * The IOMMU also manages all functions from this domain, - * with endpoint IDs 0x10000 - 0x1ffff - */ - iommu-map =3D <0x0 &iommu0 0x10000 0x10000>; -}; - -ethernet@fe001000 { - ... - /* The IOMMU manages this platform device with endpoint ID 0x20000 */ - iommus =3D <&iommu0 0x20000>; -}; - -[1] Documentation/devicetree/bindings/pci/pci.txt -[2] Documentation/devicetree/bindings/iommu/iommu.txt diff --git a/Documentation/devicetree/bindings/virtio/pci-iommu.yaml b/Docu= mentation/devicetree/bindings/virtio/pci-iommu.yaml new file mode 100644 index 000000000000..972a785a42de --- /dev/null +++ b/Documentation/devicetree/bindings/virtio/pci-iommu.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/virtio/pci-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: virtio-iommu device using the virtio-pci transport + +maintainers: + - Jean-Philippe Brucker + +description: | + When virtio-iommu uses the PCI transport, its programming interface is + discovered dynamically by the PCI probing infrastructure. However the + device tree statically describes the relation between IOMMU and DMA + masters. Therefore, the PCI root complex that hosts the virtio-iommu + contains a child node representing the IOMMU device explicitly. + + DMA from the IOMMU device isn't managed by another IOMMU. Therefore the + virtio-iommu node doesn't have an "iommus" property, and is omitted from + the iommu-map property of the root complex. + +properties: + # If compatible is present, it should contain the vendor and device ID + # according to the PCI Bus Binding specification. Since PCI provides + # built-in identification methods, compatible is not actually required. + compatible: + oneOf: + - items: + - const: virtio,pci-iommu + - const: pci1af4,1057 + - items: + - const: pci1af4,1057 + + reg: + description: | + PCI address of the IOMMU. As defined in the PCI Bus Binding + reference, the reg property is a five-cell address encoded as (phys.= hi + phys.mid phys.lo size.hi size.lo). phys.hi should contain the device= 's + BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should= be + zero. See Documentation/devicetree/bindings/pci/pci.txt + + '#iommu-cells': + const: 1 + +required: + - compatible + - reg + - '#iommu-cells' + +additionalProperties: false + +examples: + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@40000000 { + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x0 0x40000000 0x0 0x1000000>; + ranges =3D <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0= f000000>; + + /* + * The IOMMU manages all functions in this PCI domain except + * itself. Omit BDF 00:01.0. + */ + iommu-map =3D <0x0 &iommu0 0x0 0x8 + 0x9 &iommu0 0x9 0xfff7>; + + /* The IOMMU programming interface uses slot 00:01.0 */ + iommu0: iommu@1,0 { + compatible =3D "pci1af4,1057"; + reg =3D <0x800 0 0 0 0>; + #iommu-cells =3D <1>; + }; + }; + + pcie@50000000 { + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x0 0x50000000 0x0 0x1000000>; + ranges =3D <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0= f000000>; + + /* + * The IOMMU also manages all functions from this domain, + * with endpoint IDs 0x10000 - 0x1ffff + */ + iommu-map =3D <0x0 &iommu0 0x10000 0x10000>; + }; + + ethernet { + /* The IOMMU manages this platform device with endpoint ID 0x2= 0000 */ + iommus =3D <&iommu0 0x20000>; + }; + }; + +... --=20 2.37.3