From nobody Sat Sep 21 15:31:34 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46336C6FA8B for ; Thu, 22 Sep 2022 09:19:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230271AbiIVJTA (ORCPT ); Thu, 22 Sep 2022 05:19:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229492AbiIVJS7 (ORCPT ); Thu, 22 Sep 2022 05:18:59 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C81F3D01F2; Thu, 22 Sep 2022 02:18:57 -0700 (PDT) X-UUID: cb9f9983939f46e4b6b1e727fbb1b345-20220922 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TfqhOqAraOYl4pp9RKfs7slY2GB+uduanHzBsKQ5+dQ=; b=K1aHmLjJG0SslGFO1rJcOsBJAqx4FpMPJqy7+rWlatfH7X3oxQVbsaQk7aF0dlNNhBZdUShfuYkxzxuPHe7gp7dlfrSx75oGfpBmLbDfO0sEI/EcHMDMGvx+7QTjBCVCImBJZk2iJdzA/ZagnziiL4Wk+GHPQIW1WYGDqyvdf+8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:738db8d4-35ff-48c4-bdb7-5f8244b928a2,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:9fbdab06-1cee-4c38-b21b-a45f9682fdc0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: cb9f9983939f46e4b6b1e727fbb1b345-20220922 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 304467776; Thu, 22 Sep 2022 17:18:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 22 Sep 2022 17:18:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 22 Sep 2022 17:18:53 +0800 From: Miles Chen To: Stephen Boyd , Michael Turquette , Matthias Brugger CC: , AngeloGioacchino Del Regno , Chen-Yu Tsai , Chun-Jie Chen , Miles Chen , , , Subject: [PATCH 1/7] clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver Date: Thu, 22 Sep 2022 17:18:29 +0800 Message-ID: <20220922091841.4099-2-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220922091841.4099-1-miles.chen@mediatek.com> References: <20220922091841.4099-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-bdp.c | 36 ++++++++++---------------- drivers/clk/mediatek/clk-mt2701-img.c | 36 ++++++++++---------------- drivers/clk/mediatek/clk-mt2701-vdec.c | 36 ++++++++++---------------- 3 files changed, 39 insertions(+), 69 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index 662a8ab3fbb1..435ed4819d56 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -94,33 +94,23 @@ static const struct mtk_gate bdp_clks[] =3D { GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16), }; =20 -static const struct of_device_id of_match_clk_mt2701_bdp[] =3D { - { .compatible =3D "mediatek,mt2701-bdpsys", }, - {} +static const struct mtk_clk_desc bdp_desc =3D { + .clks =3D bdp_clks, + .num_clks =3D ARRAY_SIZE(bdp_clks), }; =20 -static int clk_mt2701_bdp_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_BDP_NR); - - mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), - clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct of_device_id of_match_clk_mt2701_bdp[] =3D { + { + .compatible =3D "mediatek,mt2701-bdpsys", + .data =3D &bdp_desc, + }, { + /* sentinel */ + } +}; =20 static struct platform_driver clk_mt2701_bdp_drv =3D { - .probe =3D clk_mt2701_bdp_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-bdp", .of_match_table =3D of_match_clk_mt2701_bdp, diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index c4f3cd26df60..7e53deb7f990 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -36,33 +36,23 @@ static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9), }; =20 -static const struct of_device_id of_match_clk_mt2701_img[] =3D { - { .compatible =3D "mediatek,mt2701-imgsys", }, - {} +static const struct mtk_clk_desc img_desc =3D { + .clks =3D img_clks, + .num_clks =3D ARRAY_SIZE(img_clks), }; =20 -static int clk_mt2701_img_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR); - - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), - clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct of_device_id of_match_clk_mt2701_img[] =3D { + { + .compatible =3D "mediatek,mt2701-imgsys", + .data =3D &img_desc, + }, { + /* sentinel */ + } +}; =20 static struct platform_driver clk_mt2701_img_drv =3D { - .probe =3D clk_mt2701_img_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-img", .of_match_table =3D of_match_clk_mt2701_img, diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index a2f18117f27a..d3089da0ab62 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -47,33 +47,23 @@ static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0), }; =20 -static const struct of_device_id of_match_clk_mt2701_vdec[] =3D { - { .compatible =3D "mediatek,mt2701-vdecsys", }, - {} +static const struct mtk_clk_desc vdec_desc =3D { + .clks =3D vdec_clks, + .num_clks =3D ARRAY_SIZE(vdec_clks), }; =20 -static int clk_mt2701_vdec_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR); - - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct of_device_id of_match_clk_mt2701_vdec[] =3D { + { + .compatible =3D "mediatek,mt2701-vdecsys", + .data =3D &vdec_desc, + }, { + /* sentinel */ + } +}; =20 static struct platform_driver clk_mt2701_vdec_drv =3D { - .probe =3D clk_mt2701_vdec_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-vdec", .of_match_table =3D of_match_clk_mt2701_vdec, --=20 2.18.0