From nobody Thu Apr 2 19:58:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F158BC6FA82 for ; Wed, 21 Sep 2022 15:53:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231749AbiIUPw6 (ORCPT ); Wed, 21 Sep 2022 11:52:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231720AbiIUPvh (ORCPT ); Wed, 21 Sep 2022 11:51:37 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DE0B339; Wed, 21 Sep 2022 08:49:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8D6B76313C; Wed, 21 Sep 2022 15:49:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E66CC433D6; Wed, 21 Sep 2022 15:49:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1663775347; bh=jnrtrwVThl7jBOaHqlfiiHiaXpyyPz87zg3tkY08qJc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VUT3/NW9hmcQAaPJYQhmuVxDuYlXY8yVJZ52Ky8OwUcyYiD3xZJX/rVzHBXSFdA+y eliaU5FURzggPNkgaw+9m5SYwR986RXmFruLIRmUa9F2VpMQw9BH0LPphRvzif5wLA kRaAxz5bvluYyW+KmvrpFlygG7Rl8t1ULB0+OEf8= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Gustaw Smolarczyk , Lijo Lazar , Alex Deucher Subject: [PATCH 5.15 22/45] drm/amdgpu: Dont enable LTR if not supported Date: Wed, 21 Sep 2022 17:46:12 +0200 Message-Id: <20220921153647.598306582@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921153646.931277075@linuxfoundation.org> References: <20220921153646.931277075@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lijo Lazar commit 6c20490663553cd7e07d8de8af482012329ab9d6 upstream. As per PCIE Base Spec r4.0 Section 6.18 'Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR.' This fixes the Unsupported Request error reported through AER during ASPM enablement. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D216455 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_= device_capability()") Reported-by: Gustaw Smolarczyk Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 9 ++++++++- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 9 ++++++++- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -366,6 +366,7 @@ static void nbio_v2_3_enable_aspm(struct WREG32_PCIE(smnPCIE_LC_CNTL, data); } =20 +#ifdef CONFIG_PCIEASPM static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) { uint32_t def, data; @@ -387,9 +388,11 @@ static void nbio_v2_3_program_ltr(struct if (def !=3D data) WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); } +#endif =20 static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) { +#ifdef CONFIG_PCIEASPM uint32_t def, data; =20 def =3D data =3D RREG32_PCIE(smnPCIE_LC_CNTL); @@ -445,7 +448,10 @@ static void nbio_v2_3_program_aspm(struc if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL6, data); =20 - nbio_v2_3_program_ltr(adev); + /* Don't bother about LTR if LTR is not enabled + * in the path */ + if (adev->pdev->ltr_path) + nbio_v2_3_program_ltr(adev); =20 def =3D data =3D RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); data |=3D 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; @@ -469,6 +475,7 @@ static void nbio_v2_3_program_aspm(struc data &=3D ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL3, data); +#endif } =20 static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev) --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -278,6 +278,7 @@ static void nbio_v6_1_init_registers(str WREG32_PCIE(smnPCIE_CI_CNTL, data); } =20 +#ifdef CONFIG_PCIEASPM static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) { uint32_t def, data; @@ -299,9 +300,11 @@ static void nbio_v6_1_program_ltr(struct if (def !=3D data) WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); } +#endif =20 static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) { +#ifdef CONFIG_PCIEASPM uint32_t def, data; =20 def =3D data =3D RREG32_PCIE(smnPCIE_LC_CNTL); @@ -357,7 +360,10 @@ static void nbio_v6_1_program_aspm(struc if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL6, data); =20 - nbio_v6_1_program_ltr(adev); + /* Don't bother about LTR if LTR is not enabled + * in the path */ + if (adev->pdev->ltr_path) + nbio_v6_1_program_ltr(adev); =20 def =3D data =3D RREG32_PCIE(smnRCC_BIF_STRAP3); data |=3D 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; @@ -381,6 +387,7 @@ static void nbio_v6_1_program_aspm(struc data &=3D ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL3, data); +#endif } =20 const struct amdgpu_nbio_funcs nbio_v6_1_funcs =3D { --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -630,6 +630,7 @@ const struct amdgpu_nbio_ras_funcs nbio_ .ras_fini =3D amdgpu_nbio_ras_fini, }; =20 +#ifdef CONFIG_PCIEASPM static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) { uint32_t def, data; @@ -651,9 +652,11 @@ static void nbio_v7_4_program_ltr(struct if (def !=3D data) WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); } +#endif =20 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) { +#ifdef CONFIG_PCIEASPM uint32_t def, data; =20 def =3D data =3D RREG32_PCIE(smnPCIE_LC_CNTL); @@ -709,7 +712,10 @@ static void nbio_v7_4_program_aspm(struc if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL6, data); =20 - nbio_v7_4_program_ltr(adev); + /* Don't bother about LTR if LTR is not enabled + * in the path */ + if (adev->pdev->ltr_path) + nbio_v7_4_program_ltr(adev); =20 def =3D data =3D RREG32_PCIE(smnRCC_BIF_STRAP3); data |=3D 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; @@ -733,6 +739,7 @@ static void nbio_v7_4_program_aspm(struc data &=3D ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; if (def !=3D data) WREG32_PCIE(smnPCIE_LC_CNTL3, data); +#endif } =20 const struct amdgpu_nbio_funcs nbio_v7_4_funcs =3D {