From nobody Sat Sep 21 17:16:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94024ECAAD8 for ; Wed, 21 Sep 2022 09:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231451AbiIUJPs (ORCPT ); Wed, 21 Sep 2022 05:15:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231346AbiIUJPT (ORCPT ); Wed, 21 Sep 2022 05:15:19 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E50AA3FA1B; Wed, 21 Sep 2022 02:15:17 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1314D660203A; Wed, 21 Sep 2022 10:15:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1663751716; bh=WC6+3zs0TTK7nz9pxwcyEOmuluWn+r9om49txfLNcZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WUP+1pB9R9WXUIybFJyk1YHHSJdUHlqBrzF3hPQzk/dBG1xe0fVjxY0G9LDBBYBr4 s6A04uoJh6wkkVHaW0cLp6dFAREkBZC0yCfPTDkB3Pgi6hdyn/1Dv1HriZHUFamQD0 4AgCtVO82qWpWBhzuHxaNkc0BjVgcmUkvVJdMC2n9dGCNotp1XNS/daGhwAw4KJs/F ClVjRt/eXO3PR/2fi2V4WIBYZkOuPKI0J693/bkJQV7oJ7dmYQcYu56nwHbezqWbqD YmI5Azgx2yE0II5RanA1NoLN1iZsWakOcr/W3hfGZPpry88GinHgPANGY5Iuq+B/BX uka/a4KHElgeA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, y.oudjana@protonmail.com, angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, ck.hu@mediatek.com, fparent@baylibre.com, rex-bc.chen@mediatek.com, tinghan.shen@mediatek.com, ikjn@chromium.org, miles.chen@mediatek.com, sam.shih@mediatek.com, wenst@chromium.org, bgolaszewski@baylibre.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, kernel@collabora.com, Rob Herring Subject: [RESEND PATCH v6 4/8] dt-bindings: clock: mediatek: Add clock driver bindings for MT6795 Date: Wed, 21 Sep 2022 11:14:51 +0200 Message-Id: <20220921091455.41327-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220921091455.41327-1-angelogioacchino.delregno@collabora.com> References: <20220921091455.41327-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring --- .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++++ .../clock/mediatek,mt6795-sys-clock.yaml | 54 +++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795= -clock.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795= -sys-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml new file mode 100644 index 000000000000..04469eabc8fa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno + - Chun-Jie Chen + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mfgcfg: clock-controller@13000000 { + compatible =3D "mediatek,mt6795-mfgcfg"; + reg =3D <0 0x13000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible =3D "mediatek,mt6795-vdecsys"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vencsys: clock-controller@18000000 { + compatible =3D "mediatek,mt6795-vencsys"; + reg =3D <0 0x18000000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-cloc= k.yaml new file mode 100644 index 000000000000..378b761237d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno + - Chun-Jie Chen + +description: + The Mediatek system clock controller provides various clocks and system + configuration like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + topckgen: clock-controller@10000000 { + compatible =3D "mediatek,mt6795-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; --=20 2.37.2