From nobody Thu Apr 2 21:31:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2841BC6FA82 for ; Wed, 21 Sep 2022 03:15:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229630AbiIUDPC (ORCPT ); Tue, 20 Sep 2022 23:15:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231207AbiIUDN4 (ORCPT ); Tue, 20 Sep 2022 23:13:56 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BBC57E323; Tue, 20 Sep 2022 20:13:54 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dm5a049745; Tue, 20 Sep 2022 22:13:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730028; bh=I+nGWrcAi/D1mbpmFU+/PWqTsF+4nqx+/Nw37+CSyDo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=E8wRtln5wOufXmq7KOKj9Vmu6PhMCl7eWsq04Jkw5e7Q1ejlLLrwKy4iD5d7BAMH5 SP+EMdB77elW1tZZ4onpzii21YFNrvXWyiSWClIsn3KiRjRyoJrwFhEa/LfmwQ0nf2 eLtwMYNADyWXHAo4mQQYEQ2IIgtGKcY0DD3SUBm0= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DmaI015710 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:48 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:47 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:48 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DjDU011064; Tue, 20 Sep 2022 22:13:47 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 5/9] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Tue, 20 Sep 2022 20:13:23 -0700 Message-ID: <20220921031327.4135-6-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 791f235bd95f..aa75dc541842 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx0 { @@ -372,6 +378,22 @@ serdes0_pcie_link: phy@0 { }; }; =20 +&usb_serdes_mux { + idle-states =3D <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; --=20 2.37.2