From nobody Thu Apr 2 21:30:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14C3FC6FA82 for ; Wed, 21 Sep 2022 03:14:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbiIUDOQ (ORCPT ); Tue, 20 Sep 2022 23:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230527AbiIUDNw (ORCPT ); Tue, 20 Sep 2022 23:13:52 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DAAB7E312; Tue, 20 Sep 2022 20:13:50 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DjiW040831; Tue, 20 Sep 2022 22:13:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730025; bh=4USz15EscPrhZXEZj5iD4JTv7qfTP2nH8DHZYb8coM8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JdZCgyq6rJCBgI+UikOubcDW8Xy0kfrCLk+3NA9FGSDjY/iHUjnoe0yAKZSybpZrp PBkHV7s41mfA9QoYM+Bu/o8iXcs1cBBsAPlXABPPaXIMgR3vLGti9+knLVv/asiG/X EPFtEXvClunYVzbpjNoMQRz9l8EzfPSwELBf7DII= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3Dj7V044232 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:45 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:44 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:44 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DgxO074383; Tue, 20 Sep 2022 22:13:43 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 4/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Tue, 20 Sep 2022 20:13:22 -0700 Message-ID: <20220921031327.4135-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b210cc07c539..791f235bd95f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ =20 #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include =20 / { compatible =3D "ti,j721s2-evm", "ti,j721s2"; @@ -350,6 +353,25 @@ &cpsw_port1 { phy-handle =3D <&phy0>; }; =20 +&serdes_ln_ctrl { + idle-states =3D , , + , ; +}; + +&serdes_refclk { + clock-frequency =3D <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; --=20 2.37.2