From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1E59C6FA82 for ; Wed, 21 Sep 2022 03:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbiIUDO2 (ORCPT ); Tue, 20 Sep 2022 23:14:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbiIUDNu (ORCPT ); Tue, 20 Sep 2022 23:13:50 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E501E7E31C; Tue, 20 Sep 2022 20:13:42 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DYDU051238; Tue, 20 Sep 2022 22:13:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730014; bh=ZrUHB7hSiwgO8aC2igzluVfUcksEqQq/batRKS59/R4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EQOpzvJdgGNK4/Hv8fLY1IyJXscxxrLRVonR5uei2Eo2Wp+AwrFWZYURG47l+a13J 1s3G0udKgk5fp8ekhZ6hb/IA8dcFEqbZDLPPE/FaetjeO7we91t3/9SmEuo5CyKZl3 eDUxXzhOUHxWYhn7+dHVQGEk5nJV3OlUO1tiZMoU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DYph083391 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:34 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:33 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:33 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DVPF074149; Tue, 20 Sep 2022 22:13:32 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 1/9] arm64: dts: ti: k3-j721s2-main: Add support for USB Date: Tue, 20 Sep 2022 20:13:19 -0700 Message-ID: <20220921031327.4135-2-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for single instance of USB 3.0 controller in J721S2 SoC. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 34e7d577ae13..1f178ad3fa42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,20 @@ l3cache-sram@200000 { }; }; =20 + scm_conf: syscon@104000 { + compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg =3D <0x00 0x00104000 0x00 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller-0 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; @@ -686,6 +700,34 @@ cpts@310d0000 { }; }; =20 + usbss0: cdns-usb@4104000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x04104000 0x00 0x100>; + clocks =3D <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 360 17>; + power-domains =3D <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-coherent; + + usb0: usb@6000000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D , + , + ; + interrupt-names =3D "host", "peripheral", "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D692C6FA82 for ; Wed, 21 Sep 2022 03:14:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230352AbiIUDOu (ORCPT ); Tue, 20 Sep 2022 23:14:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231209AbiIUDN5 (ORCPT ); Tue, 20 Sep 2022 23:13:57 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 578C07E324; Tue, 20 Sep 2022 20:13:54 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Db5M049714; Tue, 20 Sep 2022 22:13:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730017; bh=N6qozps8bDMn9lW8NQSWgT9uC5bba9QSDWJQchNs+BI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eGVoHzLC5zDo4k7qzweONJ3gQATe5JRlOQJujxwBjivNLmDRZ2VkrEA805OIiGSvU y88xMS3fABCcy5Dd+2EH3RPchDrkrKIKri6+6cbuVBTdv6YaUzkk5UFftfuOYnDf+p QM7itrSsYa0jbttNSMyGhPb44DDDaOUqWyElFcXg= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DbL5083406 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:37 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:37 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:37 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DYHJ010818; Tue, 20 Sep 2022 22:13:36 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 2/9] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Date: Tue, 20 Sep 2022 20:13:20 -0700 Message-ID: <20220921031327.4135-3-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Cc: Vignesh Raghavendra Cc: Nishanth Menon Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 1f178ad3fa42..a4260ffb75c7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,16 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -38,6 +48,13 @@ usb_serdes_mux: mux-controller-0 { #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller-80 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; =20 gic500: interrupt-controller@1800000 { @@ -728,6 +745,42 @@ usb0: usb@6000000 { }; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,am64-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks =3D <&k3_clks 365 3>; + assigned-clock-parents =3D <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B941C6FA82 for ; Wed, 21 Sep 2022 03:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbiIUDOm (ORCPT ); Tue, 20 Sep 2022 23:14:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbiIUDNz (ORCPT ); Tue, 20 Sep 2022 23:13:55 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F8A37E322; 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Tue, 20 Sep 2022 22:13:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:41 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dcqa074289; Tue, 20 Sep 2022 22:13:39 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 3/9] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Date: Tue, 20 Sep 2022 20:13:21 -0700 Message-ID: <20220921031327.4135-4-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for two instance of OSPI in J721S2 SoC. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4d1bfabd1313..7bc268f27030 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -299,4 +299,44 @@ cpts@3d000 { ti,cpts-periodic-outputs =3D <2>; }; }; + + fss: syscon@47000000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x0 0x47000000 0x0 0x100>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ospi0: spi@47040000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47040000 0x00 0x100>, + <0x5 0x0000000 0x1 0x0000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 109 5>; + assigned-clocks =3D <&k3_clks 109 5>; + assigned-clock-parents =3D <&k3_clks 109 7>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + ospi1: spi@47050000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47050000 0x00 0x100>, + <0x7 0x0000000 0x1 0x0000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 110 5>; + power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + }; }; --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14C3FC6FA82 for ; Wed, 21 Sep 2022 03:14:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbiIUDOQ (ORCPT ); Tue, 20 Sep 2022 23:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230527AbiIUDNw (ORCPT ); Tue, 20 Sep 2022 23:13:52 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DAAB7E312; Tue, 20 Sep 2022 20:13:50 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DjiW040831; Tue, 20 Sep 2022 22:13:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730025; bh=4USz15EscPrhZXEZj5iD4JTv7qfTP2nH8DHZYb8coM8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JdZCgyq6rJCBgI+UikOubcDW8Xy0kfrCLk+3NA9FGSDjY/iHUjnoe0yAKZSybpZrp PBkHV7s41mfA9QoYM+Bu/o8iXcs1cBBsAPlXABPPaXIMgR3vLGti9+knLVv/asiG/X EPFtEXvClunYVzbpjNoMQRz9l8EzfPSwELBf7DII= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3Dj7V044232 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:45 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:44 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:44 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DgxO074383; Tue, 20 Sep 2022 22:13:43 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 4/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Tue, 20 Sep 2022 20:13:22 -0700 Message-ID: <20220921031327.4135-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b210cc07c539..791f235bd95f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ =20 #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include =20 / { compatible =3D "ti,j721s2-evm", "ti,j721s2"; @@ -350,6 +353,25 @@ &cpsw_port1 { phy-handle =3D <&phy0>; }; =20 +&serdes_ln_ctrl { + idle-states =3D , , + , ; +}; + +&serdes_refclk { + clock-frequency =3D <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2841BC6FA82 for ; Wed, 21 Sep 2022 03:15:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229630AbiIUDPC (ORCPT ); Tue, 20 Sep 2022 23:15:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231207AbiIUDN4 (ORCPT ); Tue, 20 Sep 2022 23:13:56 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BBC57E323; Tue, 20 Sep 2022 20:13:54 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dm5a049745; Tue, 20 Sep 2022 22:13:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730028; bh=I+nGWrcAi/D1mbpmFU+/PWqTsF+4nqx+/Nw37+CSyDo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=E8wRtln5wOufXmq7KOKj9Vmu6PhMCl7eWsq04Jkw5e7Q1ejlLLrwKy4iD5d7BAMH5 SP+EMdB77elW1tZZ4onpzii21YFNrvXWyiSWClIsn3KiRjRyoJrwFhEa/LfmwQ0nf2 eLtwMYNADyWXHAo4mQQYEQ2IIgtGKcY0DD3SUBm0= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DmaI015710 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:48 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:47 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:48 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DjDU011064; Tue, 20 Sep 2022 22:13:47 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 5/9] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Tue, 20 Sep 2022 20:13:23 -0700 Message-ID: <20220921031327.4135-6-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 791f235bd95f..aa75dc541842 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx0 { @@ -372,6 +378,22 @@ serdes0_pcie_link: phy@0 { }; }; =20 +&usb_serdes_mux { + idle-states =3D <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB593C6FA82 for ; Wed, 21 Sep 2022 03:15:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230489AbiIUDPQ (ORCPT ); Tue, 20 Sep 2022 23:15:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231250AbiIUDOD (ORCPT ); Tue, 20 Sep 2022 23:14:03 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99DAA7E334; Tue, 20 Sep 2022 20:13:59 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dp2j034363; Tue, 20 Sep 2022 22:13:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730031; bh=Rp8YMiq1/xP1RLJDQd85gu+rQhLvpDn1uVk1XkCvvks=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=p7sbj7UNYGLNQShzWJFWOp39Brhn2V+foKwxOn4jVxbbNpQg251ys4v0mwX6j2Sva 5+FZh3ja23cXhpcPn8CP4pQCQ+DmYxpOIWnJm9VYq34T1zScDHOdOF/rp7mYpU0X5V z8/Kp0lRfgEnyVKEX4eOjM6Limel03z07KuNSU1g= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DphR015726 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:51 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:51 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:51 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DnR0009824; Tue, 20 Sep 2022 22:13:50 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 6/9] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Tue, 20 Sep 2022 20:13:24 -0700 Message-ID: <20220921031327.4135-7-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 4 +- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++ 3 files changed, 78 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index aa75dc541842..cb99a97af426 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-defau= lt { J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; =20 &main_gpio2 { @@ -394,6 +408,26 @@ &usb0 { maximum-speed =3D "high-speed"; }; =20 +&ospi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 7bc268f27030..ab49f8266d10 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -301,8 +301,8 @@ cpts@3d000 { }; =20 fss: syscon@47000000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x0 0x47000000 0x0 0x100>; + compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg =3D <0x00 0x47000000 0x00 0x100>; #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 76f0ceacb6d4..a05c17dd69b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ transceiver0: can-phy0 { }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins =3D < @@ -78,6 +100,26 @@ &main_mcan16 { phys =3D <&transceiver0>; }; =20 +&ospi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mailbox0_cluster0 { status =3D "disabled"; }; --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2B25C6FA82 for ; Wed, 21 Sep 2022 03:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbiIUDPI (ORCPT ); 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Tue, 20 Sep 2022 22:13:55 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:55 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:55 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DqpU011186; Tue, 20 Sep 2022 22:13:54 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 7/9] dt-bindings: PCI: Add host mode device-id for j721s2 platform Date: Tue, 20 Sep 2022 20:13:25 -0700 Message-ID: <20220921031327.4135-8-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add unique device-id of 0xb013 for j721s2 platform to oneOf field. Signed-off-by: Matt Ranostay Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b= /Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 2115d5a3f0e1..ba8def03b691 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -73,6 +73,8 @@ properties: - const: 0xb00f - items: - const: 0xb010 + - items: + - const: 0xb013 =20 msi-map: true =20 --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EE3DC6FA82 for ; Wed, 21 Sep 2022 03:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231172AbiIUDPV (ORCPT ); Tue, 20 Sep 2022 23:15:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230217AbiIUDOE (ORCPT ); Tue, 20 Sep 2022 23:14:04 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 889137AC36; Tue, 20 Sep 2022 20:14:03 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dxst040846; Tue, 20 Sep 2022 22:13:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730039; bh=KTfIkBAgkkJeo7UshvmEefNsEe/R1AD4BsxUGVSwyHA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jtqZENrvpQVxxINaFpA2xiLSVCkccurIsErj8mbY6EgcMQ7d85qB4dUn39im7Kd9X dWSaMS8LYYWh1Vt8G4NyxrETQfcYbGF4wDAsP3aQKmCm/WoQUBVwZ7T6jIHGbnhlvH k3DPM9FiQrBuMvikXzHFcuo/CeCtgEY8R18CIRF4= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DxO6118012 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:59 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:58 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:58 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DuoO063192; Tue, 20 Sep 2022 22:13:57 -0500 From: Matt Ranostay To: , , CC: , , Subject: [PATCH v3 8/9] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Date: Tue, 20 Sep 2022 20:13:26 -0700 Message-ID: <20220921031327.4135-9-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j721s2. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index a4260ffb75c7..fc4cf8b4a28b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -781,6 +781,67 @@ serdes0: serdes@5060000 { }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.37.2 From nobody Thu Apr 2 19:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAAD8C6FA82 for ; Wed, 21 Sep 2022 03:15:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229916AbiIUDP2 (ORCPT ); Tue, 20 Sep 2022 23:15:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230368AbiIUDOH (ORCPT ); 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Tue, 20 Sep 2022 22:14:02 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:14:02 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Dx3N063245; Tue, 20 Sep 2022 22:14:01 -0500 From: Matt Ranostay To: , , CC: , , Subject: [PATCH v3 9/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Tue, 20 Sep 2022 20:13:27 -0700 Message-ID: <20220921031327.4135-10-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index cb99a97af426..793ee77838f4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -428,6 +428,20 @@ flash@0{ }; }; =20 +&pcie1_rc { + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; +}; + +&pcie1_ep { + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; + status =3D "disabled"; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; --=20 2.37.2