From nobody Thu Apr 2 22:59:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E1C1ECAAD8 for ; Tue, 20 Sep 2022 11:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230456AbiITLmC (ORCPT ); Tue, 20 Sep 2022 07:42:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230027AbiITLlp (ORCPT ); Tue, 20 Sep 2022 07:41:45 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 393807171F for ; Tue, 20 Sep 2022 04:41:29 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id bu5-20020a17090aee4500b00202e9ca2182so1319270pjb.0 for ; Tue, 20 Sep 2022 04:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=S/VY5MZwOkPVf4gf0OmaE3pHGUVQux0NVg5TTa4NfT8=; b=NqTOe3iiUQICAXunR2DJaV/3zsHDSJpEw+TwFpamvurkELyWckCG2t6an2YRvKW5Sl ZbICfqeSBGkudUhvJYL9b0BY0f9rtGW7n0MMPfzhNs6iqdeNf7jqmfp+i014B6ZUFzIm RyYbE7NkqBfcSUToaKyItyfaoVcB4mpTJramTrh5QecNsmNvdtI77NUUKrhX204KBAa1 ugeLYqZdu0hEk9/+bEWA1UBK0IFPPj9uiX+rXS6IVXE2xPcS20DG2uNf2zFdtMGsIHwi DJsqUlDSoJ8itYLNrYjO8uDq/SmAPIoOXxzXqe9/TT/M1hcX4UOdZSIqyr0S8yPPWNaA UDlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=S/VY5MZwOkPVf4gf0OmaE3pHGUVQux0NVg5TTa4NfT8=; b=D9eRo2F1nvprmClY6mnjw15moAFxoDcsj2TBKkpoCbUkdCm/lPjqOVZI/tt3aiueLu ln9BUwYNvoLt3hfL9o8ZQ2p2qVgbJmTimydqylly/t2kQ0A0aq6OKcQDdrj+M6Y435Fg lfO4skwToECQtWj/BNdjhSOyGN/KciHVR2C5MfJt7K84+jX8spML6c4aRUxu8wDAQ/Md eOGCt8k9sc2X2kD/FKOoNGidbHTfTp55yfY/utDupIE+PCZQ9AMASuFbI+bEuqmZ7Z2N BV+ncgKn2ISIC2LcRowh6qg3dy639km9JEisxg5SrxC4Ee7TemFMTXWQ74XULrTIw55X N3+A== X-Gm-Message-State: ACrzQf2s6xi1Lznb8NzmiXRuMBqi/Xv9rYJFbzc87ltKYhNixPvZwvE1 A3eKuakCKPiT1fYgswg1kc/z5w== X-Google-Smtp-Source: AMsMyM5DsNX3RgjSRPJweeS5J16q4ACPjJjDNmXrM1xncre90UD6HKG2UPAJycXK3zCZiHWC4cM0UA== X-Received: by 2002:a17:902:eb90:b0:178:25ab:b3ee with SMTP id q16-20020a170902eb9000b0017825abb3eemr4360076plg.23.1663674088867; Tue, 20 Sep 2022 04:41:28 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c61:6535:ca5f:67d1:670d:e188]) by smtp.gmail.com with ESMTPSA id p30-20020a63741e000000b00434e57bfc6csm1348793pgc.56.2022.09.20.04.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 04:41:28 -0700 (PDT) From: Bhupesh Sharma To: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, herbert@gondor.apana.org.au, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, thara.gopinath@gmail.com, robh@kernel.org, krzysztof.kozlowski@linaro.org, andersson@kernel.org, bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, davem@davemloft.net, Jordan Crouse Subject: [PATCH v7 5/9] crypto: qce: core: Add support to initialize interconnect path Date: Tue, 20 Sep 2022 17:10:47 +0530 Message-Id: <20220920114051.1116441-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220920114051.1116441-1-bhupesh.sharma@linaro.org> References: <20220920114051.1116441-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Thara Gopinath Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 etc. requires interconnect path between the engine and memory to be explicitly enabled and bandwidth set prior to any operations. Add support in the qce core to enable the interconnect path appropriately. Cc: Bjorn Andersson Cc: Rob Herring Cc: herbert@gondor.apana.org.au Tested-by: Jordan Crouse Signed-off-by: Thara Gopinath Signed-off-by: Bhupesh Sharma [Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()] --- drivers/crypto/qce/core.c | 16 +++++++++++++++- drivers/crypto/qce/core.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index d3780be44a76..63be06df5519 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -22,6 +23,8 @@ #define QCE_MAJOR_VERSION5 0x05 #define QCE_QUEUE_LENGTH 1 =20 +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 + static const struct qce_algo_ops *qce_ops[] =3D { #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER &skcipher_ops, @@ -206,6 +209,10 @@ static int qce_crypto_probe(struct platform_device *pd= ev) if (ret < 0) return ret; =20 + qce->mem_path =3D devm_of_icc_get(qce->dev, "memory"); + if (IS_ERR(qce->mem_path)) + return PTR_ERR(qce->mem_path); + qce->core =3D devm_clk_get(qce->dev, "core"); if (IS_ERR(qce->core)) return PTR_ERR(qce->core); @@ -218,10 +225,14 @@ static int qce_crypto_probe(struct platform_device *p= dev) if (IS_ERR(qce->bus)) return PTR_ERR(qce->bus); =20 - ret =3D clk_prepare_enable(qce->core); + ret =3D icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_= MEM_BANDWIDTH); if (ret) return ret; =20 + ret =3D clk_prepare_enable(qce->core); + if (ret) + goto err_mem_path_disable; + ret =3D clk_prepare_enable(qce->iface); if (ret) goto err_clks_core; @@ -260,6 +271,9 @@ static int qce_crypto_probe(struct platform_device *pde= v) clk_disable_unprepare(qce->iface); err_clks_core: clk_disable_unprepare(qce->core); +err_mem_path_disable: + icc_set_bw(qce->mem_path, 0, 0); + return ret; } =20 diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 085774cdf641..228fcd69ec51 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -35,6 +35,7 @@ struct qce_device { void __iomem *base; struct device *dev; struct clk *core, *iface, *bus; + struct icc_path *mem_path; struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; --=20 2.37.1