From nobody Thu Apr 2 21:31:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A151C54EE9 for ; Tue, 20 Sep 2022 09:47:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230232AbiITJrh (ORCPT ); Tue, 20 Sep 2022 05:47:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229866AbiITJr3 (ORCPT ); Tue, 20 Sep 2022 05:47:29 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DF5C6B179; Tue, 20 Sep 2022 02:47:27 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28K9lLCm130892; Tue, 20 Sep 2022 04:47:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663667242; bh=pBcOtFMNMFpiWfmGRPsmc7gXS+Bf4K0LEqsKB/wbEkA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PDCa2v6NtIr4+6zx82lfps5Jt44s5gqq+THiexfMRQNPd92sZRc1Jb8w5w0xDcHb/ Hi6Ye0FEwF2JbkxOrG7jX5+iLF2JoolL9Lh0evyEr8+wnT3+eC1hCCVZA61iJexuRr mHG4W4DGGHq/OVbmmUE8S9xxz9eC+bKHlnnsBtzI= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28K9lLia078333 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 04:47:21 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 04:47:21 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 04:47:21 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28K9lKgP027111; Tue, 20 Sep 2022 04:47:21 -0500 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v5 1/2] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs Date: Tue, 20 Sep 2022 15:17:12 +0530 Message-ID: <20220920094713.18950-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220920094713.18950-1-r-ravikumar@ti.com> References: <20220920094713.18950-1-r-ravikumar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vijay Pothukuchi Add dts nodes for 6 EHRPWM instances on SoC Signed-off-by: Vijay Pothukuchi Signed-off-by: Rahul T R --- .../dts/ti/k3-j721e-common-proc-board.dts | 24 +++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 +++++++ 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index b1691ac3442d..4f8ab839fbc4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -995,3 +995,27 @@ &main_mcan12 { &main_mcan13 { status =3D "disabled"; }; + +&main_ehrpwm0 { + status =3D "disabled"; +}; + +&main_ehrpwm1 { + status =3D "disabled"; +}; + +&main_ehrpwm2 { + status =3D "disabled"; +}; + +&main_ehrpwm3 { + status =3D "disabled"; +}; + +&main_ehrpwm4 { + status =3D "disabled"; +}; + +&main_ehrpwm5 { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 917c9dc99efa..2027c724a2d6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -66,7 +66,67 @@ usb_serdes_mux: mux-controller@4000 { #mux-control-cells =3D <1>; mux-reg-masks =3D <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible =3D "ti,am654-ehrpwm-tbclk", "syscon"; + reg =3D <0x4140 0x18>; + #clock-cells =3D <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3000000 0x00 0x100>; + power-domains =3D <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3010000 0x00 0x100>; + power-domains =3D <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3020000 0x00 0x100>; + power-domains =3D <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3030000 0x00 0x100>; + power-domains =3D <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3040000 0x00 0x100>; + power-domains =3D <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x3050000 0x00 0x100>; + power-domains =3D <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names =3D "tbclk", "fck"; }; =20 gic500: interrupt-controller@1800000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 80358cba6954..98a55778f3fe 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1129,3 +1129,27 @@ &c71_0 { memory-region =3D <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; + +&main_ehrpwm0 { + status =3D "disabled"; +}; + +&main_ehrpwm1 { + status =3D "disabled"; +}; + +&main_ehrpwm2 { + status =3D "disabled"; +}; + +&main_ehrpwm3 { + status =3D "disabled"; +}; + +&main_ehrpwm4 { + status =3D "disabled"; +}; + +&main_ehrpwm5 { + status =3D "disabled"; +}; --=20 2.37.3 From nobody Thu Apr 2 21:31:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FDD8ECAAD8 for ; Tue, 20 Sep 2022 09:47:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230369AbiITJrw (ORCPT ); Tue, 20 Sep 2022 05:47:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230313AbiITJrm (ORCPT ); Tue, 20 Sep 2022 05:47:42 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C97DE6E2DC; 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Tue, 20 Sep 2022 04:47:23 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28K9lMJA100432; Tue, 20 Sep 2022 04:47:23 -0500 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v5 2/2] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Date: Tue, 20 Sep 2022 15:17:13 +0530 Message-ID: <20220920094713.18950-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220920094713.18950-1-r-ravikumar@ti.com> References: <20220920094713.18950-1-r-ravikumar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sinthu Raja Add pinmux required to bring out i2c5 and gpios on 40 pin RPi header on sk board Signed-off-by: Sinthu Raja Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 55 +++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 98a55778f3fe..a418494d1fd6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -400,6 +400,47 @@ ekey_reset_pins_default: ekey-reset-pns-pins-default { J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_S= CL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_S= DA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; }; =20 &wkup_pmx0 { @@ -633,7 +674,9 @@ &main_i2c4 { =20 &main_i2c5 { /* Brought out on RPi Header */ - status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; }; =20 &main_i2c6 { @@ -1153,3 +1196,13 @@ &main_ehrpwm4 { &main_ehrpwm5 { status =3D "disabled"; }; + +&main_gpio0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_gpio1_pins_default>; +}; --=20 2.37.3