From nobody Sat Sep 21 17:04:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9775ECAAD8 for ; Tue, 20 Sep 2022 09:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230439AbiITJEI (ORCPT ); Tue, 20 Sep 2022 05:04:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231614AbiITJC0 (ORCPT ); Tue, 20 Sep 2022 05:02:26 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0E616C76E for ; Tue, 20 Sep 2022 02:02:09 -0700 (PDT) X-UUID: 722250fe614c45978e59a70f38af7c86-20220920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VyahJL+MfWqllq63TY1YFqUJAezoEPsb3Sn9XQWCiVQ=; b=troxGkZ0iG/myN5EDF1Br+HavFuAFisWpR4zSTMbuHfDSuQEq4rFAUggTFrKSkpO2P4zIFp3N/0H+yl7zPiG68JecDyRH5IvAnj+bgE7cv2CtoJYswNlH8HU7R4umpVtnRxX9rgJzaT9zbRbNk64jzWseLDUeZXrUSvgvVos77w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:b573e125-5033-48ae-9ff7-62b95d00ada7,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:39a5ff1,CLOUDID:d5ca6670-dafa-4a42-b716-cf2cd4845592,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 722250fe614c45978e59a70f38af7c86-20220920 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1907861798; Tue, 20 Sep 2022 17:01:48 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 17:00:54 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Sep 2022 17:00:54 +0800 From: Chunfeng Yun To: Chun-Kuang Hu , Vinod Koul CC: Philipp Zabel , Chunfeng Yun , Kishon Vijay Abraham I , Matthias Brugger , , , , , , Jitao Shi , Stanley Chu Subject: [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Date: Tue, 20 Sep 2022 17:00:38 +0800 Message-ID: <20220920090038.15133-19-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com> References: <20220920090038.15133-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove private register access helpers, use the common ones instead. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 24 ------------------------ drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 5 ----- 2 files changed, 29 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek= /phy-mtk-mipi-dsi.c index 28506932bd91..cf9c386385bb 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c @@ -10,30 +10,6 @@ inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struc= t clk_hw *hw) return container_of(hw, struct mtk_mipi_tx, pll_hw); } =20 -void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 bits) -{ - u32 temp =3D readl(mipi_tx->regs + offset); - - writel(temp & ~bits, mipi_tx->regs + offset); -} - -void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 bits) -{ - u32 temp =3D readl(mipi_tx->regs + offset); - - writel(temp | bits, mipi_tx->regs + offset); -} - -void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 mask, u32 data) -{ - u32 temp =3D readl(mipi_tx->regs + offset); - - writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset); -} - int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek= /phy-mtk-mipi-dsi.h index c76f07c3fdeb..47b60b1a7226 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -37,10 +36,6 @@ struct mtk_mipi_tx { }; =20 struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw); -void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 b= its); -void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bit= s); -void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 = mask, - u32 data); int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, --=20 2.18.0