From nobody Sat Sep 21 15:35:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE57C54EE9 for ; Tue, 20 Sep 2022 09:05:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230100AbiITJFB (ORCPT ); Tue, 20 Sep 2022 05:05:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231774AbiITJD6 (ORCPT ); Tue, 20 Sep 2022 05:03:58 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7AA86C76F for ; Tue, 20 Sep 2022 02:02:34 -0700 (PDT) X-UUID: 5bf0666eaf024ba2a187176927e2122f-20220920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DSDkL3C2Mq/F4dBnTwYM0dQ/Ae/qiUFXxaV42IGqGBU=; b=U/DDjU1hNrauJLMOGkHDJl26SZNAmSQOMh61ezq6kv2bv3pWHMd0+Nckdbw+8fpt8IiwqDl00CIod834FAicIiohhU7Zf+UbIDEA/AUDAYHiha0bfuXTNcLiV9UsRTMnD6jQjkebNBdkIA3Q4unQ7ftalfayUwzoLQAfKUx0GyI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:ae6966af-1144-42e2-bd5c-27e0ad613d26,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:ae6966af-1144-42e2-bd5c-27e0ad613d26,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:b9d26670-dafa-4a42-b716-cf2cd4845592,B ulkID:2209201702278B2SDHZB,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 5bf0666eaf024ba2a187176927e2122f-20220920 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1399201135; Tue, 20 Sep 2022 17:02:26 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 17:00:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Sep 2022 17:00:49 +0800 From: Chunfeng Yun To: Chun-Kuang Hu , Vinod Koul CC: Philipp Zabel , Chunfeng Yun , Kishon Vijay Abraham I , Matthias Brugger , , , , , , Jitao Shi , Stanley Chu Subject: [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Date: Tue, 20 Sep 2022 17:00:32 +0800 Message-ID: <20220920090038.15133-13-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com> References: <20220920090038.15133-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove private register access helpers, use the common ones instead. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-hdmi.c | 33 ----------------------------- drivers/phy/mediatek/phy-mtk-hdmi.h | 7 ------ 2 files changed, 40 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy= -mtk-hdmi.c index d4bd419abc3c..b16d437d6721 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops =3D { .owner =3D THIS_MODULE, }; =20 -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg =3D hdmi_phy->regs + offset; - u32 tmp; - - tmp =3D readl(reg); - tmp &=3D ~bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg =3D hdmi_phy->regs + offset; - u32 tmp; - - tmp =3D readl(reg); - tmp |=3D bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask) -{ - void __iomem *reg =3D hdmi_phy->regs + offset; - u32 tmp; - - tmp =3D readl(reg); - tmp =3D (tmp & ~mask) | (val & mask); - writel(tmp, reg); -} - inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw) { return container_of(hw, struct mtk_hdmi_phy, pll_hw); diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy= -mtk-hdmi.h index dcf9bb13699b..c7fa65cff989 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -42,12 +41,6 @@ struct mtk_hdmi_phy { unsigned int ibias_up; }; =20 -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask); struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); =20 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; --=20 2.18.0