From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0349FC6FA92 for ; Mon, 19 Sep 2022 15:14:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229815AbiISPOB (ORCPT ); Mon, 19 Sep 2022 11:14:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229731AbiISPNx (ORCPT ); Mon, 19 Sep 2022 11:13:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15DDC3057E; Mon, 19 Sep 2022 08:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600429; x=1695136429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PEAr6TVpDp2c/6ZQZm9V8R/nrF0G8eQ7kqrLgzUvUe8=; b=BDog0Chh/rBWVP/ynWEjshO2o7xY+i8jhSrNM/snGfl3vQ5b2L4JtYzX WC2dLh2vKhnUfpMg47y/WcalvZutTV3/viMLKMv54cdD7PDkJnGOSl1N6 Y80Nl4sCv+L54D3i+fGM5hkT3T/dgKMdjlzYbgrN5I3WLK0xgS82yz0AB aMTSPMSNd5hZSnMlPfDQBf1xSuEa16IStBUuds+0hXlXmxoqLkkJVl2Wg /fyrhN+FMmkFLWm2RAxfH3uSZaCmwswRWFdd1yBVO3DzSoNcND0jAdgu0 yac6D6zGZS8zE8sRJAiweDjLU0Ixjqw2tSE2WYkN6gPpWXpR4dND7+FsF A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="181106628" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:13:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:43 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:39 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Date: Mon, 19 Sep 2022 18:08:39 +0300 Message-ID: <20220919150846.1148783-2-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Another functionality of FLEXCOM is that of SPI. In order for the proper validation of the SPI children nodes through the binding to occur, the proper binding for SPI must be referenced. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - use full schema paths v2 -> v3: - Added Reviewed-by tag, previously this was [PATCH 3] v3 -> v4: - Nothing, previously this was [PATCH 5] .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.ya= ml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0c80f4e98c54..f283cfd84b2d 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -78,10 +78,9 @@ patternProperties: of USART bindings. =20 "^spi@[0-9a-f]+$": - type: object + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: - Child node describing SPI. See ../spi/spi_atmel.txt for details - of SPI bindings. + Child node describing SPI. =20 "^i2c@[0-9a-f]+$": $ref: /schemas/i2c/atmel,at91sam-i2c.yaml --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6E97C6FA90 for ; Mon, 19 Sep 2022 15:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiISPOG (ORCPT ); Mon, 19 Sep 2022 11:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229745AbiISPN6 (ORCPT ); Mon, 19 Sep 2022 11:13:58 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 087CE31DCA; Mon, 19 Sep 2022 08:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600431; x=1695136431; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OzBsRUW8Q65tS0yFFfPIEZ1BvKdRKTYYU9GFDi0HUKw=; b=DT+TQSsuKUFGZxcifxhpG5wChlWL3gE5iM7SKEkRCsXrxgL+t+J0tZxS vR0grKZyEuQ01ciO3Nmmq7X4ZSYlvBQiyWiaxMI6xBAZeCNBp18vEIpYb abjKwFzArH/FyF2CvbYhDMEuxTvbeeSKCVVEFBif1KoaLpES1r6WAfBO1 q5wxvsb8VcnxRHm+fqWdm4eYxW2MyOUMkLPxb1NPe1biEWgjDiB13aLqR FUvpr4fXC4VFO311p1J7YsNE0nJ4N2q/PZZ/2lPmnuxppkt6E2NtwU61X QDI8zqZ6Ggw63538x+crGwI7X4vnrWwbVPHGc1jnipBExv6cCECg1SToA g==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="181106638" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:13:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:48 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:44 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Date: Mon, 19 Sep 2022 18:08:40 +0300 Message-ID: <20220919150846.1148783-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert at91 USART DT Binding for Atmel/Microchip SoCs to json-schema format. Furthermore, move this binding to the serial directory, since binding directories match hardware, unlike the driver subsystems which match Linux convention. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - only do what the commit says, split the addition of other compatibles and properties in other patches - remove unnecessary "|"'s - mention header in `atmel,usart-mode`'s description - place `if:` under `allOf:` - respect order of spi0's DT properties: compatible, then reg then the rese= t of properties v2 -> v3: - Previously [PATCH 5] - Check value of `atmel,usart-mode` instead of the node regex - Define all properties top level and disallow them explicitly for other ty= pe, since additionalProperties:false conflicts with referencing other schemas - Remove useless else if: after else: v3 -> v4: - add R-b tag, this was previously [PATCH 6] .../devicetree/bindings/mfd/atmel-usart.txt | 98 ---------- .../bindings/serial/atmel,at91-usart.yaml | 182 ++++++++++++++++++ 2 files changed, 182 insertions(+), 98 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usa= rt.yaml diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Docume= ntation/devicetree/bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066aff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be (found in dt-bindings/m= fd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/D= CD line respectively. - It will use specified PIO instead of the peripheral function pin for the= USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store fo= r FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: s= ee rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible =3D "atmel,at91sam9260-usart"; - reg =3D <0xfff8c000 0x4000>; - interrupts =3D <7>; - clocks =3D <&usart0_clk>; - clock-names =3D "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios =3D <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios =3D <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios =3D <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios =3D <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios =3D <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios =3D <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible =3D "atmel,at91sam9260-usart"; - reg =3D <0xf001c000 0x100>; - interrupts =3D <12 4 5>; - clocks =3D <&usart0_clk>; - clock-names =3D "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas =3D <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names =3D "tx", "rx"; - atmel,fifo-size =3D <32>; - }; - -- SPI mode: - #include - - spi0: spi@f001c000 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode =3D ; - reg =3D <0xf001c000 0x100>; - interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks =3D <&usart0_clk>; - clock-names =3D "usart"; - dmas =3D <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names =3D "tx", "rx"; - cs-gpios =3D <&pioB 3 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 000000000000..bb1b5ed431f7 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USAR= T) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + const: usart + + clocks: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either for SPI or + for USART (found in dt-bindings/mfd/at91-us= art.h). + enum: [ 0, 1 ] + + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - atmel,usart-mode + +allOf: + - if: + properties: + atmel,usart-mode: + const: 1 + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,use-dma-rx: false + + atmel,use-dma-tx: false + + atmel,fifo-size: false + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - "#size-cells" + - "#address-cells" + + else: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible =3D "atmel,at91sam9260-usart"; + reg =3D <0xfff8c000 0x4000>; + atmel,usart-mode =3D ; + interrupts =3D <7>; + clocks =3D <&usart0_clk>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios =3D <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios =3D <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios =3D <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios =3D <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios =3D <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios =3D <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible =3D "atmel,at91sam9260-usart"; + reg =3D <0xf001c000 0x100>; + atmel,usart-mode =3D ; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks =3D <&usart0_clk>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas =3D <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASA= P)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + compatible =3D "atmel,at91sam9260-usart"; + reg =3D <0xf001c000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,usart-mode =3D ; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks =3D <&usart0_clk>; + clock-names =3D "usart"; + dmas =3D <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASA= P)>; + dma-names =3D "tx", "rx"; + cs-gpios =3D <&pioB 3 GPIO_ACTIVE_HIGH>; + }; --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D871ECAAD3 for ; Mon, 19 Sep 2022 15:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbiISPOK (ORCPT ); Mon, 19 Sep 2022 11:14:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbiISPN7 (ORCPT ); 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19 Sep 2022 08:13:55 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:52 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:48 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Date: Mon, 19 Sep 2022 18:08:41 +0300 Message-ID: <20220919150846.1148783-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Require SAM9260 fallback compatible for SAM9X60, because SAM9X60 is fully compatible with SAM9260 and Linux driver requires the latter. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Use the commit message suggested by Krzysztof Kozlowski v3 -> v4: - add A-b tag, this was previously [PATCH 7] Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index bb1b5ed431f7..4da642763bef 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,8 @@ properties: - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart =20 reg: maxItems: 1 --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43AA6C54EE9 for ; Mon, 19 Sep 2022 15:14:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229555AbiISPOP (ORCPT ); Mon, 19 Sep 2022 11:14:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229728AbiISPN7 (ORCPT ); Mon, 19 Sep 2022 11:13:59 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F305233A13; Mon, 19 Sep 2022 08:13:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600437; x=1695136437; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VP458oCOHjqOR7JXccLy0gPNHRVK7fPlldUzn0Oe8CU=; b=bMhxVQSLrSVlYVRgTatR+RcIL6+C7iJ+fq3zYBAKwMLv/Er/wzGuKFjA R9xCISIh/VQBbJipECQXsgfTXycD13b8YpzM7vW0+SmhQSjrvTGukAFxR RhFfuIl4MLHG2cJet0rwEu9NwG2B5EJFg7Pd1apdUW8/5gp1TufAjWKrV XLsHUerz+CoCNpBJ95DDxNfI2k/0746RFqIdWfrMWWWYk5iGH+KlsrRcU i4FMtIZlC+HXhT/WgYMuYFWWps3R3EJqN+xTccjqASKVNmc+taqtjG5XP 3ofWDJPDj1ZwrKnPUtixDtwq7eYgtBVsoVM73D68lg2XSTaRvgQoBZkcv A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="181106681" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:13:56 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:56 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:52 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Date: Mon, 19 Sep 2022 18:08:42 +0300 Message-ID: <20220919150846.1148783-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the compatible string. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing v2 -> v3: - Previously [PATCH 7] - Compare devices based on the compatible instead of the clock v3 -> v4: - add A-b tag, this was previously [PATCH 8] .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.ya= ml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index f283cfd84b2d..0ebe624c2d32 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,21 @@ properties: =20 patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: /schemas/serial/atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. =20 "^spi@[0-9a-f]+$": - $ref: /schemas/spi/atmel,at91rm9200-spi.yaml + allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-usart + then: + $ref: /schemas/serial/atmel,at91-usart.yaml + else: + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. =20 --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F853C54EE9 for ; Mon, 19 Sep 2022 15:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbiISPOb (ORCPT ); Mon, 19 Sep 2022 11:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229761AbiISPOD (ORCPT ); Mon, 19 Sep 2022 11:14:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ABDC3137B; Mon, 19 Sep 2022 08:14:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600442; x=1695136442; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LWPKpBW+FzEpHyrvfDs1eab0UJz+OP3Fs1bFiL2379w=; b=j1nNvczXnh2DBDm880EHlSFmrtezFsEOfcmRu/hXkGGaw3cYptXijBLr 2KbcgX1r5COyB9HB54mV+1kI0kx0o3yLZU199RaVxiIbkkpkjyiAEYjIu GbqDKuo14I9ZQsv/GkDxrUQ1+14/Et8aJTjL1iIeYTmbG98GcwIXSKsw1 Oivszgn8BoCOG995JfIhMlMzETkjJUNGCawc4VG+vE5W7TuhkApI4A5kG fOAiS0YvBUbs96TPkZMHs/A7cIxDFHmZcqizYKOP18l4Bm36bH2P1zZ2G YNxtWkyhyIu4JUOy4Q9Jaf+zwfsdxCYCF/6zGUdqafgi4PpLMebJUvrFm A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="177851583" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:01 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:00 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:56 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Date: Mon, 19 Sep 2022 18:08:43 +0300 Message-ID: <20220919150846.1148783-6-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Devicetree nodes for FLEXCOM's USART can also have an alternative clock source for the baudrate generator (other than the peripheral clock), namely the Generick Clock. Thus make the binding aware of this clock that someone may place in the clock related properties of the USART node. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, Previously this was [PATCH 13] v3 -> v4: - Add A-b tag, this was previously [PATCH 9] .../devicetree/bindings/serial/atmel,at91-usart.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 4da642763bef..30b2131b5860 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -36,10 +36,16 @@ properties: maxItems: 1 =20 clock-names: - const: usart + minItems: 1 + items: + - const: usart + - const: gclk =20 clocks: - maxItems: 1 + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock =20 dmas: items: --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58BA2C54EE9 for ; Mon, 19 Sep 2022 15:14:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229946AbiISPOi (ORCPT ); Mon, 19 Sep 2022 11:14:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229895AbiISPO1 (ORCPT ); Mon, 19 Sep 2022 11:14:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2A2233E24; Mon, 19 Sep 2022 08:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600447; x=1695136447; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I4gMGo2tfk/2mg9vrlwrTzCDmtNMbNJml/dUvNSNDZ4=; b=kG5tYkjCHpb3mDSOy7xoLpe00U1KIXBXZGx+m2tYIe/81C2uXZtAANgB trV5XIEL7JLdNQJKlqTmB+HM31fGRxsw93MBJ6A5z64YCzWg5QtAQSAyT +VuOvh0bzoQXw/QNC1DzHIE+0ctlzLLONhaX8I9XKIRDjKuBNa8yB7ms3 Et+kaOacBXPUfOREkLvJIW0YrxmJNj/uBjZDGIGpsDBucD/+ynfnM5kob bgSt4O9rYkQaXKIu/blECeN4V7RGo6gepFCWQ9d+zyUrjBWmSpQDmyi5l MpFrUP4Q7XSMhmONeTLPl9+LQc22ki2/nrxzj2n2agDXh5PALIxNn3eLU Q==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="180993026" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:04 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:01 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock Date: Mon, 19 Sep 2022 18:08:44 +0300 Message-ID: <20220919150846.1148783-7-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define the bit that represents the choice of having GCLK as a baudrate source clock inside the USCLKS bitmask of the Mode Register of USART IP's. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing v3 -> v4: - Nothing, this was previously [PATCH 10] drivers/tty/serial/atmel_serial.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_s= erial.h index 0d8a0f9cc5c3..70d0611e56fd 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -49,6 +49,7 @@ #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_GCLK (2 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ #define ATMEL_US_CHRL_5 (0 << 6) --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDE26C6FA91 for ; Mon, 19 Sep 2022 15:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229935AbiISPO4 (ORCPT ); Mon, 19 Sep 2022 11:14:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbiISPOa (ORCPT ); Mon, 19 Sep 2022 11:14:30 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68ABE356E9; Mon, 19 Sep 2022 08:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600453; x=1695136453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9l85M5Mmw+iMAkBceErn0IPu5335FhxC7YxeDPx3hLA=; b=iAMrjHpJcHEGSHviZERNBWQaf6IoSPLI8M8AiLHs/Bdyf4H2sf4XzWSe xCRfvapbEOHVSbHpMZYOlowVQ0w5DfZ37JN7TACwJjMULhxGTSNiwuyJs BueZjamDv8c7Fc34gMenklvlBxBeTc2OMTMrqbn3XxGvDn2kBUNg0I4yv Xn9ZlSQm7+d1agSmPveXPJqH+ZbT2FefhmY4mWT9/qrmCAbl8Iq7leak0 ljep3wWiuVAOos5lGFyFveJTCrtrQGi2w9xbu+Cjg09gRXG+nBdSXgWli 2jF90D8V2/TVUC0YA8/wlmFfIMlls3Th5120DUj31A8FV7CGdnu92AX5P A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="177851613" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:12 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:08 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:05 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register Date: Mon, 19 Sep 2022 18:08:45 +0300 Message-ID: <20220919150846.1148783-8-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add definitions for the Baud Rate Source Clock bitmask of the Mode Register of UART IP's and its bitfields. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, previously this was [PATCH 9] V3 -> v4: - Nothing, this was previously [PATCH 11] drivers/tty/serial/atmel_serial.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_s= erial.h index 70d0611e56fd..ed64035ba6c3 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -68,6 +68,9 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK GENMASK(13, 12) /* Clock Selection for UART */ +#define ATMEL_UA_BRSRCCK_PERIPH_CLK (0 << 12) +#define ATMEL_UA_BRSRCCK_GCLK (1 << 12) #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64947C54EE9 for ; Mon, 19 Sep 2022 15:15:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229890AbiISPPB (ORCPT ); Mon, 19 Sep 2022 11:15:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229887AbiISPOd (ORCPT ); Mon, 19 Sep 2022 11:14:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0ADE356FA; Mon, 19 Sep 2022 08:14:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600455; x=1695136455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZdF5SM4cO4qp59VQ1wleOscxihQfsANgHden/vCDiF4=; b=MmgsBaIzaLoN02eMZ7PgukOVFm3mNw+YdGrmjmCr6NpttSxexYQscSmP bkWeAzBAdGLlCWCgcIg+Dstep2H69XBJwfezFVufLYoU8GET5BueqLvMH FBpOsu5eQVFdb8CI8+yrR4mxHVrB7Jr30U0IS4l9QHp8BBc/jyCzaKDlT +6MgsFLWh9I+TdOOTJ4j7nVltaTAdeQcCzsyQQoFCAkQQoYDrzNqgU2kf zSse+tX8Ywnxza6fdQXa0HZ9pYO7Bdm1rFDoc5GA2RbBb0HL210BCT+0m FlJeonOuxZteJX9lGUyMmK20RtyZYuBaPV0OmtKjNxC3oNN0fkEHuzbJ9 g==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="114368344" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:14 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:13 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:09 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 8/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Date: Mon, 19 Sep 2022 18:08:46 +0300 Message-ID: <20220919150846.1148783-9-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make sure that the driver only divides the clock divisor if the IP handled at that point is USART, since UART IP's do not support implicit peripheral clock division. Instead, in the case of UART, go with the highest possible clock divisor. Signed-off-by: Sergiu Moga Reviewed-by: Ilpo J=C3=A4rvinen --- v1 -> v2: - Nothing, this patch was not here before and is mainly meant as both clean= up and as a way to introduce a new field into struct atmel_uart_port that will= be used by the last patch to diferentiate between USART and UART regarding the location of the Baudrate Clock Source bitmask. v2 -> v3: - Use ATMEL_US_CD instead of 65535 - Previously [PATCH 10] v3 -> v4: - Use min_t instead of & - Previously [PATCH 12] drivers/tty/serial/atmel_serial.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_s= erial.c index ab4a9dfae07d..c983798a4ab2 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -150,6 +150,7 @@ struct atmel_uart_port { u32 rts_low; bool ms_irq_enabled; u32 rtor; /* address of receiver timeout register if it exists */ + bool is_usart; bool has_frac_baudrate; bool has_hw_timer; struct timer_list uart_timer; @@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port) */ atmel_port->has_frac_baudrate =3D false; atmel_port->has_hw_timer =3D false; + atmel_port->is_usart =3D false; =20 if (name =3D=3D new_uart) { dev_dbg(port->dev, "Uart with hw timer"); @@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "Usart\n"); atmel_port->has_frac_baudrate =3D true; atmel_port->has_hw_timer =3D true; + atmel_port->is_usart =3D true; atmel_port->rtor =3D ATMEL_US_RTOR; version =3D atmel_uart_readl(port, ATMEL_US_VERSION); switch (version) { @@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "This version is usart\n"); atmel_port->has_frac_baudrate =3D true; atmel_port->has_hw_timer =3D true; + atmel_port->is_usart =3D true; atmel_port->rtor =3D ATMEL_US_RTOR; break; case 0x203: @@ -2283,10 +2287,21 @@ static void atmel_set_termios(struct uart_port *por= t, cd =3D uart_get_divisor(port, baud); } =20 - if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ + /* + * If the current value of the Clock Divisor surpasses the 16 bit + * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral + * Clock implicitly divided by 8. + * If the IP is UART however, keep the highest possible value for + * the CD and avoid needless division of CD, since UART IP's do not + * support implicit division of the Peripheral Clock. + */ + if (atmel_port->is_usart && cd > ATMEL_US_CD) { cd /=3D 8; mode |=3D ATMEL_US_USCLKS_MCK_DIV8; + } else { + cd =3D min_t(unsigned int, cd, ATMEL_US_CD); } + quot =3D cd | fp << ATMEL_US_FP_OFFSET; =20 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) --=20 2.34.1 From nobody Thu Apr 2 23:18:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6473EC54EE9 for ; Mon, 19 Sep 2022 15:15:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229948AbiISPPL (ORCPT ); Mon, 19 Sep 2022 11:15:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbiISPOr (ORCPT ); Mon, 19 Sep 2022 11:14:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20245357D8; Mon, 19 Sep 2022 08:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600460; x=1695136460; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c870c32AhfgZVg4pwd9ZMePlL4mjnVCOQA4N7lzg7uk=; b=k60+i5P5Mqyl8vfrc1i+E1GdVv6KyNK+2bguKeMU95I3ACooU2eHHgkd U2FUrfHj+dkYm7W3mLRABpD/Mh8XRGgIjtbUYeOeQ/9JE+fIXcVb8GVT4 Fw/qzGqFNIy4KlA7VSJLqXIw614mloVUq6kmbaF19zFcqTK7vl8E5Pnh0 JQqijtCIUzB/+YLNky7fiYYPepD2z2cKyZvIk/9YrZDbwXfGWHeQ9oTx8 TfthvTR+nY/ysH1UYups6CpvsO21qmDUFW8wK5/ofYzR3iR3kojrtNfIs 54jLBMeF2SFzhvrz8gRZsiDcn65t13Wv+0ZKkFXxjB65sMCa5IoatevgV w==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="114368422" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:17 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:13 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 9/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Mon, 19 Sep 2022 18:08:47 +0300 Message-ID: <20220919150846.1148783-10-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - take into account the different placement of the baudrate clock source into the IP's Mode Register (USART vs UART) - don't check for atmel_port->gclk !=3D NULL - use clk_round_rate instead of clk_set_rate + clk_get_rate - remove clk_disable_unprepare from the end of the probe method v2 -> v3: - add the error rate calculation function as an inline function instead of a macro definition - add `gclk_fail` goto - replace `goto err` with `goto err_clk_disable_unprepare;` v3 -> v4: - Nothing, this was previously [PATCH 14] drivers/tty/serial/atmel_serial.c | 59 ++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_s= erial.c index c983798a4ab2..426f9d4f9a5a 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need = to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uar= t_port *port) (port->iso7816.flags & SER_ISO7816_ENABLED); } =20 +static inline int atmel_error_rate(int desired_value, int actual_value) +{ + return 100 - (desired_value * 100) / actual_value; +} + #ifdef CONFIG_SERIAL_ATMEL_PDC static bool atmel_use_pdc_rx(struct uart_port *port) { @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, u= nsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port, { struct atmel_uart_port *atmel_port =3D to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp =3D 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp =3D 0; + unsigned int baud, actual_baud, gclk_rate; + int ret; =20 /* save the current mode register */ mode =3D old_mode =3D atmel_uart_readl(port, ATMEL_US_MR); @@ -2302,6 +2313,46 @@ static void atmel_set_termios(struct uart_port *port, cd =3D min_t(unsigned int, cd, ATMEL_US_CD); } =20 + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!atmel_port->has_frac_baudrate) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + gclk_rate =3D clk_round_rate(atmel_port->gclk, 16 * baud); + actual_baud =3D clk_get_rate(atmel_port->clk) / (16 * cd); + if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) > + abs(atmel_error_rate(baud, gclk_rate / 16))) { + clk_set_rate(atmel_port->gclk, 16 * baud); + ret =3D clk_prepare_enable(atmel_port->gclk); + if (ret) + goto gclk_fail; + + if (atmel_port->is_usart) { + mode &=3D ~ATMEL_US_USCLKS; + mode |=3D ATMEL_US_USCLKS_GCLK; + } else { + mode &=3D ~ATMEL_UA_BRSRCCK; + mode |=3D ATMEL_UA_BRSRCCK_GCLK; + } + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd =3D 1; + } + } + +gclk_fail: quot =3D cd | fp << ATMEL_US_FP_OFFSET; =20 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2897,6 +2948,12 @@ static int atmel_serial_probe(struct platform_device= *pdev) if (ret) goto err; =20 + atmel_port->gclk =3D devm_clk_get_optional(&pdev->dev, "gclk"); + if (IS_ERR(atmel_port->gclk)) { + ret =3D PTR_ERR(atmel_port->gclk); + goto err_clk_disable_unprepare; + } + ret =3D atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare; --=20 2.34.1