From nobody Sat Sep 21 14:45:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E485ECAAD3 for ; Mon, 19 Sep 2022 08:49:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230103AbiISItA (ORCPT ); Mon, 19 Sep 2022 04:49:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbiISIsh (ORCPT ); Mon, 19 Sep 2022 04:48:37 -0400 Received: from mail.base45.de (mail.base45.de [80.241.60.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACAA522507; Mon, 19 Sep 2022 01:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=fe80.eu; s=20190804; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=vmMH+fMWlszjT3xrI6x6BPzn+VWGtlXNR874DKMXudU=; b=ipUxJbFlUFRufa+84syKI7F1af i9V6OGsjDZMWWimDJX0P00pjoiHYV2ryVuCmFqXXvCl2GCUecYTS27u+4liVMjv/L4FVVeLp1GQtf H6gCrZ4z46C/0exl8LN6qV2cTocNVCvT9U0v9E3NpDXkO6k6ajcVPXqQMGADwgLhEKp5GPFS7Xg4J nRYuqvV1HB7heRLXqPmhHSzRvsklzf3SJ8/Mi1/H1RKaAotTSN+8+skesrGEOmkK81ef9gMWCEDcI TsNdnAWI5B8pfU5SxIu5WMhwh1XDPFPmlQnx0qMNyW6ZsZ82bIQA+omKg0zopbMTq5IOFAQ6W5Xqz Lf1Ooj7Q==; Received: from dynamic-089-204-138-189.89.204.138.pool.telefonica.de ([89.204.138.189] helo=localhost.localdomain) by mail.base45.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oaCHJ-0015f0-Hu; Mon, 19 Sep 2022 08:37:21 +0000 From: Alexander Couzens To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger Cc: Daniel Golle , Alexander Couzens , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 1/5] net: mediatek: sgmii: fix powering up the SGMII phy Date: Mon, 19 Sep 2022 10:37:08 +0200 Message-Id: <20220919083713.730512-2-lynxis@fe80.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220919083713.730512-1-lynxis@fe80.eu> References: <20220919083713.730512-1-lynxis@fe80.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are cases when the SGMII_PHYA_PWD register contains 0x9 which prevents SGMII from working. The SGMII still shows link but no traffic can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was taken from a good working state of the SGMII interface. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 25 ++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index 736839c84130..b9b15e1a292c 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -36,9 +36,15 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) val |=3D SGMII_AN_RESTART; regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); =20 - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &=3D ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + /* Release PHYA power down state + * Only removing bit SGMII_PHYA_PWD isn't enough. + * There are cases when the SGMII_PHYA_PWD register contains 0x9 which + * prevents SGMII from working. The SGMII still shows link but no traffic + * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was + * taken from a good working state of the SGMII interface. + * Tested on mt7622 & mt7986. + */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); =20 return 0; =20 @@ -69,10 +75,15 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpc= s, val |=3D SGMII_SPEED_1000; regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); =20 - /* Release PHYA power down state */ - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &=3D ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + /* Release PHYA power down state + * Only removing bit SGMII_PHYA_PWD isn't enough. + * There are cases when the SGMII_PHYA_PWD register contains 0x9 which + * prevents SGMII from working. The SGMII still shows link but no traffic + * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was + * taken from a good working state of the SGMII interface. + * Tested on mt7622 & mt7986. + */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); =20 return 0; } --=20 2.37.3 From nobody Sat Sep 21 14:45:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDC9BC54EE9 for ; Mon, 19 Sep 2022 08:48:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230112AbiISIsw (ORCPT ); Mon, 19 Sep 2022 04:48:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbiISIsh (ORCPT ); Mon, 19 Sep 2022 04:48:37 -0400 Received: from mail.base45.de (mail.base45.de [80.241.60.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7F8BBE36; Mon, 19 Sep 2022 01:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=fe80.eu; s=20190804; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=1DACBHOF6bWkOkqzEWq59C2Rno8KqMCb78TJcrYbS/U=; b=djnNEqg5MEYCs/Rn/KVZvcU6LU JBoNaHs5fAcwEVraya2ifpOQqK+exVqSGwjI+ULSNsoQm7P2BX7VW7WHQEWSoqsoiT9nw/ZxamE1N iwYqc4jluf6yNZDjGraFCQ2v/MZzzYNjaAEFCQYgtZ5DuMp54i4DbObQB2xbea7CxAYoRDjEpJUqg 0W985cHB4hScOyyFkeg0ZBjuMV+SCNAX41mqpr3Nr1KHadgud8HgLtJUWmlmXt2/E0JKM6ICa5AdV Qy/A+7hvSmRiLEIaF6G0EuthkO38X4LmMsq77f6z4xZ1U4LUKAhDu4gDQGDgejCoVdYBOLzVhxN4+ CVQ4R2lA==; Received: from dynamic-089-204-138-189.89.204.138.pool.telefonica.de ([89.204.138.189] helo=localhost.localdomain) by mail.base45.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oaCHK-0015f0-MQ; Mon, 19 Sep 2022 08:37:22 +0000 From: Alexander Couzens To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger Cc: Daniel Golle , Alexander Couzens , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 2/5] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration Date: Mon, 19 Sep 2022 10:37:09 +0200 Message-Id: <20220919083713.730512-3-lynxis@fe80.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220919083713.730512-1-lynxis@fe80.eu> References: <20220919083713.730512-1-lynxis@fe80.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The code expect the PHY to be in power down which is only true after reset. Allow changes of the SGMII parameters more than once. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index b9b15e1a292c..18de85709e87 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -7,6 +7,7 @@ * */ =20 +#include #include #include #include @@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) { unsigned int val; =20 + /* PHYA power down */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); + /* Setup the link timer and QPHY power up inside SGMIISYS */ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, SGMII_LINK_TIMER_DEFAULT); @@ -42,8 +46,10 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) * prevents SGMII from working. The SGMII still shows link but no traffic * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was * taken from a good working state of the SGMII interface. + * Unknown how much the QPHY needs but it is racy without a sleep. * Tested on mt7622 & mt7986. */ + usleep_range(50, 100); regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); =20 return 0; @@ -58,6 +64,9 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, { unsigned int val; =20 + /* PHYA power down */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); val &=3D ~RG_PHY_SPEED_MASK; if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) @@ -81,8 +90,10 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, * prevents SGMII from working. The SGMII still shows link but no traffic * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was * taken from a good working state of the SGMII interface. + * Unknown how much the QPHY needs but it is racy without a sleep. * Tested on mt7622 & mt7986. */ + usleep_range(50, 100); regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); =20 return 0; --=20 2.37.3 From nobody Sat Sep 21 14:45:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B14ECAAD3 for ; Mon, 19 Sep 2022 08:48:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230119AbiISIs5 (ORCPT ); Mon, 19 Sep 2022 04:48:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbiISIsh (ORCPT ); Mon, 19 Sep 2022 04:48:37 -0400 Received: from mail.base45.de (mail.base45.de [80.241.60.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3E622503; Mon, 19 Sep 2022 01:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=fe80.eu; s=20190804; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=dT1y+29LfGYYXr/kgVW5snS+ww+Guphm3qcxKvTGRM4=; b=WghFA2VplecHWY3tR2poQdmoj7 l1v/yX0/m76QpmmFOXecuePay3hY6lrWOuB8J3u8hIX4Al0nUZPRFvxUi0k8qI48OeZNEVUZE4HDg tm11LZGt5teydPJmAIJ25pakjd1K4p5xjpyMaAgjjUCTXn1dEIV63TctkqOvp2Ny9j0sqbCjVYeac 88/9jqkeNxewWNU7f9P+T0s9+vsiYbJVz3zIGBz542guXLaSXkJAxwRFkbcZFCh6O8obMJ1TSt2Mp MkUG4BN+m1Q0VuL0FxDIFC6o01+VAN/NAZGfsucw20DhDdhNxmp957paXgIvngVBHrguhj9OkUrqa hFJ3ddpA==; Received: from dynamic-089-204-138-189.89.204.138.pool.telefonica.de ([89.204.138.189] helo=localhost.localdomain) by mail.base45.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oaCHL-0015f0-Pe; Mon, 19 Sep 2022 08:37:23 +0000 From: Alexander Couzens To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger Cc: Daniel Golle , Alexander Couzens , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 3/5] net: mediatek: sgmii: mtk_pcs_setup_mode_an: don't rely on register defaults Date: Mon, 19 Sep 2022 10:37:10 +0200 Message-Id: <20220919083713.730512-4-lynxis@fe80.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220919083713.730512-1-lynxis@fe80.eu> References: <20220919083713.730512-1-lynxis@fe80.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Ensure autonegotiation is enabled. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index 18de85709e87..6f4c1ca5a36f 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -32,12 +32,13 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, SGMII_LINK_TIMER_DEFAULT); =20 + /* disable remote fault & enable auto neg */ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); - val |=3D SGMII_REMOTE_FAULT_DIS; + val |=3D SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN; regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); =20 regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); - val |=3D SGMII_AN_RESTART; + val |=3D SGMII_AN_RESTART | SGMII_AN_ENABLE; regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); =20 /* Release PHYA power down state --=20 2.37.3 From nobody Sat Sep 21 14:45:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6B78C6FA82 for ; Mon, 19 Sep 2022 08:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbiISIvn (ORCPT ); Mon, 19 Sep 2022 04:51:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbiISIvV (ORCPT ); Mon, 19 Sep 2022 04:51:21 -0400 Received: from mail.base45.de (mail.base45.de [80.241.60.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C67B12638; Mon, 19 Sep 2022 01:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=fe80.eu; s=20190804; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=QBCl0pfQcWqm7TdLuZxzEDBy56PZexf/QrFrNulelxc=; b=ZMB80DSusgcxYXocGFwCxmOfCY 2NtV1oKiF537zlxG0wWTs+860QIo5U0pA0AkmbVXaJZWYBY38CcGJPJVlB5mrPeNUMp/BQT+ttGPk 2hSSxpv+VMBLyhb9lpQqGWdPSSUAbV+PCw5Ggc06csB+7wcFbjdEN4ujHupPVTpQ15bcQsUuJ58N0 uprm4A4USMNqb/LlSIUWrXeIQgAz8e5sYcoDGIL6VdjIuMpI/fNa0Kry4NHeudfIgfCN25bHFuIhM TZcOYbqPWldjgursAaeEzDb7L+FXwWjvFTbc+FVg9GGgSqYfLet4t9J/jI8Lqtq0AsN8BtnHwMc9c K6tELyYw==; Received: from dynamic-089-204-138-189.89.204.138.pool.telefonica.de ([89.204.138.189] helo=localhost.localdomain) by mail.base45.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oaCHM-0015f0-VR; Mon, 19 Sep 2022 08:37:25 +0000 From: Alexander Couzens To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , Russell King Cc: Daniel Golle , Alexander Couzens , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 4/5] net: mediatek: sgmii: set the speed according to the phy interface in AN Date: Mon, 19 Sep 2022 10:37:11 +0200 Message-Id: <20220919083713.730512-5-lynxis@fe80.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220919083713.730512-1-lynxis@fe80.eu> References: <20220919083713.730512-1-lynxis@fe80.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The non auto-negotioting code path is setting the correct speed for the interface. Ensure auto-negotiation code path is doing it as well. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index 6f4c1ca5a36f..4c8e8c7b1d32 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pc= s *pcs) } =20 /* For SGMII interface mode */ -static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) +static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t int= erface) { unsigned int val; =20 /* PHYA power down */ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); =20 + /* Set SGMII phy speed */ + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); + val &=3D ~RG_PHY_SPEED_MASK; + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val |=3D RG_PHY_SPEED_3_125G; + regmap_write(mpcs->regmap, mpcs->ana_rgc3, val); + /* Setup the link timer and QPHY power up inside SGMIISYS */ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, SGMII_LINK_TIMER_DEFAULT); @@ -112,7 +119,7 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsi= gned int mode, if (interface !=3D PHY_INTERFACE_MODE_SGMII) err =3D mtk_pcs_setup_mode_force(mpcs, interface); else if (phylink_autoneg_inband(mode)) - err =3D mtk_pcs_setup_mode_an(mpcs); + err =3D mtk_pcs_setup_mode_an(mpcs, interface); =20 return err; } --=20 2.37.3 From nobody Sat Sep 21 14:45:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF533C54EE9 for ; Mon, 19 Sep 2022 08:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230211AbiISIwK (ORCPT ); Mon, 19 Sep 2022 04:52:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230059AbiISIvd (ORCPT ); Mon, 19 Sep 2022 04:51:33 -0400 Received: from mail.base45.de (mail.base45.de [80.241.60.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99743E42; Mon, 19 Sep 2022 01:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=fe80.eu; s=20190804; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=D/qYEGwuEVapUTF3lqnvMGKfhRgLgW56QQsSQBIKfeI=; b=vA2a0mdF0n8xHi/88ZNpodKeAt ITdIozAy55N2hIAXkqZhIU9ktcn0KRiLukZZwOpdkqWwGF3rmmVZqD//uzBCsnSXzE1oEG2kxnsCC WdnxMOsc8BKLFhB9OG2z/QvrU9Q3UB9dKlKlo+zkmIPb46THOX7cGkmxfMHke+Rmt4b7RTFiKcxZu vpLwcqUnvH2viOJTGDxOxCFFR7GPQYaZbsTTmX1ggRI/QIXmIVXQhsXDgrRkGiSDAkAK6U6WKUbfH 40t+BaiVcohe0wYiUkj6qYGidrwdXHFSCnApqvH3EERYHTZw9V0rCHIfHt7inHe/6URllZAMfkuDq zjiQNmlg==; Received: from dynamic-089-204-138-189.89.204.138.pool.telefonica.de ([89.204.138.189] helo=localhost.localdomain) by mail.base45.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oaCHO-0015f0-8E; Mon, 19 Sep 2022 08:37:26 +0000 From: Alexander Couzens To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , Russell King Cc: Daniel Golle , Alexander Couzens , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 5/5] net: mediatek: sgmii: refactor power cycling into mtk_pcs_config() Date: Mon, 19 Sep 2022 10:37:12 +0200 Message-Id: <20220919083713.730512-6-lynxis@fe80.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220919083713.730512-1-lynxis@fe80.eu> References: <20220919083713.730512-1-lynxis@fe80.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Both code paths (autonegotiated and force mode) are power cycling the phy. Move power cycling code to the caller to remove code duplicity. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 45 ++++++++--------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index 4c8e8c7b1d32..50f605208295 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -25,9 +25,6 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, ph= y_interface_t interface { unsigned int val; =20 - /* PHYA power down */ - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); - /* Set SGMII phy speed */ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); val &=3D ~RG_PHY_SPEED_MASK; @@ -48,18 +45,6 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, p= hy_interface_t interface val |=3D SGMII_AN_RESTART | SGMII_AN_ENABLE; regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); =20 - /* Release PHYA power down state - * Only removing bit SGMII_PHYA_PWD isn't enough. - * There are cases when the SGMII_PHYA_PWD register contains 0x9 which - * prevents SGMII from working. The SGMII still shows link but no traffic - * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was - * taken from a good working state of the SGMII interface. - * Unknown how much the QPHY needs but it is racy without a sleep. - * Tested on mt7622 & mt7986. - */ - usleep_range(50, 100); - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); - return 0; =20 } @@ -72,9 +57,6 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, { unsigned int val; =20 - /* PHYA power down */ - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); - regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); val &=3D ~RG_PHY_SPEED_MASK; if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) @@ -92,18 +74,6 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, val |=3D SGMII_SPEED_1000; regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); =20 - /* Release PHYA power down state - * Only removing bit SGMII_PHYA_PWD isn't enough. - * There are cases when the SGMII_PHYA_PWD register contains 0x9 which - * prevents SGMII from working. The SGMII still shows link but no traffic - * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was - * taken from a good working state of the SGMII interface. - * Unknown how much the QPHY needs but it is racy without a sleep. - * Tested on mt7622 & mt7986. - */ - usleep_range(50, 100); - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); - return 0; } =20 @@ -115,12 +85,27 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, uns= igned int mode, struct mtk_pcs *mpcs =3D pcs_to_mtk_pcs(pcs); int err =3D 0; =20 + /* PHYA power down */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); + /* Setup SGMIISYS with the determined property */ if (interface !=3D PHY_INTERFACE_MODE_SGMII) err =3D mtk_pcs_setup_mode_force(mpcs, interface); else if (phylink_autoneg_inband(mode)) err =3D mtk_pcs_setup_mode_an(mpcs, interface); =20 + /* Release PHYA power down state + * Only removing bit SGMII_PHYA_PWD isn't enough. + * There are cases when the SGMII_PHYA_PWD register contains 0x9 which + * prevents SGMII from working. The SGMII still shows link but no traffic + * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was + * taken from a good working state of the SGMII interface. + * Unknown how much the QPHY needs but it is racy without a sleep. + * Tested on mt7622 & mt7986. + */ + usleep_range(50, 100); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + return err; } =20 --=20 2.37.3