From nobody Sat Sep 21 09:25:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44541C4332F for ; Mon, 28 Nov 2022 16:22:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232682AbiK1QW0 (ORCPT ); Mon, 28 Nov 2022 11:22:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232644AbiK1QVt (ORCPT ); Mon, 28 Nov 2022 11:21:49 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B435D20185 for ; Mon, 28 Nov 2022 08:21:45 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id d1so17711766wrs.12 for ; Mon, 28 Nov 2022 08:21:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dS8cQQ4bUCIGdTuiAN/aAd8jqSH5EJokFUSJdAjidPI=; b=0+jl/jbubFkfZTQZYgBADk0y7xxrO/2O6QnzOVhd0Ay2GZ3bHMfzNgrtNe26Sz8wrW x+gpWK/PWX9RuKHQi9Ch0lKr7Fd2CxuKQcJefXlOvLsbdjQbfpN81PLo5z6u6RrKZQ1/ dY0NeCNnghuCx5+smHJpKR5x43S7aUls/hwRPXFC3u/Z7e49DZ70Ni+XFVOcAUJwZU4U LbehBw0bXN9VsXSVv3+SyJrjfLxG47GWP1E1qPhVnl9qHUwRU8OrPseNT2rJvgdixZnD tix9Ry5TWNyILcL7MiL4+CyOFJc2kjHhqnjEuH53SjfWTtCwAbhBDmrA64Ain9vGGAl8 dlIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dS8cQQ4bUCIGdTuiAN/aAd8jqSH5EJokFUSJdAjidPI=; b=71RwpUm/n6Lcfn4DUmDnQWWXhjmqx+6QJNb4YAK0dmbtPfkadakdS2HWPBcanx8aM3 h78gSd4mtsWlys9wztoMrDn0HDMEzy46OyH+ngD9b0OyLQLgBNlXoU8w/iE1uNvO3QFZ Ft9QMdeZZQGEhvYuxG/z1QkhTkHPNq3DWizlkfq/Fcbs0NW+PGu/QNYCK7n78RiRxfaY suH2Uencx/eFGsfySnm0I4WGl4QOxjIFiUEailLTk6AFgQYGfVQfxfXPkuG5xbd1N1aI eBwl993DYZb/57x255AYJkQi/Nlk9g6ZlGsf2xOUC+To5itVzvJMbdphoCfZCV2AwQZH bYZA== X-Gm-Message-State: ANoB5pk67pLMR9N/N6uh73Vz/f5kmQcTB/gPMRbLvExmNXGuGvzOC/69 gtxTEBd3x23J1noKomQrH8x5JQ== X-Google-Smtp-Source: AA0mqf7zILY88KtlDUpp9lKnmVPVFaeVSYmrpe6eWbhZCXd1jcABe1SItKMY2e2rfy2bYoaSKhc5bQ== X-Received: by 2002:adf:fd01:0:b0:235:83aa:a6ed with SMTP id e1-20020adffd01000000b0023583aaa6edmr30496312wrr.543.1669652505287; Mon, 28 Nov 2022 08:21:45 -0800 (PST) Received: from [127.0.0.1] (2a02-8440-6340-f657-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6340:f657:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id s10-20020a1cf20a000000b003cfe1376f68sm15311450wmc.9.2022.11.28.08.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:21:44 -0800 (PST) From: Guillaume Ranquet Date: Mon, 28 Nov 2022 17:17:36 +0100 Subject: [PATCH v5 1/3] dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220919-v5-1-f346444bc459@baylibre.com> References: <20220919-v5-0-f346444bc459@baylibre.com> In-Reply-To: <20220919-v5-0-f346444bc459@baylibre.com> To: Chunfeng Yun , Krzysztof Kozlowski , David Airlie , Matthias Brugger , Philipp Zabel , Rob Herring , Kishon Vijay Abraham I , Daniel Vetter , Vinod Koul , Chun-Kuang Hu , CK Hu , Jitao shi Cc: mac.shen@mediatek.com, Guillaume Ranquet , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com, kernel test robot , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a compatible for the HDMI PHY on MT8195 Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Signed-off-by: Guillaume Ranquet --- Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b= /Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index 0d94950b84ca..71c75a11e189 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -28,6 +28,7 @@ properties: - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt8173-hdmi-phy + - const: mediatek,mt8195-hdmi-phy =20 reg: maxItems: 1 --=20 2.38.1 From nobody Sat Sep 21 09:25:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA1EC47089 for ; Mon, 28 Nov 2022 16:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232724AbiK1QV5 (ORCPT ); Mon, 28 Nov 2022 11:21:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232616AbiK1QVt (ORCPT ); Mon, 28 Nov 2022 11:21:49 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D74013E86 for ; Mon, 28 Nov 2022 08:21:48 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id x17so17699373wrn.6 for ; Mon, 28 Nov 2022 08:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=A0OXxX4BN+JC/Hy+vtoYftLVfMwhN/RiALx1B4QXUlc=; b=SlkrWf3SnnGDpb675mkRP6lf4nLIT1ljnSs811QXoTIpKGIr6nkO1robz4uvX+3hel emJjd5A2yCCTjR0LXKEjLdGYNb2o2zsvcHdQ1nXfW9oFv0bIePuY9EEF+wvSQ1jpJpfe uYlNtXWlsAQakgdO/rq4yHkCGTL/bSh4cUCBhsM2mfP/FtZp0bXgE/HPcGJU/oRl3i2l zPL3lW+z6Kap+h6fgLOacZBtOL/HD9TJ6ShxhljgFYgVd4/L6A/2W0q8oT/Juz8T/7qv qlVqVlXVA5+/JbXKOjRIX+Nb72oLRueixKPJUM69A14modQclXgDP110z0Dye0vX0jdJ cvZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A0OXxX4BN+JC/Hy+vtoYftLVfMwhN/RiALx1B4QXUlc=; b=0SQL6eOr1DqOtayspfAl8Ru9UjhY7v8qF/IfSUP1F5XJ/FXzZScpXl7WCVXJDaoXwB sWF8GbyCXCmeo0P+SHQ8E+cC7T09IPmftcxRkiP27jYEsIw972lmxciHi/8stdQ6ecJq /v+Fo7ICnhSD02ZFYlK2BPaPeJMY40HnkwpsPa0CNDC9rYBchmFP9qaHPjapsvsYJD4W L6loeWw61AZblM2Zn7WQtO/Ht1Ls01/Px2Wm9DkR49oTld91FXgV2wW+SCMafxrzXrHo Wd9ap+g2lJ8jyN2u9Z8cTOR3jI36V8lugjIUxWLygllmxAF4n6hyKnnqpaQqYLlmjmHv 0DfA== X-Gm-Message-State: ANoB5pkysmuRXCSeyWJttgIS3rvnkbBZRmIrz4Fw5aCMpyHhngi2Sfnq l2S1hqmT/qXyhNQ3V56iQOz5gA== X-Google-Smtp-Source: AA0mqf4mvZhMdusHlUCoDzlaITnTfcTdfTwIBg2rPiKj4l0XqNnN3xuoOOxzvyyaTx+gTn619CGt5g== X-Received: by 2002:a05:6000:128c:b0:236:e512:1a9e with SMTP id f12-20020a056000128c00b00236e5121a9emr23151843wrx.416.1669652506887; Mon, 28 Nov 2022 08:21:46 -0800 (PST) Received: from [127.0.0.1] (2a02-8440-6340-f657-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6340:f657:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id s10-20020a1cf20a000000b003cfe1376f68sm15311450wmc.9.2022.11.28.08.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:21:46 -0800 (PST) From: Guillaume Ranquet Date: Mon, 28 Nov 2022 17:17:37 +0100 Subject: [PATCH v5 2/3] phy: phy-mtk-hdmi: Add generic phy configure callback MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220919-v5-2-f346444bc459@baylibre.com> References: <20220919-v5-0-f346444bc459@baylibre.com> In-Reply-To: <20220919-v5-0-f346444bc459@baylibre.com> To: Chunfeng Yun , Krzysztof Kozlowski , David Airlie , Matthias Brugger , Philipp Zabel , Rob Herring , Kishon Vijay Abraham I , Daniel Vetter , Vinod Koul , Chun-Kuang Hu , CK Hu , Jitao shi Cc: mac.shen@mediatek.com, Guillaume Ranquet , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com, kernel test robot , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some phys, such as mt8195, needs to have a configure callback defined. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Signed-off-by: Guillaume Ranquet --- drivers/phy/mediatek/phy-mtk-hdmi.c | 12 ++++++++++++ drivers/phy/mediatek/phy-mtk-hdmi.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy= -mtk-hdmi.c index b16d437d6721..32f713301768 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -8,10 +8,12 @@ =20 static int mtk_hdmi_phy_power_on(struct phy *phy); static int mtk_hdmi_phy_power_off(struct phy *phy); +static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opt= s *opts); =20 static const struct phy_ops mtk_hdmi_phy_dev_ops =3D { .power_on =3D mtk_hdmi_phy_power_on, .power_off =3D mtk_hdmi_phy_power_off, + .configure =3D mtk_hdmi_phy_configure, .owner =3D THIS_MODULE, }; =20 @@ -43,6 +45,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy) return 0; } =20 +static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opt= s *opts) +{ + struct mtk_hdmi_phy *hdmi_phy =3D phy_get_drvdata(phy); + + if (hdmi_phy->conf->hdmi_phy_configure) + return hdmi_phy->conf->hdmi_phy_configure(phy, opts); + + return 0; +} + static const struct phy_ops * mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy) { diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy= -mtk-hdmi.h index c7fa65cff989..f5aac9d352d8 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -24,6 +24,7 @@ struct mtk_hdmi_phy_conf { const struct clk_ops *hdmi_phy_clk_ops; void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); + int (*hdmi_phy_configure)(struct phy *phy, union phy_configure_opts *opts= ); }; =20 struct mtk_hdmi_phy { --=20 2.38.1 From nobody Sat Sep 21 09:25:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEA38C4332F for ; Mon, 28 Nov 2022 16:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232627AbiK1QWU (ORCPT ); Mon, 28 Nov 2022 11:22:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232638AbiK1QVw (ORCPT ); Mon, 28 Nov 2022 11:21:52 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38DAD205E5 for ; Mon, 28 Nov 2022 08:21:50 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id x17so17699552wrn.6 for ; Mon, 28 Nov 2022 08:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xt5u9C+PfP+tQVHzS7623/aKy8QDwt4q6W0wP6jZnZE=; b=6/l2WDehMqeL3zdyRiTizi9TNCA1CLTQYa6SsTfywAngJsZnwlKeOLju+tj3oAKDvj 2BoUSe9uUB/LVPxvY9DjDaZvNJOORKEA54ZfbtNVLn+1CoE/vVNiNnoj3Kwf1NCH8+on AkI+YVT9VwCxnH/RlTR+2duf98wPy6fnxYdG10K3Q+xe6Xyw25c8XfMwdyRa4qixf330 N7GsHUmEUso6dPzr59uAzNu5hYuDxbayYqP0/IsIqDy71Dsoxkct8hmCSntPU/EnK0RN 8vgDQ7gn2Rbs29PzYnfbj1jxzB2Xs/wm/g9dpfMzcT2QhoVP1UjeBXUOir4HZNya9EZe 1VMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xt5u9C+PfP+tQVHzS7623/aKy8QDwt4q6W0wP6jZnZE=; b=53jcJXU09vNteq9q6avb5EVM+Jh6YZr/zVl2Zu2Nqej8lq5JZuKQmlr+9LS3NFThhX PsUCrvJcfpcA2eyJSr2ifUpMXewQ3Us3i5tuFZV416BoT6X0g0nEYMx8e4jI3CMPpdiz 7Qvf4eC6D0Uo7tOOlRI+TdvKConXzy3CE3CAakJ/ANA8YReJIqXKZOkR3Jf8zV025Q5l m5ZbyTW2HyHKzr0wltlK1E61U6j9KOBFAfOmcoe3qI/keISxbZHajci1NeFe7bbbqPON XBwkVoHhSshnhUO2b0lOQr7eAmM7s770Ix2nLNT3FegS0zVtZ86B63kyTXS5rdqJR35S DMtQ== X-Gm-Message-State: ANoB5pnWsvd43CLOg9aFOjUjEvLt+H9AlcsrlOzDLJ6WvobOT6sdAycv 7iC9xMkZHT/xidAz6G3TIGrlFg== X-Google-Smtp-Source: AA0mqf4k7FdKoQsza2z+wH6D/ruq3fezyAIVCGSXovvqnG2fBtndhzIBkDPmtk38EEY0X7D/oNiMWA== X-Received: by 2002:a05:6000:1181:b0:22e:53c0:ead8 with SMTP id g1-20020a056000118100b0022e53c0ead8mr32129519wrx.210.1669652508584; Mon, 28 Nov 2022 08:21:48 -0800 (PST) Received: from [127.0.0.1] (2a02-8440-6340-f657-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6340:f657:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id s10-20020a1cf20a000000b003cfe1376f68sm15311450wmc.9.2022.11.28.08.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:21:48 -0800 (PST) From: Guillaume Ranquet Date: Mon, 28 Nov 2022 17:17:38 +0100 Subject: [PATCH v5 3/3] phy: mediatek: add support for phy-mtk-hdmi-mt8195 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220919-v5-3-f346444bc459@baylibre.com> References: <20220919-v5-0-f346444bc459@baylibre.com> In-Reply-To: <20220919-v5-0-f346444bc459@baylibre.com> To: Chunfeng Yun , Krzysztof Kozlowski , David Airlie , Matthias Brugger , Philipp Zabel , Rob Herring , Kishon Vijay Abraham I , Daniel Vetter , Vinod Koul , Chun-Kuang Hu , CK Hu , Jitao shi Cc: mac.shen@mediatek.com, Guillaume Ranquet , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com, kernel test robot , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the mediatek hdmi phy on MT8195 SoC Reported-by: kernel test robot Signed-off-by: Guillaume Ranquet --- drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 527 +++++++++++++++++++++++++= ++++ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 111 ++++++ drivers/phy/mediatek/phy-mtk-hdmi.c | 3 + drivers/phy/mediatek/phy-mtk-hdmi.h | 1 + 5 files changed, 643 insertions(+) diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index fb1f8edaffa7..c9a50395533e 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_MTK_XSPHY) +=3D phy-mtk-xsphy.o phy-mtk-hdmi-drv-y :=3D phy-mtk-hdmi.o phy-mtk-hdmi-drv-y +=3D phy-mtk-hdmi-mt2701.o phy-mtk-hdmi-drv-y +=3D phy-mtk-hdmi-mt8173.o +phy-mtk-hdmi-drv-y +=3D phy-mtk-hdmi-mt8195.o obj-$(CONFIG_PHY_MTK_HDMI) +=3D phy-mtk-hdmi-drv.o =20 phy-mtk-mipi-dsi-drv-y :=3D phy-mtk-mipi-dsi.o diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c new file mode 100644 index 000000000000..822f5fa29025 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2022 BayLibre, SAS + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-mtk-io.h" +#include "phy-mtk-hdmi.h" +#include "phy-mtk-hdmi-mt8195.h" + +static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy) +{ + /* make data fifo writable for hdmi2.0 */ + mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); +} + +static void +mtk_mt8195_phy_tmds_high_bit_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, + bool enable) +{ + void __iomem *regs =3D hdmi_phy->regs; + + mtk_hdmi_ana_fifo_en(hdmi_phy); + + /* HDMI 2.0 specification, 3.4Gbps <=3D TMDS Bit Rate <=3D 6G, + * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 + */ + if (enable) + mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, REG_TXC_DIV); + else + mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); +} + +static void mtk_hdmi_pll_select_source(struct clk_hw *hw) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + void __iomem *regs =3D hdmi_phy->regs; + + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); + + /* DA_HDMITX21_REF_CK for TXPLL input source */ + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); +} + +static int mtk_hdmi_pll_performance_setting(struct clk_hw *hw) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + void __iomem *regs =3D hdmi_phy->regs; + + /* BP2 */ + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); + + /* BC */ + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC); + + /* IC */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1); + + /* BR */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2); + + /* IR */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2); + + /* BP */ + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP); + + /* IBAND_FIX_EN, RESERVE[14] */ + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); + + /* HIKVCO */ + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO); + + /* HREN */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); + + /* LVR_SEL */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); + + /* RG_HDMITXPLL_RESERVE[12:11] */ + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); + + /* TCL_EN */ + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN); + + return 0; +} + +static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, unsigned char prediv, + unsigned char fbkdiv_high, + unsigned long fbkdiv_low, + unsigned char fbkdiv_hs3, unsigned char posdiv1, + unsigned char posdiv2, unsigned char txprediv, + unsigned char txposdiv, + unsigned char digital_div) +{ + unsigned char txposdiv_value; + unsigned char div3_ctrl_value; + unsigned char posdiv_vallue; + unsigned char div_ctrl_value; + unsigned char reserve_3_2_value; + unsigned char prediv_value; + unsigned char reserve13_value; + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + void __iomem *regs =3D hdmi_phy->regs; + + mtk_hdmi_pll_select_source(hw); + + mtk_hdmi_pll_performance_setting(hw); + + mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SE= L, 0x2); + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); + mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2); + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); + mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + + /* TXPOSDIV */ + txposdiv_value =3D ilog2(txposdiv); + + mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv= _value); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN); + + /* TXPREDIV */ + switch (txprediv) { + case 2: + div3_ctrl_value =3D 0x0; + posdiv_vallue =3D 0x0; + break; + case 4: + div3_ctrl_value =3D 0x0; + posdiv_vallue =3D 0x1; + break; + case 6: + div3_ctrl_value =3D 0x1; + posdiv_vallue =3D 0x0; + break; + case 12: + div3_ctrl_value =3D 0x1; + posdiv_vallue =3D 0x1; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CT= RL, div3_ctrl_value); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv= _vallue); + + /* POSDIV1 */ + switch (posdiv1) { + case 5: + div_ctrl_value =3D 0x0; + break; + case 10: + div_ctrl_value =3D 0x1; + break; + case 12: + div_ctrl_value =3D 0x2; + break; + case 15: + div_ctrl_value =3D 0x3; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_= ctrl_value); + + /* DE add new setting */ + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); + + /* POSDIV2 */ + switch (posdiv2) { + case 1: + reserve_3_2_value =3D 0x0; + break; + case 2: + reserve_3_2_value =3D 0x1; + break; + case 4: + reserve_3_2_value =3D 0x2; + break; + case 6: + reserve_3_2_value =3D 0x3; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2= , reserve_3_2_value); + + /* DE add new setting */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0= , 0x2); + + /* PREDIV */ + prediv_value =3D ilog2(prediv); + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv= _value); + + /* FBKDIV_HS3 */ + reserve13_value =3D ilog2(fbkdiv_hs3); + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13,= reserve13_value); + + /* FBDIV */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, f= bkdiv_high); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fb= kdiv_low); + + /* Digital DIVIDER */ + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); + + if (digital_div =3D=3D 1) { + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); + } else { + mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); + mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div -= 1); + } + + return 0; +} + +static int mtk_hdmi_pll_calculate_params(struct clk_hw *hw, unsigned long = rate, + unsigned long parent_rate) +{ + int ret; + u64 tmds_clk, pixel_clk; + /* pll input source frequency */ + u64 da_hdmitx21_ref_ck; + /* ICO output clk */ + u64 ns_hdmipll_ck; + /* source clk for Display digital */ + u8 digital_div; + u64 pcw; + u32 fbkdiv_high; + u32 fbkdiv_low; + u8 txprediv, txposdiv, posdiv1, posdiv2; + /* prediv is always 1 */ + u8 prediv =3D 1; + /* fbkdiv_hs3 is always 1 */ + u8 fbkdiv_hs3 =3D 1; + u8 txpredivs[4] =3D { 2, 4, 6, 12 }; + int i; + + pixel_clk =3D rate; + tmds_clk =3D pixel_clk; + + if (tmds_clk < 25000000 || tmds_clk > 594000000) + return -EINVAL; + + /* in Hz */ + da_hdmitx21_ref_ck =3D 26000000UL; + + /* TXPOSDIV stage treatment: + * 0M < TMDS clk < 54M /8 + * 54M <=3D TMDS clk < 148.35M /4 + * 148.35M <=3DTMDS clk < 296.7M /2 + * 296.7 <=3DTMDS clk <=3D 594M /1 + */ + if (tmds_clk < 54000000UL) + txposdiv =3D 8; + else if (tmds_clk < 148350000UL) + txposdiv =3D 4; + else if (tmds_clk < 296700000UL) + txposdiv =3D 2; + else if (tmds_clk <=3D 594000000UL) + txposdiv =3D 1; + else + return -EINVAL; + + /* calculate txprediv: can be 2, 4, 6, 12 + * ICO clk =3D 5*TMDS_CLK*TXPOSDIV*TXPREDIV + * ICO clk constraint: 5G =3D< ICO clk <=3D 12G + */ + for (i =3D 0; i < ARRAY_SIZE(txpredivs); i++) { + ns_hdmipll_ck =3D 5 * tmds_clk * txposdiv * txpredivs[i]; + if (ns_hdmipll_ck >=3D 5000000000UL && + ns_hdmipll_ck <=3D 12000000000UL) + break; + } + if (i =3D=3D (ARRAY_SIZE(txpredivs) - 1) && + (ns_hdmipll_ck < 5000000000UL || ns_hdmipll_ck > 12000000000UL)) { + return -EINVAL; + } + if (i =3D=3D ARRAY_SIZE(txpredivs)) + return -EINVAL; + + txprediv =3D txpredivs[i]; + + /* PCW calculation: FBKDIV + * formula: pcw=3D(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; + * RG_HDMITXPLL_FBKDIV[32:0]: + * [32,24] 9bit integer, [23,0]:24bit fraction + */ + pcw =3D div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, + da_hdmitx21_ref_ck / fbkdiv_hs3); + + if (pcw > GENMASK_ULL(32, 0)) + return -EINVAL; + + fbkdiv_high =3D FIELD_GET(GENMASK_ULL(63, 32), pcw); + fbkdiv_low =3D FIELD_GET(GENMASK(31, 0), pcw); + + /* posdiv1: + * posdiv1 stage treatment according to color_depth: + * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5, + * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10 + */ + posdiv1 =3D 10; + posdiv2 =3D 1; + + /* Digital clk divider, max /32 */ + digital_div =3D div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk= ); + if (!(digital_div <=3D 32 && digital_div >=3D 1)) + return -EINVAL; + + ret =3D mtk_hdmi_pll_set_hw(hw, prediv, fbkdiv_high, fbkdiv_low, + fbkdiv_hs3, posdiv1, posdiv2, txprediv, + txposdiv, digital_div); + if (ret) + return -EINVAL; + + return 0; +} + +static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) +{ + unsigned char data_channel_bias, clk_channel_bias; + unsigned char impedance, impedance_en; + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + unsigned long tmds_clk; + unsigned long pixel_clk =3D hdmi_phy->pll_rate; + void __iomem *regs =3D hdmi_phy->regs; + + tmds_clk =3D pixel_clk; + + /* bias & impedance setting: + * 3G < data rate <=3D 6G: enable impedance 100ohm, + * data channel bias 24mA, clock channel bias 20mA + * pixel clk >=3D HD, 74.175MHZ <=3D pixel clk <=3D 300MHZ: + * enalbe impedance 100ohm + * data channel 20mA, clock channel 16mA + * 27M =3D< pixel clk < 74.175: disable impedance + * data channel & clock channel bias 10mA + */ + + /* 3G < data rate <=3D 6G, 300M < tmds rate <=3D 594M */ + if (tmds_clk > 300000000UL && tmds_clk <=3D 594000000UL) { + data_channel_bias =3D 0x3c; /* 24mA */ + clk_channel_bias =3D 0x34; /* 20mA */ + impedance_en =3D 0xf; + impedance =3D 0x36; /* 100ohm */ + } else if (pixel_clk >=3D 74175000UL) { + data_channel_bias =3D 0x34; /* 20mA */ + clk_channel_bias =3D 0x2c; /* 16mA */ + impedance_en =3D 0xf; + impedance =3D 0x36; /* 100ohm */ + } else if (pixel_clk >=3D 27000000UL) { + data_channel_bias =3D 0x14; /* 10mA */ + clk_channel_bias =3D 0x14; /* 10mA */ + impedance_en =3D 0x0; + impedance =3D 0x0; + } else { + return -EINVAL; + } + + /* bias */ + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_= channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_= channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_= channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_= channel_bias); + + /* impedance */ + mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedan= ce_en); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, imp= edance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, imp= edance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, imp= edance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, im= pedance); + + return 0; +} + +static int mtk_hdmi_pll_prepare(struct clk_hw *hw) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + void __iomem *regs =3D hdmi_phy->regs; + + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); + + mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN); + + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN); + + mtk_hdmi_pll_drv_setting(hw); + + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); + + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); + usleep_range(5, 10); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); + usleep_range(5, 10); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + usleep_range(30, 50); + return 0; +} + +static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + void __iomem *regs =3D hdmi_phy->regs; + + mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); + + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + usleep_range(10, 20); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); + usleep_range(10, 20); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); +} + +static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + + dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate, + parent_rate); + + return mtk_hdmi_pll_calculate_params(hw, rate, parent_rate); +} + +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + + hdmi_phy->pll_rate =3D rate; + return rate; +} + +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); + + return hdmi_phy->pll_rate; +} + +static const struct clk_ops mtk_hdmi_pll_ops =3D { + .prepare =3D mtk_hdmi_pll_prepare, + .unprepare =3D mtk_hdmi_pll_unprepare, + .set_rate =3D mtk_hdmi_pll_set_rate, + .round_rate =3D mtk_hdmi_pll_round_rate, + .recalc_rate =3D mtk_hdmi_pll_recalc_rate, +}; + +static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on) +{ + void __iomem *regs =3D hdmi_phy->regs; + + if (on) + mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); + else + mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); +} + +static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) +{ + vtx_signal_en(hdmi_phy, true); + usleep_range(100, 150); +} + +static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) +{ + vtx_signal_en(hdmi_phy, false); +} + +static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opt= s *opts) +{ + struct phy_configure_opts_dp *dp_opts =3D &opts->dp; + struct mtk_hdmi_phy *hdmi_phy =3D phy_get_drvdata(phy); + int ret; + + ret =3D clk_set_rate(hdmi_phy->pll, dp_opts->link_rate); + if (ret) + return ret; + + mtk_mt8195_phy_tmds_high_bit_clk_ratio(hdmi_phy, false); + + return ret; +} + +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf =3D { + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, + .hdmi_phy_clk_ops =3D &mtk_hdmi_pll_ops, + .hdmi_phy_enable_tmds =3D mtk_hdmi_phy_enable_tmds, + .hdmi_phy_disable_tmds =3D mtk_hdmi_phy_disable_tmds, + .hdmi_phy_configure =3D mtk_hdmi_phy_configure, +}; + +MODULE_AUTHOR("Can Zeng "); +MODULE_DESCRIPTION("MediaTek MT8195 HDMI PHY Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.h new file mode 100644 index 000000000000..c7b364e7cfbb --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2022 BayLibre, SAS + */ + +#ifndef _MTK_HDMI_PHY_8195_H +#define _MTK_HDMI_PHY_8195_H + +#include +#include +#include + +#define PCW_DECIMAL_WIDTH 24 + +#define HDMI20_CLK_CFG 0x70 +#define REG_TXC_DIV GENMASK(31, 30) + +#define HDMI_1_CFG_0 0x00 +#define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5) +#define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20) +#define RG_HDMITX21_DRV_EN GENMASK(27, 24) +#define RG_HDMITX21_SER_EN GENMASK(31, 28) + +#define HDMI_1_CFG_1 0x04 +#define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14) +#define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20) +#define RG_HDMITX21_DRV_IBIAS_D2 GENMASK(31, 26) + +#define HDMI_1_CFG_10 0x40 +#define RG_HDMITXPLL_REF_CK_SEL GENMASK(2, 1) +#define RG_HDMITX21_VREF_SEL BIT(4) +#define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10) +#define RG_HDMITX21_BIAS_PE_BG_VREF_SEL GENMASK(16, 15) +#define RG_HDMITX21_BG_PWD BIT(20) + +#define HDMI_1_CFG_2 0x08 +#define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8) +#define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14) +#define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20) +#define RG_HDMITX21_DRV_IMP_CLK_EN1 GENMASK(31, 26) + +#define HDMI_1_CFG_3 0x0c +#define RG_HDMITX21_CKLDO_EN BIT(3) +#define RG_HDMITX21_SLDOLPF_EN BIT(7) +#define RG_HDMITX21_SLDO_EN GENMASK(11, 8) + +#define HDMI_1_CFG_6 0x18 +#define RG_HDMITX21_D2_DRV_OP_EN BIT(8) +#define RG_HDMITX21_D1_DRV_OP_EN BIT(9) +#define RG_HDMITX21_D0_DRV_OP_EN BIT(10) +#define RG_HDMITX21_CK_DRV_OP_EN BIT(11) +#define RG_HDMITX21_FRL_EN BIT(12) +#define RG_HDMITX21_FRL_CK_EN BIT(13) +#define RG_HDMITX21_FRL_D0_EN BIT(14) +#define RG_HDMITX21_FRL_D1_EN BIT(15) +#define RG_HDMITX21_FRL_D2_EN BIT(16) +#define RG_HDMITX21_INTR_CAL GENMASK(22, 18) +#define RG_HDMITX21_TX_POSDIV GENMASK(27, 26) +#define RG_HDMITX21_TX_POSDIV_EN BIT(28) +#define RG_HDMITX21_BIAS_EN BIT(29) + +#define HDMI_1_CFG_9 0x24 +#define RG_HDMITX21_SLDO_VREF_SEL GENMASK(5, 4) + +#define HDMI_1_PLL_CFG_0 0x44 +#define RG_HDMITXPLL_HREN GENMASK(13, 12) +#define RG_HDMITXPLL_IBAND_FIX_EN BIT(24) +#define RG_HDMITXPLL_LVR_SEL GENMASK(27, 26) +#define RG_HDMITXPLL_BP2 BIT(30) +#define RG_HDMITXPLL_TCL_EN BIT(31) + +#define HDMI_1_PLL_CFG_1 0x48 +#define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0) +#define RG_HDMITXPLL_RESERVE_BIT3_2 GENMASK(3, 2) +#define RG_HDMITXPLL_RESERVE_BIT12_11 GENMASK(12, 11) +#define RG_HDMITXPLL_RESERVE_BIT13 BIT(13) +#define RG_HDMITXPLL_RESERVE_BIT14 BIT(14) + +#define HDMI_1_PLL_CFG_2 0x4c +#define RG_HDMITXPLL_BC GENMASK(28, 27) +#define RG_HDMITXPLL_IC GENMASK(26, 22) +#define RG_HDMITXPLL_BR GENMASK(21, 19) +#define RG_HDMITXPLL_IR GENMASK(18, 14) +#define RG_HDMITXPLL_BP GENMASK(13, 10) +#define RG_HDMITXPLL_HIKVCO BIT(29) +#define RG_HDMITXPLL_PWD BIT(31) + +#define HDMI_1_PLL_CFG_3 0x50 +#define RG_HDMITXPLL_FBKDIV_LOW GENMASK(31, 0) + +#define HDMI_1_PLL_CFG_4 0x54 +#define DA_HDMITXPLL_ISO_EN BIT(1) +#define DA_HDMITXPLL_PWR_ON BIT(2) +#define RG_HDMITXPLL_POSDIV_DIV3_CTRL BIT(21) +#define RG_HDMITXPLL_POSDIV GENMASK(23, 22) +#define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24) +#define RG_HDMITXPLL_PREDIV GENMASK(29, 28) +#define RG_HDMITXPLL_FBKDIV_HIGH BIT(31) + +#define HDMI_ANA_CTL 0x7c +#define REG_ANA_HDMI20_FIFO_EN BIT(16) + +#define HDMI_CTL_3 0xcc +#define REG_HDMITXPLL_DIV GENMASK(4, 0) +#define REG_HDMITX_REF_XTAL_SEL BIT(7) +#define REG_HDMITX_REF_RESPLL_SEL BIT(9) +#define REG_PIXEL_CLOCK_SEL BIT(10) +#define REG_HDMITX_PIXEL_CLOCK BIT(23) + +#endif /* MTK_HDMI_PHY_8195_H */ diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy= -mtk-hdmi.c index 32f713301768..d2e824771f9d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -161,6 +161,9 @@ static const struct of_device_id mtk_hdmi_phy_match[] = =3D { { .compatible =3D "mediatek,mt8173-hdmi-phy", .data =3D &mtk_hdmi_phy_8173_conf, }, + { .compatible =3D "mediatek,mt8195-hdmi-phy", + .data =3D &mtk_hdmi_phy_8195_conf, + }, {}, }; MODULE_DEVICE_TABLE(of, mtk_hdmi_phy_match); diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy= -mtk-hdmi.h index f5aac9d352d8..9dfb725fc57f 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -44,6 +44,7 @@ struct mtk_hdmi_phy { =20 struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); =20 +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf; extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf; =20 --=20 2.38.1