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[90.5.10.86]) by smtp.gmail.com with ESMTPSA id le8-20020a170907170800b0096f803afbe3sm5993654ejc.66.2023.05.29.07.36.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 07:36:37 -0700 (PDT) From: Guillaume Ranquet Date: Mon, 29 May 2023 16:30:58 +0200 Subject: [PATCH v4 1/8] dt-bindings: display: mediatek: add MT8195 hdmi bindings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220919-v4-1-687f09a06dd9@baylibre.com> References: <20220919-v4-0-687f09a06dd9@baylibre.com> In-Reply-To: <20220919-v4-0-687f09a06dd9@baylibre.com> To: Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , CK Hu , Jitao shi Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski , AngeloGioacchino Del Regno , mac.shen@mediatek.com, stuart.lee@mediatek.com, Guillaume Ranquet X-Mailer: b4 0.13-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mt8195 SoC bindings for hdmi and hdmi-ddc On mt8195 the ddc i2c controller is part of the hdmi IP block and thus has = no specific register range, power domain or interrupt, making it simpler than the legacy "mediatek,hdmi-ddc" binding. Signed-off-by: Guillaume Ranquet --- .../bindings/display/mediatek/mediatek,hdmi.yaml | 59 ++++++++++++++++++= ---- .../display/mediatek/mediatek,mt8195-hdmi-ddc.yaml | 45 +++++++++++++++++ 2 files changed, 93 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hd= mi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.= yaml index b90b6d18a828..4f62e6b94048 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt7623-hdmi - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi + - mediatek,mt8195-hdmi =20 reg: maxItems: 1 @@ -29,18 +30,10 @@ properties: maxItems: 1 =20 clocks: - items: - - description: Pixel Clock - - description: HDMI PLL - - description: Bit Clock - - description: S/PDIF Clock + maxItems: 4 =20 clock-names: - items: - - const: pixel - - const: pll - - const: bclk - - const: spdif + maxItems: 4 =20 phys: maxItems: 1 @@ -58,6 +51,9 @@ properties: description: | phandle link and register offset to the system configuration registe= rs. =20 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -86,9 +82,50 @@ required: - clock-names - phys - phy-names - - mediatek,syscon-hdmi - ports =20 +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-hdmi + then: + properties: + clocks: + items: + - description: APB + - description: HDCP + - description: HDCP 24M + - description: Split HDMI + clock-names: + items: + - const: hdmi_apb_sel + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + required: + - power-domains + else: + properties: + clocks: + items: + - description: Pixel Clock + - description: HDMI PLL + - description: Bit Clock + - description: S/PDIF Clock + + clock-names: + items: + - const: pixel + - const: pll + - const: bclk + - const: spdif + + required: + - mediatek,syscon-hdmi + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt= 8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/med= iatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..84c096835b47 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hd= mi-ddc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-d= dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + mediatek,hdmi: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the mt8195 hdmi controller + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + hdmiddc0: i2c { + compatible =3D "mediatek,mt8195-hdmi-ddc"; + mediatek,hdmi =3D <&hdmi0>; + clocks =3D <&clk26m>; + }; + +... --=20 2.40.0